Cypress Semiconductor PALC22V10B-15JC, PALC22V10B-15JI, PALC22V10B-15PC, PALC22V10B-15WC, PALC22V10B-15WI Datasheet
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Reprogrammable CMOS PAL® Device
PALC22V10B
This is an abbreviated datasheet. Contact a Cypress representative for complete specifications. For new designs,
please refer to the PALCE22V10
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-03018 Rev. ** Revised March 6, 1997
Features
• Advanced second generation PAL architecture
• Low power
—90 mA max. standard
—100 mA max. military
• CMOS EPROM technology for reprogrammability
• Variable product terms
—2 x (8 through 16) product terms
• User-programmable macrocell
—Output polarity control
—Individually selectable for registered or combinato-
rial operation
—15 ns commercial and industrial
10 ns t
CO
10 ns t
S
15 ns t
PD
50 MHz
—15 ns and “20 ns” military
10/15 ns t
CO
10/17 ns t
S
15/20 ns t
PD
50/31 MHz
• Up to 22 input terms and 10 outputs
• Enhanced test features
—Phantom array
—Top test
—Bottom test
—Preload
• High reliability
—Proven EPROM technology
—100% programming and functional testing
• Windowed DIP, windowed LCC, DIP, LCC, PLCC avail-
able
Functional Description
The Cypress PALC22V10B is a CMOS second-generation
programmable logic array device. It is implemented with the
familiar sum-of-products (AND-OR) logic structure and a new
concept, the “Programmable Macrocell.”
The P ALC22V10B is ex ecuted in a 24-pin 300 -mil molded DIP,
a 300-mil windowed cerDIP, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier,
and provides up to 22 inputs and 10 outputs. When the windowed cerDIP is exposed to UV light, the 22V10B is erased
and can then be reprogra mmed. The programmable macrocell
provides the capabi lity of de fining the archit ecture of eac h output individually. Each of the 10 pot ential outp uts may be spec ified as “registered” or “combinatorial.” Polari ty o f eac h o utp ut
may also be individually
LogicBlock Diagram(PDIP/CDIP)
V10B–1
Macrocell
8
10 12 14 16 16 14 12 10 8
11 10 9 8 7 6 5 4 3 2 112
13 14 15 16 17 18 19 20 21 22 23 24
Preset
PROGRAMMABLE
ANDARRAY
(132X44)
IIIIIIIIIICP/I
V
SS
II/O9I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
V
CC
Reset
Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell
PALC22V10B
Document #: 38-03018 Rev. ** Page 2 of 3
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
PinConfigurations
Top View
PLCCLCC
Top View
5
6
7
8
9
10
11
4 3 2 282726
12131415161718
25
24
23
22
21
20
19
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
2
3
4
5
6
7
25
24
23
22
21
20
19
5
6
7
8
9
10
11
121314 1516 1718
4 3 2 2827 26
I/O
I/O
I/O
I/O
I/O
I/O
2
3
4
5
6
7
I
I
I
I
I
I
I9I
CP/IVI/O
I/O
8
I/O
I/O
I
V
I
I
SS
IICP/IVI/O
I/O
0
1
0
1
CC
CC
9
8
I/O
I/O
I
V
I
I
SS
1
1
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
V10B–2
V10B–3
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