CYP15G0101DXB Evaluation
Board User’s Guide
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
August 12, 2003
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CYP15G0101DXB Evaluation Board User’s Guide
Table of Contents
1. Overview ................................................................................................................................................................................. 5
2. Kit Contents ............................................................................................................................................................................ 5
3. Features of the CYP15G0101DXB ........................................................................................................................................ 5
4. Functional Description of CYP15G0101DXB ....................................................................................................................... 6
5. Board Layout, Photograph and Pin Descriptions ............................................................................................................... 8
6. Test Modes ........................................................................................................................................................................... 13
6.1 Adjusting Settings on the Board .......................................................................................................................................14
6.2 BIST Test Set-up .................................................................................................................................................................15
6.2.1 BIST Internal Loopback Mode ....................................................................................................................................... 15
6.2.1.1 Equipment Required .................................................................................................................................................... 15
6.2.1.2 Test Equipment Set-up .................................................................................................................................................16
6.2.1.3 Test Set-up ................................................................................................................................................................... 16
6.2.2 BIST External Loopback Mode ...................................................................................................................................... 18
6.2.2.1 Equipment Required .................................................................................................................................................... 18
6.2.2.2 Test Set-up ................................................................................................................................................................... 18
6.3 Parallel Data In – Parallel Data Out Mode .........................................................................................................................19
6.3.1 Encoded Mode ................................................................................................................................................................ 19
6.3.1.1 Equipment Required .................................................................................................................................................... 19
6.3.1.2 Test Set-up ................................................................................................................................................................... 19
6.3.1.3 Result Verification ....................................................................................................................................................... 20
6.3.2 Unencoded Mode (Parallel-In – Parallel-Out) ............................................................................................................... 20
6.3.2.1 Equipment Required .................................................................................................................................................... 20
6.3.2.2 Test Set-up ................................................................................................................................................................... 20
6.3.2.3 Result Verification ....................................................................................................................................................... 22
6.3.3 Operational Variations for Parallel-In–Parallel-Out Mode ........................................................................................... 22
6.3.3.1 Equipment Required .................................................................................................................................................... 22
6.3.3.2 Test Set-up and Result Verification ........................................................................................................................... 22
7. Schematic Diagram, PCB Layout, and Bill of Materials (BOM) ....................................................................................... 23
Appendix A. Schematic Diagram of CYP15G0101DXB Evaluation Board .......................................................................... 24
Appendix B. PCB Layout for CYP15G0101DXB Evaluation Board ..................................................................................... 30
Appendix C. Bill Of Materials (BOM) CYP15G0101DXB Evaluation Board ......................................................................... 39
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CYP15G0101DXB Evaluation Board User’s Guide
List of Figures
Figure 1. CYP15G0101DXB Transmitter Section Block Diagram .......................................................................................... 6
Figure 2. CYP15G0101DXB HOTLink II™ Block Diagram ...................................................................................................... 6
Figure 3. CYP15G0101DXB Receiver Section Block Diagram ............................................................................................... 7
Figure 4. CYP15G0101DXB-EVAL Skeletal View ..................................................................................................................... 8
Figure 5. Pin Description of CYP15G0101DXB-EVAL ............................................................................................................. 9
Figure 6. The BIST Mode Operation ....................................................................................................................................... 13
Figure 7. Control Switches for Test Set-up ........................................................................................................................... 14
Figure 8. Controlling REFCLK Settings ................................................................................................................................. 14
Figure 9. Controlling SWT1 Dip Switches Settings .............................................................................................................. 15
Figure 10. Controlling JT7 Pins Settings ............................................................................................................................... 15
Figure 11. Pictorial Representation of the Internal BIST Set-up ......................................................................................... 16
Figure 12. Signal on RXST1 when BIST is Successful ......................................................................................................... 17
Figure 13. The Eye Diagram through the Signal Analyzer ................................................................................................... 18
Figure 14. Coaxial Cable Connection for External BIST Mode ............................................................................................ 18
Figure 15. Generated Clock, Data and Control Signal from DG2020 .................................................................................. 19
Figure 16. Adding Two Framing Characters to Data Stream ............................................................................................... 22
Figure 17. CYP15G0101DXB-EVAL Top Level Schematics .................................................................................................. 25
Figure 18. CYP15G0101DXB-EVAL Terminated Transmitter & Receiver Blocks ............................................................... 26
Figure 19. CYP15G0101DXB-EVAL Terminated Control Signals Block .............................................................................. 27
Figure 20. CYP15G0101DXB-EVAL Transmit and Receive Clock Schematics .................................................................. 28
Figure 21. CYP15G0101DXB-EVAL Input Power Schematics .............................................................................................. 29
Figure 22. CYP15G0101DXB-EVAL Top Layout .................................................................................................................... 31
Figure 23. CYP15G0101DXB-EVAL Bottom Layout .............................................................................................................. 32
Figure 24. CYP15G0101DXB-EVAL Top Layer Silk Layout .................................................................................................. 33
Figure 25. CYP15G0101DXB-EVAL Bottom Layer Silk Layout ............................................................................................ 34
Figure 26. CYP15G0101DXB-EVAL Top Layer Solder Mask Layout ................................................................................... 35
Figure 27. CYP15G0101DXB-EVAL Bottom Layer Solder Mask Layout ............................................................................. 36
Figure 28. CYP15G0101DXB-EVAL Power Plane Layout ..................................................................................................... 37
Figure 29. CYP15G0101DXB-EVAL Ground Plane Layout ................................................................................................... 38
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CYP15G0101DXB Evaluation Board User’s Guide
List of Tables
Table 1. Description of Connectors of the CYP15G0101DXB Evaluation Board ............................................................... 10
Table 2. Description of Control Pins in JT7 ........................................................................................................................... 11
Table 3. The High, Mid, and Low Levels on JT32 .................................................................................................................. 15
Table 4. The Levels of Different Static Signals on JT7 for BIST Mode ............................................................................... 16
Table 5. Channel Enabling Controls ...................................................................................................................................... 17
Table 6. The Levels of Static Signals on JT32 for Parallel In-Parallel Out Mode (Encoded) ............................................ 20
Table 7. The Levels of Static Signals on JT32 for Parallel In-Parallel Out Mode (Unencoded) ........................................ 21
Table 8. Output Register Bit Assignments ............................................................................................................................ 21
Table 9. Input Register Bit Assignments ............................................................................................................................... 21
Table 10. Operation Specification of CYP15G0101DXB Eval Board ................................................................................... 23
Table 11. CYP15G0101DXB Eval Board Bill Of Materials ..................................................................................................... 40
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CYP15G0101DXB Evaluation Board User’s Guide
1. Overview
The CYP15G0101DXB single-channel HOTLink II™ Transceiver is a point-to-point or point-to-multipoint communications building
block allowing the transfer of data over high-speed serial links at signaling speeds ranging from 195 to 1500 MBaud.
This document describes the operation and interface of the CYP15G0101DXB evaluation board. The evaluation board allows
users to become familiar with the functionality of the CYP15G0101DXB. Figure 4 gives a skeletal view of the evaluation board.
2. Kit Contents
• CYP15G0101DXB evaluation board (CYP15G0101DXB-EVAL)
• Dear Customer letter
• a CD containing
— CYP15G0101DXB data sheet
— CYP15G0101DXB-EVAL user’s guide
— HOTLink II application notes
— BSDL model
— CYP15G0101_EVAL.PDA.
3. Features of the CYP15G0101DXB
• Second-generation HOTLink® technology
•GbE-, FC-, ESCON-
• 8B/10B-coded or 10-bit unencoded
• Selectable parity check/generate
• Selectable input clocking options
• Selectable output clocking options
• MultiFrame™ receive framer provides alignment to
— Bit, byte, half-word, word, multi-word
— COMMA or Full K28.5 detect
— Single or multi-byte framer for byte alignment
— Low-latency option
• Skew alignment support for multiple bytes of offset
• Synchronous LVTTL parallel input interface
• Synchronous LVTTL parallel output interface
• 195-to-1500 MBaud serial signaling rate
• Internal PLLs with no external PLL components
• Dual differential PECL-compatible serial inputs
• Dual differential PECL-compatible serial outputs
• JTAG Boundary Scan
• Built In Self Testing (BIST) for at-speed link testing
• Link Quality Indicator
• Low power (1W typical)
• 100-ball BGA
•0.25µ BICMOS technology
®
, DVB-ASI-, SMPTE259-, and SMPTE292-compliant
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CYP15G0101DXB Evaluation Board User’s Guide
4. Functional Description of CYP15G0101DXB
Figure 2 shows the block diagram of CYP15G0101DXB, which has a pair of transmit and receive channels.
Figure 1 shows the transmitter section of CYP15G0101DXB.
TXRATE
SPDSEL
TXCLKO+
TXCLKO–
TXMODE[1:0]
TXCKSEL
TXPER
SCSEL
TXD[7:0]
TXOP
TXCT[1:0]
TXCLK
TXRST
PARCTL
TRANSMIT PLL
CLOCK MULTIPLIER
CHARACTER-RATE CLOCK
2
8
2
INPUT
HML
REGISTER
TRANSMIT
MODE
12
PHASE-ALIGN
BUFFER
BIT-RATE CLOCK
12
PARITY
BIST ENABLE
12
CHECK
LATCH
CHARACTER-RATE CLOCK
OUTPUT
4
8B/10B
BIST LFSR
10
ENABLE
LATCH
SHIFTER
PARITY CONTROL
BISTLE
BOE[7:0]
RBIST
OELE
8
OUT1+
OUT1–
OUT2+
OUT2–
TXLB
Figure 1. CYP15G0101DXB Transmitter Section Block Diagram
RXST[2:0]
TXCT[1:0]
TXD[7:0]
X10
Phase-Align Buffer
Encoder
8B/10B
RXD[7:0]
x11
Elasticity Buffer
Decoder
8B/10B
Framer
Serializer
TX
OUT1±
OUT2±
Deserializer
RX
IN1±
IN2±
Figure 2. CYP15G0101DXB HOTLink II™ Block Diagram
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CYP15G0101DXB Evaluation Board User’s Guide
Figure 3 shows the receive section of the CYP15G0101DXB. The serial data input passes through the framer (where the
recovered bit stream is framed to framing character), the 10B/8B Decoder and the elasticity buffer.
RXLE
BOE[7:0]
CHARACTER RATE CLOCK
SDASEL
LPEN
INSEL
IN1+
IN1–
IN2+
IN2–
TXLBA
FRAMCHAR
RFEN
RFMODE
DECMODE
RXCKSEL
RXMODE
RXRATE
RBIST
RX-PLL Enable
L
ATCH
R
ECEIVE
S
IGNAL
M
ONITOR
C
LOCK
D
ATA
R
ECOVERY
PLL
PARITY CONTROL
&
SHIFTER
10B/8B
FRAMER
BIST
C
LOCK
S
ELECT
JTAG
B
OUNDARY
S
CAN
C
ONTROLLER
UFFER
B
LASTICITY
E
UTPUT
O
.
.
2
Figure 3. CYP15G0101DXB Receiver Section Block Diagram
TMS
TCLK
TDI
TDO
LFI
8
EGISTER
3
R
RXD[7:0]
RXOP
RXST[2:0]
RXCLK+
RXCLK–
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CYP15G0101DXB Evaluation Board User’s Guide
5. Board Layout, Photograph and Pin Descriptions
Figure 4 shows the skeletal view of the CYP15G0101DX board.
Figure 4. CYP15G0101DXB-EVAL Skeletal View
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CYP15G0101DXB Evaluation Board User’s Guide
Figure 5 shows the different connectors and pins of the evaluation board for CYP15G0101DXB.
Figure 5. Pin Description of CYP15G0101DXB-EVAL
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CYP15G0101DXB Evaluation Board User’s Guide
Table 1 gives a brief description of the connectors of the evaluation board.
Table 1. Description of Connectors of the CYP15G0101DXB Evaluation Board
Connectors Signals Description
JT1, JT2 SERIN1+
JT3, JT4 SEROUT1+
JT7 RX and TX side Control
Signals
Power Supply
JT8 VCC Banana Jack
JT13 GND Banana Jack
DT1 Power On Indicator Indicates if the power supply is ON. The LED glows when the power supply goes
SMA Connectors for SERIN± (one pair per primary input)
• PECL compatible primary differential serial data inputs
• Routed through 50-ohm Impedance
• AC coupling capacitors present
• 100-ohm differential Load present
SMA connectors for SEROUT+ (one pair per primary output)
• CML compatible primary differential serial data outputs
• Routed through 50-ohm Impedance
• AC coupling capacitors present
Please refer to Table 2: Description of Control Pins in JT7 on page 11.
• +3.3 V DC
• Ground
ON.
JT11 JTAG Interface Note: For CYP15G0101DXB, there is no dedicated JTAG reset. The JTAG logic
will be reset on power-on.
JT10 TXD[7:0]
TXCT[1:0]
TXOP
JT9 Clock Outputs and
Controls
LVTTL Input
TXD[7:0]
• Transmit Data Input
• 50 Ohms Impedance terminated to 50 ohms load
TXCT[1:0]
• Transmit control signals
TXOP
• Transmit Path Odd parity
• TXPER
•RXCLK*
•RXCLK
•TXCLK
•XTAL_EN
— A shunt across this implies that the onboard crystal clock is disabled.
•XTAL_OUT
— A shunt across this implies that the crystal clock on the board is used as
REFCLK.
•REFCLK
— A shunt across this implies that external REFCLK is used. The external
REFCLK inputs are JT12 and JT14.
• REFCLK*
•TXCLKO
•TXCLKO*
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CYP15G0101DXB Evaluation Board User’s Guide
Table 1. Description of Connectors of the CYP15G0101DXB Evaluation Board (continued)
Connectors Signals Description
JT12 REFCLK External differential Reference clock. For single ended REFCLK input, apply an
JT14 REFCLK*
DT2 LFI LED Indicator
SWT1 BOE[1:0]
RXLE
OELE
BISTLE
TRSTZ
JT5 Optical Controls Controls for optical modules
XT1 The optical Interface Options for small form factor pluggable (SFP) optical modules.
JT6 RXD[7:0]
RXST[2:0]
RXOP
UT1 CYP15G0101DXB
LVTTL clock signal to REFCLK input in JT12.
BOE
• BIST, serial output, and receive channel enables.
• LVTTL Input
RXLE (Receive channel enable latch enable)
• Active HIGH
OELE (Serial output driver enable latch enable)
• Active HIGH
BISTLE (Transmit and Receive BIST Latch Enable)
• Active HIGH
TRSTZ
• Active LOW
LVTTL Output
RXD[7:0]
• Receive Data output
RXST[2:0]
• Receive Parallel Status output
RXOP
• Receive Path Odd parity
Table 2 gives a detailed description of all the control pins in JT7.
Many of the static control signals are of 3-level select. This means that they operate at three voltage levels, which are termed as
• HIGH (Direct connection to V
CC
)
• MID (Open or allowed to float)
• LOW (Direct connection to V
, i.e., GND).
SS
In JT7 on the Eval board, these levels are implemented as follows:
• HIGH – Place a shunt across columns 1 and 2
• MID – Don’t place any shunt
• LOW – Place a shunt across columns 2 and 3.
Table 2. Description of Control Pins in JT7
Pin Name Characteristics
TXMODE0,
TXMODE1
Transmit mode (two inputs)
3-Level Select
• Configure LL for Encoder bypass
• LM and LH are reserved for testing (we will be using LM in our tests)
• All other combinations along with the selection of SCSEL are for encoder control. (Please
refer to the data sheet for more details.)
TXCKSEL Transmit Clock Select (1 input)
3-Level Select
• When L, REFCLK is used by all the input registers.
• When M or H, TXCLK is used.
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CYP15G0101DXB Evaluation Board User’s Guide
Table 2. Description of Control Pins in JT7 (continued)
Pin Name Characteristics
TXRATE LVTTL Input
• When H, the transmit PLL multiplies REFCLK by 20 to generate the bit rate clock.
• When L, the transmit PLL multiplies REFCLK by 10 to generate the bit rate clock.
SCSEL Special Character Select
LVTTL Input
Used with the TXMODE[1:0] to
• Either encode special characters
• Or initiate a word sync sequence
TXRST* Transmit Clock Phase Align Buffer Reset
SPDSEL Serial Rate Select
SDASEL Signal Detect Amplitude Level Select
PARCTL Parity check/generate control
RXMODE Receive Operating Mode. This input selects one of two RXST channel status reporting
RXCKSEL Receive Clock Mode.
RFMODE Reframe Mode Select.
FRAMCHAR Framing Character Select.
Active LOW
• L: the Phase-Align Buffer is allowed to adjust its data transfer timing.
• H: the internal phase relationship between the TXCLK and the internal character-rate clock
is fixed.
3-level select
• LOW = 195–400 MBd
• MID = 400–800 MBd
• HIGH = 800–1500 MBd
3-Level Select
• LOW = 140 mV peak-peak differential
• MID = 280 mV peak-peak differential
• HIGH = 420 mV peak-peak differential
3-Level Select
• LOW = Parity checking is disabled
• MID = If encoder/decoder is enabled, inputs are checked for odd parity
• HIGH = If encoder/decoder is enabled, inputs are checked for odd parity
modes.
• L: Status A selected
• M: Reserved for Test
• H: Status B selected
This input is interpreted only when DECMODE is not LOW.
3-Level Select
• L: Output register is clocked by REFCLK.
— RXCLK± presents a buffered/delayed form of REFCLK.
• M: Output register is clocked by the recovered clock.
— RXCLK+ follows the recovered clock as selected by RXRATE.
— The elasticity buffer is bypassed.
• H: Invalid State.
3-Level Select
Please refer to the data sheet for CYP15G0101DXB for detailed information.
3-Level select.
Please refer to the data sheet for CYP15G0101DXB for detailed information.
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CYP15G0101DXB Evaluation Board User’s Guide
Table 2. Description of Control Pins in JT7 (continued)
Pin Name Characteristics
DECMODE Decoder Mode Select.
3-Level Select
• L: Decoder bypassed
• M: Cypress decoder table for special code characters is used.
• H: Alternate decoder table for special code characters is used.
RXRATE Receive Clock Rate Select.
2-Level Select
LVTTL Input
• L: RXCLK+ operates at the recovered channel clock rate
• H: RXCLK+ operates at HALF the recovered channel clock rate
LPEN All-Channel Loop-Back-Enable.
RFEN Reframe Enable for all channels.
INSEL Receive Input Channel Selector.
LVTTL Input
Active HIGH.
When HIGH
• Transmit serial data is internally routed to receive serial data
• All external serial data inputs are ignored
When LOW, the transmit data is not looped back to the receive side.
Active HIGH.
LVTTL Input.
• HIGH - IN1± input is passed into the CDR circuit
• LOW - IN2± input is passed into the CDR circuit
For example, if INSEL is selected as HIGH, IN1± input will be passed into the receiver.
6. Test Modes
The different test modes discussed in this document are as follows:
1. BIST mode
CYP15G0101DXB has the Built-In Self-Test (BIST) capability. The transmit and receive channel contain the BIST Pattern
Generator and Checker respectively.
Figure 6 shows the BIST mode operation.
Ext. BIST
TX
BIST LFSR
RX
Int. BIST
Figure 6. The BIST Mode Operation
The modes described in this document are:
— BIST internal loopback mode
— BIST external loopback mode
BIST LFSR
Parallel Inputs Ignored
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