Cypress Semiconductor CY8C29466, CY8C29566, CY8C29666, CY8C29866 User manual

CY8C29466, CY8C29566
CY8C29666, CY8C29866

PSoC® Programmable System-on-Chip™

1. Features

DIGITAL SYSTEM

SRAM

256 Bytes

Interrupt

Controller

Sleep and
Watchdog

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

Global Digital Interconnect

Global Analog Interconnect

PSoC

CORE

CPU Core (M 8C)

SROM Fla sh 16K

Digital

Block
Array

Multiply
Acc um .

Switch

Mo de

Pump

Internal
Vol ta ge

Ref.

Digital

Clocks

POR and LVD

System Resets

Decimator

SYSTEM RESOURCES

ANALOG SYSTEM

Ana l o g

Ref.

An al og

Inp ut

Mu xin g

I C

2

Por t 4 Por t 3 Po rt 2 Por t 1 Por t 0

Analog
Dr ive r s

System Bus

An alo g

Block
Ar ray

Por t 5

2. Logic Block Diagram

■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate

❐ Low Power at High Speed
❐ 3.0V to 5.25V Operating Voltage
❐ Operating Voltages Down to 1.0V Using On-Chip Switch

Mode Pump (SMP)

❐ Industrial Temperature Range: -40°C to +85°C

■ Advanced Peripherals (PSoC
❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:

• Up to 14-Bit ADCs

• Up to 9-Bit DACs

• Programmable Gain Amplifiers

• Programmable Filters and Comparators

❐ 16 Digital PSoC Blocks Provide:

• 8- to 32-Bit Timers, Counters, and PWMs

• CRC and PRS Modules

• Up to 4 Full-Duplex UARTs

• Multiple SPI™ Masters or Slaves

• Connectable to all GPIO Pins

❐ Complex Peripherals by Combining Blocks

■ Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Oscillator

❐ 24/48 MHz with Optional 32.768 kHz Crystal
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep

■ Flexible On-Chip Memory
❐ 32K Bytes Flash Program Storage 50,000 Erase/Write Cy-

cles

❐ 2K Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash

■ Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Source on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive

Modes on all GPIO

❐ 8 standard analog inputs on GPIO, plus 4 additional analog

inputs with restricted routing

❐ Four 40 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO

®

Blocks)

■ Additional System Resources

2

❐ I

C Slave, Master, and Multi-Master to

400 kHz

❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference

■ Complete Development Tools
❐ Free Development Software

(PSoC Designer™)

❐ Full-Featured, In-Circuit Emulator and

Programmer

❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
❐ Complex Events
❐ C Compilers, Assembler, and Linker

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-12013 Rev. *M Revised January 11, 2010

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3. Contents

Features............................................................................... 1

Logic Block Diagram.......................................................... 1

Contents .............................................................................. 2

PSoC Functional Overview................................................ 3

PSoC Core .................................................................... 3

Digital System ............................................................... 3

Analog System .............................................................. 4

Additional System Resources ....................................... 4

PSoC Device Characteristics ........................................ 5

Getting Started.................................................................... 5

Application Notes .......................................................... 5

Development Kits .......................................................... 5

Training ......................................................................... 5

CYPros Consultants ...................................................... 5

Solutions Library............................................................ 5

Technical Support ......................................................... 5

Development Tools ............................................................ 6

PSoC Designer Software Subsystems.......................... 6

In-Circuit Emulator......................................................... 6

Designing with PSoC Designer ......................................... 7

Select Components ....................................................... 7

Configure Components ................................................. 7

Organize and Connect .................................................. 7

Generate, Verify, and Debug......................................... 7

Document Conventions ..................................................... 8

Acronyms Used ............................................................. 8

Units of Measure ........................................................... 8

Numeric Naming............................................................ 8

Pinouts ................................................................................ 9

28-Pin Part Pinout ......................................................... 9

44-Pin Part Pinout ....................................................... 10

48-Pin Part Pinout ....................................................... 11

100-Pin Part Pinout ......................................................13

100-Pin Part Pinout (On-Chip Debug)......................... 15

Register Conventions ...................................................... 17

Abbreviations Used ..................................................... 17

Register Mapping Tables................................................. 17

Electrical Specifications .................................................. 20

Absolute Maximum Ratings......................................... 21

Operating Temperature............................................... 21

DC Electrical Characteristics....................................... 22

AC Electrical Characteristics....................................... 29

Packaging Information..................................................... 37

Packaging Dimensions................................................ 37

Thermal Impedances................................................... 42

Capacitance on Crystal Pins ....................................... 42

Solder Reflow Peak Temperature............................... 42

Development Tool Selection ........................................... 43

Software ...................................................................... 43

Development Kits ........................................................ 43

Evaluation Tools.......................................................... 43

Device Programmers................................................... 44

Accessories (Emulation and Programming).................. 44

Third Party Tools......................................................... 44

Build a PSoC Emulator into Your Board...................... 44

Ordering Information........................................................ 45

Ordering Code Definitions............................................... 45

Document History Page................................................... 46

Sales, Solutions, and Legal Information........................ 47

Worldwide Sales and Design Support......................... 47

Products ...................................................................... 47

PSoC Solutions ........................................................... 47

Document Number: 38-12013 Rev. *M Page 2 of 47

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4. PSoC Functional Overview

DIGITAL SYSTEM

To Syste m Bus

D

i

g

i

t

a

l

C

l

o

c

k

s

F

r

o

m

C

o

r

e

Digital PSoC Block Array

To Analog

Syste m

8

Row Input

Configuration

Row Output

Configuration

88

8

Row 1

DBB 10 DBB11 DCB12 DCB 13

Row Input

Configuration

4

4

Row Output

Configuration

Row 0

DBB 00 DBB01 DCB02 DCB 03

4

4

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0 ]

Global Digital
Interconnect

Por t 4

Por t 3

Por t 2

Por t 1

Por t 0

Po r t 5

The PSoC family consists of many Programmable
System-on-Chip Controller devices. These devices are designed
to replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,

4.2 Digital System

The Digital System is composed of 8 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.

Figure 4-1. Digital System Block Diagram

as well as programmable interconnects. This architecture allows
the user to create customized peripheral configurations that
match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable I/O are included in a range of conve­nient pinouts and packages.

The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C29x66 family can have up to five I/O
ports that connect to the global digital and analog interconnects,
providing access to 8 digital blocks and 12 analog blocks.

4.1 PSoC Core

The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose I/O).

The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture micropro­cessor. The CPU uses an interrupt controller with 17 vectors, to
simplify programming of real time embedded events. Program
execution is timed and protected using the included Sleep and
Watch Dog Timers (WDT).

Memory encompasses 16K of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2K of EEPROM
emulated using the Flash. Program Flash utilizes four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.

The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to

2.5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.

PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external inter­facing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.

Digital peripheral configurations include those listed below.

■ PWMs (8 to 32 bit)

■ PWMs with Dead band (8 to 32 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity (up to 2)

■ SPI slave and master (up to 2)

2

■ I

C slave and multi-master (1 available as a System Resource)

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA (up to 2)

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Character-

istics” on page 5.

Document Number: 38-12013 Rev. *M Page 3 of 47

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4.3 Analog System

ACB00 ACB01

Bloc k Ar ra y

Array Input Configuration

ACI1[1:0] ACI2[1:0]

ACB02 ACB03

ASC12 ASD13

ASD22 ASC23ASD20

ACI0[1:0] ACI3[1:0]

P0[ 6 ]

P0[ 4 ]

P0[ 2 ]

P0[ 0 ]

P2[ 2 ]

P2[ 0 ]

P2[ 6 ]

P2[ 4 ]

RefIn

AGNDI n

P0[ 7 ]

P0[ 5 ]

P0[ 3 ]

P0[ 1 ]

P2[ 3 ]

P2[ 1 ]

Re fe r e nce

Ge ner ato rs

AGNDIn
Ref In
Bandgap

Ref Hi
Ref L o
AGND

ASD11

ASC21

ASC10

Interface to

Digital System

M8C Interface (Address Bus, Data Bus, Etc.)

Analog Re fe r ence

The Analog System is composed of 12 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are listed below.

■ Analog-to-digital converters (up to 4, with 6- to 14-bit resolution,

selectable as Incremental, Delta Sigma, and SAR)

■ Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch)

■ Amplifiers (up to 4, with selectable gain to 48x)

■ Instrumentation amplifiers (up to 2, with selectable gain to 93x)

■ Comparators (up to 4, with 16 selectable thresholds)

■ DACs (up to 4, with 6- to 9-bit resolution)

■ Multiplying DACs (up to 4, with 6- to 9-bit resolution)

■ High current output drivers (four with 30 mA drive as a Core

Resource)

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

■ Modulators

■ Correlators

■ Peak detectors

■ Many other topologies possible

Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.

Figure 4-2. Analog System Block Diagram

4.4 Additional System Resources

System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Statements
describing the merits of each system resource are below.

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.

■ Multiply accumulate (MAC) provides fast 8-bit multiplier with

32-bit accumulate, to assist in general math and digital filters.

■ The decimator provides a custom hardware filter for digital

signal processing applications including the creation of Delta
Sigma ADCs.

2

■ The I

C module provides 100 and 400 kHz communication over

two wires. Slave, master, and multi-master modes are all

Document Number: 38-12013 Rev. *M Page 4 of 47

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■ Low Voltage Detection (LVD) interrupts can signal the appli-

Notes

1. Limited analog functionality.

2. Two analog blocks and one CapSense.

cation of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3V reference provides an absolute reference for

the analog system, including ADCs and DACs.

■ An integrated switch mode pump (SMP) generates normal

operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.

4.5 PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources available
for specific PSoC device groups.The PSoC device covered by
this data sheet is highlighted below.

Table 4-1. PSoC Device Characteristics

PSoC Part

Number

CY8C29x66

CY8C27x43

CY8C24x94 49 1 4 48 2 2 6 1K 16K

CY8C24x23

CY8C24x23A

CY8C21x34

CY8C21x23

CY8C20x34

I/O

Digital

up to

64

up to

44

up to

24

up to

24

up to

28

16 1 4 8 0 2

up to

28

Rows

Digital

4 16 12 4 4 12 2K 32K

2 8 12 4 4 12

1 4 12 2 2 6

1412226

142802

0 0 28 0 0

Inputs

Digital

Blocks

Analog

Analog

Analog

Outputs

Columns

Blocks

Analog

[1]

4

[1]

4

[2]

3

SRAM

256

Bytes

256

Bytes

256

Bytes

512

Bytes

256

Bytes

512

Bytes

Size

Flash

16K

4K

4K

8K

4K

8K

5. Getting Started

The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.

For in depth information, along with detailed programming
details, see the PSoC Technical Reference Manual for
CY8C29x66 PSoC devices.

For up to date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.

5.1 Application Notes

Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:

www.cypress.com/psoc. Select Application Notes under the

Documentation tab.

Size

5.2 Development Kits

PSoC Development Kits are available online from Cypress at

www.cypress.com/shop and through a growing number of

regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.

5.3 Training

Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.

5.4 CYPros Consultants

Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.

Document Number: 38-12013 Rev. *M Page 5 of 47

5.5 Solutions Library

Visit our growing library of solution focused designs at

www.cypress.com/solutions. Here you can find various

application designs that include firmware and hardware design
files that enable you to complete your designs quickly.

5.6 Technical Support

For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.

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6. Development Tools

PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.

This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built in support for third party
assemblers and C compilers.

PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.

6.1 PSoC Designer Software Subsystems

6.1.1 System-Level View

A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication
interfaces. You define when and how an output device changes
state based upon any or all other system devices. Based upon
the design, PSoC Designer automatically selects one or more
PSoC Programmable System-on-Chip Controllers that match
your system requirements.

PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.

6.1.2 Chip-Level View

The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.

The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.

6.1.3 Hybrid Designs

You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.

6.1.4 Code Generation Tools

PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.

Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.

C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.

The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.

6.1.5 Debugger

The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.

6.1.6 Online Help System

The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.

6.2 In-Circuit Emulator

A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.

The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.

Document Number: 38-12013 Rev. *M Page 6 of 47

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7. Designing with PSoC Designer

The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user selectable functions.

The PSoC development process can be summarized in the
following four steps:

1. Select Components

2. Configure Components

3. Organize and Connect

4. Generate, Verify, and Debug

7.1 Select Components

Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces

2

(I

C-bus, for example), and the logic to control how they interact

with one another (called valuators).

In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and programmable
system-on-chip varieties.

7.2 Configure Components

Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.

Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in the PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.

7.3 Organize and Connect

You can build signal chains at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.

In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.

In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.

7.4 Generate, Verify, and Debug

When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.

Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.

A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.

The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you define complex breakpoint events that
include monitoring address and data bus values, memory
locations and external signals.

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8. Document Conventions

8.1 Acronyms Used

This table lists the acronyms used in this data sheet.

Table 8-1. Acronyms

Acronym Description

AC alternating current

ADC analog-to-digital converter

API application programming interface

CPU central processing unit

CT continuous time

DAC digital-to-analog converter

DC direct current

EEPROM electrically erasable programmable read-only

FSR full scale range

GPIO general purpose I/O

ICE in-circuit emulator

IDE integrated development environment

I/O input/output

ISSP in-system serial programming

IPOR imprecise power on reset

LSb least-significant bit

LVD low voltage detect

MSb most-significant bit

PC program counter

PGA programmable gain amplifier

POR power on reset

PPOR precision power on reset

®

PSoC

PWM pulse width modulator

ROM read only memory

SC switched capacitor

SMP switch mode pump

SRAM static random access memory

memory

Programmable System-on-Chip™

8.2 Units of Measure

A units of measure table is located in the section

Electrical Specifications on page 20. Table 12-1 on page 20 lists

all the abbreviations used to measure the PSoC devices.

8.3 Numeric Naming

Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.

Document Number: 38-12013 Rev. *M Page 8 of 47

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9. Pinouts

A, I, P0[7 ]
A, IO, P0[5 ]
A, IO, P0[3 ]

A, I, P0[1 ]

P2[ 7]
P2[ 5]

A, I, P2[3 ]

A, I, P2[1 ]

SMP

I2 C SCL , P1[7 ]

I2 C SDA, P1 [5 ]

P1[ 3]

I2 C SCL , XTALi n , P1 [1 ]

Vss

Vdd
P0[6 ], A, I
P0[4 ], A, IO
P0[2 ], A, IO
P0[0 ], A, I
P2[6], Ex ter n a l VREF
P2[4], Ex ter n a l AGND
P2[2 ], A, I
P2[0 ], A, I
XRES
P1 [6]
P1[4], EXT CL K
P1 [2]
P1[0 ], XTALou t, I2 C SDA

PDIP

SSOP

SOIC

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

The CY8C29x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, SMP, and XRES are not capable of Digital I/O.

9.1 28-Pin Part Pinout

Table 9-1. 28-Pin Part Pinout (PDIP, SSOP, SOIC)

Pin

No.

1 I/O I P0[7] Analog column mux input.
2 I/O I/O P0[5] Analog column mux input and column output.
3 I/O I/O P0[3] Analog column mux input and column output.
4 I/O I P0[1] Analog column mux input.
5 I/O P2[7]
6 I/O P2[5]
7 I/O I P2[3] Direct switched capacitor block input.
8 I/O I P2[1] Direct switched capacitor block input.
9 Power SMP Switch Mode Pump (SMP) connection to

10 I/O P1[7] I2C Serial Clock (SCL).
11 I/O P1[5] I2C Serial Data (SDA).
12 I/O P1[3]
13 I/O P1[1] Crystal (XTALin), I2C Serial Clock (SCL),

14 Power Vss Ground connection.
15 I/O P1[0] Crystal (XTALout), I2C Serial Data (SDA),

16 I/O P1[2]
17 I/O P1[4] Optional External Clock Input (EXTCLK).
18 I/O P1[6]
19 Input XRES Active high external reset with internal pull

20 I/O I P2[0] Direct switched capacitor block input.
21 I/O I P2[2] Direct switched capacitor block input.
22 I/O P2[4] External Analog Ground (AGND).
23 I/O P2[6] External Voltage Reference (VREF).
24 I/O I P0[0] Analog column mux input.
25 I/O I/O P0[2] Analog column mux input and column output.
26 I/O I/O P0[4] Analog column mux input and column output.
27 I/O I P0[6] Analog column mux input.
28 Power Vdd Supply voltage.

LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.

Typ e

Digital Analog

Pin

Name

external components required.

ISSP-SCLK*.

ISSP-SDATA*.

down.

Description

Figure 9-1. CY8C29466 28-Pin PSoC Device

Document Number: 38-12013 Rev. *M Page 9 of 47

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CY8C29666, CY8C29866

9.2 44-Pin Part Pinout

TQFP

P3[1]

P2[7]

P2[5] P2[4], External AGND
A, I, P2[3] P2[2], A, I
A, I, P2[1] P2[0], A, I

P4[7]

P4[6]

P4[5]

P4[4]

P4[3]

P4[2]

P4[1]

P4[0]

SMP X RE S

P3[7]

P3[6]
P3[5] P3[4]
P3[3] P3[2]

I2C SCL, P1[7]

P0[1], A, I

I2C SDA, P1[5]

P0[3], A, IO

P1[3]

P0[5], A, IO

I2C SCL, XTALin, P1[1]

P0[7], A, I

Vss

Vdd

I2C SDA, XTALout, P1[0]

P0[6], A, I

P1[2]

P0[4], A, IO

EXTCLK, P1[4]

P0[2], A, IO

P1[6]

P0[0], A, I

P3[0]

P2[6], External VREF

33
32
31
30
29
28
27
26

25
24
23

1
2
3
4
5
6
7
8
9

10

11

4443424140393837363534

13

14

15

16

17

18

192021

22

12

Table 9-2. 44-Pin Part Pinout (TQFP)

Pin
No.

1 I/O P2[5]
2 I/O I P2[3] Direct switched capacitor block input.
3 I/O I P2[1] Direct switched capacitor block input.
4 I/O P4[7]
5 I/O P4[5]
6 I/O P4[3]
7 I/O P4[1]
8 Power SMP Switch Mode Pump (SMP) connection to

9 I/O P3[7]
10 I/O P3[5]
11 I/O P3[3]
12 I/O P3[1]
13 I/O P1[7] I2C Serial Clock (SCL).
14 I/O P1[5] I2C Serial Data (SDA).
15 I/O P1[3]
16 I/O P1[1] Crystal (XTALin), I2C Serial Clock (SCL),

17 Power Vss Ground connection.
18 I/O P1[0] Crystal (XTALout), I2C Serial Data (SDA),

19 I/O P1[2]
20 I/O P1[4] Optional External Clock Input (EXTCLK).
21 I/O P1[6]
22 I/O P3[0]
23 I/O P3[2]
24 I/O P3[4]
25 I/O P3[6]
26 Input XRES Active high external reset with internal pull

27 I/O P4[0]
28 I/O P4[2]
29 I/O P4[4]
30 I/O P4[6]
31 I/O I P2[0] Direct switched capacitor block input.
32 I/O I P2[2] Direct switched capacitor block input.
33 I/O P2[4] External Analog Ground (AGND).
34 I/O P2[6] External Voltage Reference (VREF).
35 I/O I P0[0] Analog column mux input.
36 I/O I/O P0[2] Analog column mux input and column output.
37 I/O I/O P0[4] Analog column mux input and column output.
38 I/O I P0[6] Analog column mux input.
39 Power Vdd Supply voltage.
40 I/O I P0[7] Analog column mux input.
41 I/O I/O P0[5] Analog column mux input and column output.
42 I/O I/O P0[3] Analog column mux input and column output.
43 I/O I P0[1] Analog column mux input.
44 I/O P2[7]

LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-ChipTechnical Reference Manual for details.

Typ e

Digital Analog

Pin

Name

external components required.

ISSP-SCLK*.

ISSP-SDATA*.

down.

Description

Figure 9-2. CY8C29566 44-Pin PSoC Device

Document Number: 38-12013 Rev. *M Page 10 of 47

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CY8C29666, CY8C29866

9.3 48-Pin Part Pinouts

SSOP

A, I, P0[7]

Vdd

A, IO, P0[5]

P0[6], A, I

A, IO, P0[3]

P0[2], A, IO

A, I, P0[1]

P0[4], A, IO

P2[7]

P0[0], A, I

P2[5]

P2[6], External VREF

A, I, P2[3]

P2[4], External AGND

A, I, P2[1]

P2[2], A, I

P4[7]

P2[0], A, I

P4[5]

P4[6]

P4[3]

P4[4]

P4[1]

P4[2]

SMP

P4[0]

P3[7]

XRES

P3[5]

P3[6]

P3[3]

P3[4]

P3[1]

P3[2]

P5[3]

P3[0]

P5[1]

P5[2]

I2C SCL, P1[7]

P5[0]

I2C SDA, P1[5]

P1[6]

P1[3]

P1[4], EXT CLK

I2C SCL, XTALin, P1[1] P1[2]

Vss P1[0], XTALout, I2C SDA

1
2

3
4

5

6
7

8

9
10
11
12
13

14

15

16
17
18
19
20

21

22
23

24

48
47
46
45

43

44

42

40

41

39
38
37
36
35

33

34

32
31
30

29
28
27
26
25

Table 9-3. 48-Pin Part Pinout (SSOP)

Pin
No.

1 I/O I P0[7] Analog column mux input.
2 I/O I/O P0[5] Analog column mux input and column output.
3 I/O I/O P0[3] Analog column mux input and column output.
4 I/O I P0[1] Analog column mux input.
5 I/O P2[7]
6 I/O P2[5]
7 I/O I P2[3] Direct switched capacitor block input.
8 I/O I P2[1] Direct switched capacitor block input.
9 I/O P4[7]
10 I/O P4[5]
11 I/O P4[3]
12 I/O P4[1]
13 Power SMP Switch Mode Pump (SMP) connection to

14 I/O P3[7]
15 I/O P3[5]
16 I/O P3[3]
17 I/O P3[1]
18 I/O P5[3]
19 I/O P5[1]
20 I/O P1[7] I2C Serial Clock (SCL).
21 I/O P1[5] I2C Serial Data (SDA).
22 I/O P1[3]
23 I/O P1[1] Crystal (XTALin), I2C Serial Clock (SCL),

24 Power Vss Ground connection.
25 I/O P1[0] Crystal (XTALout), I2C Serial Data (SDA),

26 I/O P1[2]
27 I/O P1[4] Optional External Clock Input (EXTCLK).
28 I/O P1[6]
29 I/O P5[0]
30 I/O P5[2]
31 I/O P3[0]
32 I/O P3[2]
33 I/O P3[4]
34 I/O P3[6]
35 Input XRES Active high external reset with internal pull

36 I/O P4[0]
37 I/O P4[2]
38 I/O P4[4]
39 I/O P4[6]
40 I/O I P2[0] Direct switched capacitor block input.
41 I/O I P2[2] Direct switched capacitor block input.
42 I/O P2[4] External Analog Ground (AGND).
43 I/O P2[6] External Voltage Reference (VREF).
44 I/O I P0[0] Analog column mux input.
45 I/O I/O P0[2] Analog column mux input and column output.
46 I/O I/O P0[4] Analog column mux input and column output.
47 I/O I P0[6] Analog column mux input.
48 Power Vdd Supply voltage.

LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.

Document Number: 38-12013 Rev. *M Page 11 of 47

Typ e

Digital Analog

Pin

Name

external components required.

ISSP-SCLK*.

ISSP-SDATA*.

down.

Description

Figure 9-3. CY8C29666 48-Pin PSoC Device

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CY8C29466, CY8C29566
CY8C29666, CY8C29866

QFN

(Top View)

P2[5]

P2[7]

P0 [1 ], A , I

P0 [3 ], A , IO

P0 [5 ], A , IO

P0 [7 ], A , I

Vdd

P0 [6 ], A , I

P0 [4 ], A , IO

P0 [2 ], A , IO

P0 [0 ], A , I

P2 [6 ], E xtern a l V REF

10
11

12

A, I, P2[3]
A, I, P2[1]

P4[7]
P4[5]
P4[3]
P4[1]

SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]

35
34
33
32
31
30
29
28
27
26
25

36

4847464544

43424140393837

P2[2], A, I

P2[0], A, I
P4[6]
P4[4]

P4[2]
P4[0]
XRES

P3[6]
P3[4]

P3[2]
P3[0]

P2[4], External AGND

1
2

3
4
5
6

7
8
9

1314151617181920212223

24

P5[1]

I2C SCL, P1[7 ]

I2C SDA, P1[5]

P1[3]

I2C SCL, XTALi n, P1 [1 ]

Vss

I2C SDA , XTA Lo u t, P 1[0]

P1[2]

EXTCLK, P1[4]

P1[6]

P5[0]

P5[2]

Table 9-4. 48-Pin Part Pinout (QFN)**

Pin
No.

1 I/O I P2[3] Direct switched capacitor block input.

2 I/O I P2[1] Direct switched capacitor block input.

3 I/O P4[7]

4 I/O P4[5]

5 I/O P4[3]

6 I/O P4[1]

7 Power SMP Switch Mode Pump (SMP) connection to

8 I/O P3[7]

9 I/O P3[5]

10 I/O P3[3]

11 I/O P3[1]

12 I/O P5[3]

13 I/O P5[1]

14 I/O P1[7] I2C Serial Clock (SCL).

15 I/O P1[5] I2C Serial Data (SDA).

16 I/O P1[3]

17 I/O P1[1] Crystal (XTALin), I2C Serial Clock (SCL),

18 Power Vss Ground connection.

19 I/O P1[0] Crystal (XTALout), I2C Serial Data (SDA),

20 I/O P1[2]

21 I/O P1[4] Optional External Clock Input (EXTCLK).

22 I/O P1[6]

23 I/O P5[0]

24 I/O P5[2]

25 I/O P3[0]

26 I/O P3[2]

27 I/O P3[4]

28 I/O P3[6]

29 Input XRES Active high external reset with internal pull

30 I/O P4[0]

31 I/O P4[2]

32 I/O P4[4]

33 I/O P4[6]

34 I/O I P2[0] Direct switched capacitor block input.

35 I/O I P2[2] Direct switched capacitor block input.

36 I/O P2[4] External Analog Ground (AGND).

37 I/O P2[6] External Voltage Reference (VREF).

38 I/O I P0[0] Analog column mux input.

39 I/O I/O P0[2] Analog column mux input and column output.

40 I/O I/O P0[4] Analog column mux input and column output.

41 I/O I P0[6] Analog column mux input.

42 Power Vdd Supply voltage.

43 I/O I P0[7] Analog column mux input.

44 I/O I/O P0[5] Analog column mux input and column output.

45 I/O I/O P0[3] Analog column mux input and column output.

46 I/O I P0[1] Analog column mux input.

47 I/O P2[7]

48 I/O P2[5]

LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
** The QFN package has a center pad that must be connected to ground (Vss).

Typ e

Digital Analog

Pin

Name

external components required.

ISSP-SCLK*.

ISSP-SDATA*.

down.

Description

Figure 9-4. CY8C29666 48-Pin PSoC Device

Document Number: 38-12013 Rev. *M Page 12 of 47

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9.4 100-Pin Part Pinout

Table 9-5. 100-Pin Part Pinout (TQFP)

Pin
No.

1 NC No connection. 51 NC No connection.
2 NC No connection. 52 I/O P5[0]
3 I/O I P0[1] Analog column mux input. 53 I/O P5[2]
4 I/O P2[7] 54 I/O P5[4]
5 I/O P2[5] 55 I/O P5[6]
6 I/O I P2[3] Direct switched capacitor block input. 56 I/O P3[0]
7 I/O I P2[1] Direct switched capacitor block input. 57 I/O P3[2]
8 I/O P4[7] 58 I/O P3[4]
9 I/O P4[5] 59 I/O P3[6]
10 I/O P4[3] 60 NC No connection.
11 I/O P4[1] 61 NC No connection.
12 NC No connection. 62 Input XRES Active high external reset with internal pull

13 NC No connection. 63 I/O P4[0]
14 Power SMP Switch Mode Pump (SMP) connection to

15 Power Vss Ground connection. 65 Power Vss Ground connection.
16 I/O P3[7] 66 I/O P4[4]
17 I/O P3[5] 67 I/O P4[6]
18 I/O P3[3] 68 I/O I P2[0] Direct switched capacitor block input.
19 I/O P3[1] 69 I/O I P2[2] Direct switched capacitor block input.
20 I/O P5[7] 70 I/O P2[4] External Analog Ground (AGND).
21 I/O P5[5] 71 NC No connection.
22 I/O P5[3] 72 I/O P2[6] External Voltage Reference (VREF).
23 I/O P5[1] 73 NC No connection.
24 I/O P1[7] I2C Serial Clock (SCL). 74 I/O I P0[0] Analog column mux input.
25 NC No connection. 75 NC No connection.
26 NC No connection. 76 NC No connection.
27 NC No connection. 77 I/O I/O P0[2] Analog column mux input and column output.
28 I/O P1[5] I2C Serial Data (SDA). 78 NC No connection.
29 I/O P1[3] 79 I/O I/O P0[4] Analog column mux input and column output.
30 I/O P1[1] Crystal (XTALin), I2C Serial Clock (SCL),

31 NC No connection. 81 I/O I P0[6] Analog column mux input.
32 Power Vdd Supply voltage. 82 Power Vdd Supply voltage.
33 NC No connection. 83 Power Vdd Supply voltage.
34 Power Vss Ground connection. 84 Power Vss Ground connection.
35 NC No connection. 85 Power Vss Ground connection.
36 I/O P7[7] 86 I/O P6[0]
37 I/O P7[6] 87 I/O P6[1]
38 I/O P7[5] 88 I/O P6[2]
39 I/O P7[4] 89 I/O P6[3]
40 I/O P7[3] 90 I/O P6[4]
41 I/O P7[2] 91 I/O P6[5]
42 I/O P7[1] 92 I/O P6[6]
43 I/O P7[0] 93 I/O P6[7]
44 I/O P1[0] Crystal (XTALout), I2C Serial Data (SDA),

45 I/O P1[2] 95 I/O I P0[7] Analog column mux input.
46 I/O P1[4] Optional External Clock Input (EXTCLK). 96 NC No connection.
47 I/O P1[6] 97 I/O I/O P0[5] Analog column mux input and column output.
48 NC No connection. 98 NC No connection.
49 NC No connection. 99 I/O I/O P0[3] Analog column mux input and column output.
50 NC No connection. 100 NC No connection.

LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.

Typ e

Digital Analog Digital Analog

Name Description

external components required.

ISSP-SCLK*.

ISSP-SDATA*.

Pin
No.

64 I/O P4[2]

80 NC No connection.

94 NC No connection.

Typ e

Name Description

down.

Document Number: 38-12013 Rev. *M Page 13 of 47

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Figure 9-5. CY8C29866 100-Pin PSoC Device

TQF P

NC
NC

A, I, P0[1]

P2[7]
P2[5]

A, I, P2[3]

A, I, P2[1]

P4[7]
P4[5]
P4[3]

P4[1]

NC
NC

SMP

Vss
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]

I2C SCL, P1[7]

NC

NC

Vss

P7[3]

EXTCLK, P1[4]

NC

I2C SDA, P1[5]

P1[3]

XTALin, I2C SCL, P1[1]

NC

Vdd

NC

NC

P7[7]

P7[6]

P7[5]

P7[4]

P7[2]

P7[1]

P7[0]

XTALout, I2C SDA, P1[0]

P1[2]

P1[6]

NCNCNC

NC
P0[0], A, I
NC
P2[6], External VREF
NC

P2[4], External AGND
P2[2], A, I

P2[0], A, I
P4[6]
P4[4]
Vss
P4[2]

P4[0]
XRES
NC

NC
P3[6]
P3[4]
P3[2]
P3[0]
P5[6]

P5[4]
P5[2]

P5[0]
NC

NC

P0[3], A, IONCP0[5], A, IONCP0[7], A, INCP6[7]

P6[6]

P6[5]

P6[4]

P6[3]

P6[2]

P6[1]

P6[0]

Vss

Vss

Vdd

Vdd

P0[6], A, INCP0[4], A, IONCP0[2], A, IO

NC

75
74

73
72
71

70
69
68

67
66
65
64
63
62
61
60
59
58
57
56
55

54
53
52
51

100

9998979695949392919089888786858483828180797877

76

10
11
12
13
14
15
16
17
18

19
20

21
22
23
24
25

1
2
3
4
5
6
7
8
9

26272829303132333435363738394041424344454647485049

Document Number: 38-12013 Rev. *M Page 14 of 47

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9.5 100-Pin Part Pinout (On-Chip Debug)

The 100-pin TQFP part is for the CY8C29000 On-Chip Debug (OCD) PSoC device.

Note OCD parts are only used for in-circuit debugging. OCD parts are NOT available for production

Table 9-6. 100-Pin OCD Part Pinout (TQFP)

Pin
No.

1 NC No internal connection. 51 NC No internal connection.
2 NC No internal connection. 52 I/O P5[0]
3 I/O I P0[1] Analog column mux input. 53 I/O P5[2]
4 I/O P2[7] 54 I/O P5[4]
5 I/O P2[5] 55 I/O P5[6]
6 I/O I P2[3] Direct switched capacitor block input. 56 I/O P3[0]
7 I/O I P2[1] Direct switched capacitor block input. 57 I/O P3[2]
8 I/O P4[7] 58 I/O P3[4]
9 I/O P4[5] 59 I/O P3[6]
10 I/O P4[3] 60 HCLK OCD high speed clock output
11 I/O P4[1] 61 CCLK OCD CPU clock output
12 OCDE OCD even data I/O 62 Input XRES Active high pin reset with internal pull down.
13 OCDO OCD odd data output 63 I/O P4[0]
14 Power SMP Switch Mode Pump (SMP) connection to

15 Power Vss Ground connection. 65 Power Vss Ground connection.
16 I/O P3[7] 66 I/O P4[4]
17 I/O P3[5] 67 I/O P4[6]
18 I/O P3[3] 68 I/O I P2[0] Direct switched capacitor block input.
19 I/O P3[1] 69 I/O I P2[2] Direct switched capacitor block input.
20 I/O P5[7] 70 I/O P2[4] External Analog Ground (AGND) input.
21 I/O P5[5] 71 NC No internal connection.
22 I/O P5[3] 72 I/O P2[6] External Voltage Reference (VREF) input.
23 I/O P5[1] 73 NC No internal connection.
24 I/O P1[7] I2C Serial Clock (SCL) 74 I/O I P0[0] Analog column mux input.
25 NC No internal connection. 75 NC No internal connection.
26 NC No internal connection. 76 NC No internal connection.
27 NC No internal connection. 77 I/O I/O P0[2] Analog column mux input and column output.
28 I/O P1[5] I2C Serial Data (SDA). 78 NC No internal connection.
29 I/O P1[3] I

30 I/O P1[1]* Crystal (XTALin), I2C Serial Clock (SCL), TC

31 NC No internal connection. 81 I/O I P0[6] Analog column mux input.
32 Power Vdd Supply voltage. 82 Power Vdd Supply voltage.
33 NC No internal connection. 83 Power Vdd Supply voltage.
34 Power Vss Ground connection. 84 Power Vss Ground connection.
35 NC No internal connection. 85 Power Vss Ground connection.
36 I/O P7[7] 86 I/O P6[0]
37 I/O P7[6] 87 I/O P6[1]
38 I/O P7[5] 88 I/O P6[2]
39 I/O P7[4] 89 I/O P6[3]
40 I/O P7[3] 90 I/O P6[4]
41 I/O P7[2] 91 I/O P6[5]
42 I/O P7[1] 92 I/O P6[6]
43 I/O P7[0] 93 I/O P6[7]
44 I/O P1[0]* Crystal (XTALout), I2C Serial Data (SDA), TC

45 I/O P1[2] V
46 I/O P1[4] Optional External Clock Input (EXTCLK) 96 NC No internal connection.
47 I/O P1[6] 97 I/O I/O P0[5] Analog column mux input and column output.
48 NC No internal connection. 98 NC No internal connection.
49 NC No internal connection. 99 I/O I/O P0[3] Analog column mux input and column output.
50 NC No internal connection. 100 NC No internal connection.

LEGEND A = Analog, I = Input, O = Output, NC = No Connection, TC/TM: Test.

Name Description

Digital

Analog

required external components.

79 I/O I/O P0[4] Analog column mux input and column output,

FMTEST

SCLK.

SDATA

FMTEST

* ISSP pin which is not HiZ at POR.

Pin
No.

Digital

64 I/O P4[2]

80 NC No internal connection.

94 NC No internal connection.

95 I/O I P0[7] Analog column mux input.

Name Description

Analog

V

.

REF

Document Number: 38-12013 Rev. *M Page 15 of 47

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