Cypress Semiconductor CY8C29466, CY8C29566, CY8C29666, CY8C29866 User manual

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PSoC® Programmable System-on-Chip™

1. Features

DIGITAL SYSTEM

SRAM

256 Bytes

Interrupt

Controller

Sleep and Watchdog

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

Global Digital Interconnect

Global Analog Interconnect

PSoC

CORE

CPU Core (M 8C)

SROM Fla sh 16K

Digital

Block Array

Multiply Acc um .

Switch

Mo de

Pump

Internal Vol ta ge

Ref.

Digital

Clocks

POR and LVD

System Resets

Decimator

SYSTEM RESOURCES

ANALOG SYSTEM

Ana l o g

Ref.

An al og

Inp ut

Mu xin g

I C

Por t 4 Por t 3 Po rt 2 Por t 1 Por t 0

Analog Dr ive r s

System Bus

An alo g

Block Ar ray

Por t 5

2. Logic Block Diagram

■ Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 24 MHz ❐ Two 8x8 Multiply, 32-Bit Accumulate

❐ Low Power at High Speed ❐ 3.0V to 5.25V Operating Voltage ❐ Operating Voltages Down to 1.0V Using On-Chip Switch

Mode Pump (SMP)

❐ Industrial Temperature Range: -40°C to +85°C

■ Advanced Peripherals (PSoC ❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:

• Up to 14-Bit ADCs

• Up to 9-Bit DACs

• Programmable Gain Amplifiers

• Programmable Filters and Comparators

❐ 16 Digital PSoC Blocks Provide:

• 8- to 32-Bit Timers, Counters, and PWMs

• CRC and PRS Modules

• Up to 4 Full-Duplex UARTs

• Multiple SPI™ Masters or Slaves

• Connectable to all GPIO Pins

❐ Complex Peripherals by Combining Blocks

■ Precision, Programmable Clocking ❐ Internal ±2.5% 24/48 MHz Oscillator

❐ 24/48 MHz with Optional 32.768 kHz Crystal ❐ Optional External Oscillator, up to 24 MHz ❐ Internal Oscillator for Watchdog and Sleep

■ Flexible On-Chip Memory ❐ 32K Bytes Flash Program Storage 50,000 Erase/Write Cy-

cles

❐ 2K Bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash

■ Programmable Pin Configurations ❐ 25 mA Sink, 10 mA Source on all GPIO ❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive

Modes on all GPIO

❐ 8 standard analog inputs on GPIO, plus 4 additional analog

inputs with restricted routing

❐ Four 40 mA Analog Outputs on GPIO ❐ Configurable Interrupt on all GPIO

Blocks)

■ Additional System Resources

❐ I

C Slave, Master, and Multi-Master to

400 kHz

❐ Watchdog and Sleep Timers ❐ User-Configurable Low Voltage Detection ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Reference

■ Complete Development Tools ❐ Free Development Software

(PSoC Designer™)

❐ Full-Featured, In-Circuit Emulator and

Programmer

❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128K Bytes Trace Memory ❐ Complex Events ❐ C Compilers, Assembler, and Linker

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-12013 Rev. *M Revised January 11, 2010

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3. Contents

Features............................................................................... 1

Logic Block Diagram.......................................................... 1

Contents .............................................................................. 2

PSoC Functional Overview................................................ 3

PSoC Core .................................................................... 3

Digital System ............................................................... 3

Analog System .............................................................. 4

Additional System Resources ....................................... 4

PSoC Device Characteristics ........................................ 5

Getting Started.................................................................... 5

Application Notes .......................................................... 5

Development Kits .......................................................... 5

Training ......................................................................... 5

CYPros Consultants ...................................................... 5

Solutions Library............................................................ 5

Technical Support ......................................................... 5

Development Tools ............................................................ 6

PSoC Designer Software Subsystems.......................... 6

In-Circuit Emulator......................................................... 6

Designing with PSoC Designer ......................................... 7

Select Components ....................................................... 7

Configure Components ................................................. 7

Organize and Connect .................................................. 7

Generate, Verify, and Debug......................................... 7

Document Conventions ..................................................... 8

Acronyms Used ............................................................. 8

Units of Measure ........................................................... 8

Numeric Naming............................................................ 8

Pinouts ................................................................................ 9

28-Pin Part Pinout ......................................................... 9

44-Pin Part Pinout ....................................................... 10

48-Pin Part Pinout ....................................................... 11

100-Pin Part Pinout ......................................................13

100-Pin Part Pinout (On-Chip Debug)......................... 15

Abbreviations Used ..................................................... 17

Electrical Specifications .................................................. 20

Absolute Maximum Ratings......................................... 21

Operating Temperature............................................... 21

DC Electrical Characteristics....................................... 22

AC Electrical Characteristics....................................... 29

Packaging Information..................................................... 37

Packaging Dimensions................................................ 37

Thermal Impedances................................................... 42

Capacitance on Crystal Pins ....................................... 42

Solder Reflow Peak Temperature............................... 42

Development Tool Selection ........................................... 43

Software ...................................................................... 43

Development Kits ........................................................ 43

Evaluation Tools.......................................................... 43

Device Programmers................................................... 44

Accessories (Emulation and Programming).................. 44

Third Party Tools......................................................... 44

Build a PSoC Emulator into Your Board...................... 44

Ordering Information........................................................ 45

Ordering Code Definitions............................................... 45

Document History Page................................................... 46

Sales, Solutions, and Legal Information........................ 47

Worldwide Sales and Design Support......................... 47

Products ...................................................................... 47

PSoC Solutions ........................................................... 47

Document Number: 38-12013 Rev. *M Page 2 of 47

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4. PSoC Functional Overview

DIGITAL SYSTEM

To Syste m Bus

Digital PSoC Block Array

To Analog

Syste m

Row Input

Configuration

Row Output

Configuration

Row 1

DBB 10 DBB11 DCB12 DCB 13

Row Input

Configuration

Row Output

Configuration

Row 0

DBB 00 DBB01 DCB02 DCB 03

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0 ]

Global Digital Interconnect

Por t 4

Por t 3

Por t 2

Por t 1

Por t 0

Po r t 5

The PSoC family consists of many Programmable System-on-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic,

4.2 Digital System

The Digital System is composed of 8 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references.

Figure 4-1. Digital System Block Diagram

as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages.

The PSoC architecture, as illustrated on the left, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C29x66 family can have up to five I/O ports that connect to the global digital and analog interconnects, providing access to 8 digital blocks and 12 analog blocks.

4.1 PSoC Core

The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose I/O).

The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 17 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT).

Memory encompasses 16K of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2K of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection.

The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to

2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device.

PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.

Digital peripheral configurations include those listed below.

■ PWMs (8 to 32 bit)

■ PWMs with Dead band (8 to 32 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity (up to 2)

■ SPI slave and master (up to 2)

■ I

C slave and multi-master (1 available as a System Resource)

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA (up to 2)

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled “PSoC Device Character-

istics” on page 5.

Document Number: 38-12013 Rev. *M Page 3 of 47

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4.3 Analog System

ACB00 ACB01

Bloc k Ar ra y

Array Input Configuration

ACI1[1:0] ACI2[1:0]

ACB02 ACB03

ASC12 ASD13

ASD22 ASC23ASD20

ACI0[1:0] ACI3[1:0]

P0[ 6 ]

P0[ 4 ]

P0[ 2 ]

P0[ 0 ]

P2[ 2 ]

P2[ 0 ]

P2[ 6 ]

P2[ 4 ]

RefIn

AGNDI n

P0[ 7 ]

P0[ 5 ]

P0[ 3 ]

P0[ 1 ]

P2[ 3 ]

P2[ 1 ]

Re fe r e nce

Ge ner ato rs

AGNDIn Ref In Bandgap

Ref Hi Ref L o AGND

ASD11

ASC21

ASC10

Interface to

Digital System

M8C Interface (Address Bus, Data Bus, Etc.)

Analog Re fe r ence

The Analog System is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are listed below.

■ Analog-to-digital converters (up to 4, with 6- to 14-bit resolution,

selectable as Incremental, Delta Sigma, and SAR)

■ Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch)

■ Amplifiers (up to 4, with selectable gain to 48x)

■ Instrumentation amplifiers (up to 2, with selectable gain to 93x)

■ Comparators (up to 4, with 16 selectable thresholds)

■ DACs (up to 4, with 6- to 9-bit resolution)

■ Multiplying DACs (up to 4, with 6- to 9-bit resolution)

■ High current output drivers (four with 30 mA drive as a Core

Resource)

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

■ Modulators

■ Correlators

■ Peak detectors

■ Many other topologies possible

Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below.

Figure 4-2. Analog System Block Diagram

4.4 Additional System Resources

System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Statements describing the merits of each system resource are below.

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers.

■ Multiply accumulate (MAC) provides fast 8-bit multiplier with

32-bit accumulate, to assist in general math and digital filters.

■ The decimator provides a custom hardware filter for digital

signal processing applications including the creation of Delta Sigma ADCs.

■ The I

C module provides 100 and 400 kHz communication over

two wires. Slave, master, and multi-master modes are all

Document Number: 38-12013 Rev. *M Page 4 of 47

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■ Low Voltage Detection (LVD) interrupts can signal the appli-

Notes

1. Limited analog functionality.

2. Two analog blocks and one CapSense.

cation of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3V reference provides an absolute reference for

the analog system, including ADCs and DACs.

■ An integrated switch mode pump (SMP) generates normal

operating voltages from a single 1.2V battery cell, providing a low cost boost converter.

4.5 PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups.The PSoC device covered by this data sheet is highlighted below.

Table 4-1. PSoC Device Characteristics

PSoC Part

Number

CY8C29x66

CY8C27x43

CY8C24x94 49 1 4 48 2 2 6 1K 16K

CY8C24x23

CY8C24x23A

CY8C21x34

CY8C21x23

CY8C20x34

I/O

Digital

up to

16 1 4 8 0 2

up to

Rows

Digital

4 16 12 4 4 12 2K 32K

2 8 12 4 4 12

1 4 12 2 2 6

1412226

142802

0 0 28 0 0

Inputs

Digital

Blocks

Analog

Outputs

Columns

Blocks

Analog

[1]

[2]

SRAM

256

Bytes

256

Bytes

256

Bytes

512

Bytes

256

Bytes

512

Bytes

Size

Flash

16K

5. Getting Started

The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications.

For in depth information, along with detailed programming details, see the PSoC Technical Reference Manual for CY8C29x66 PSoC devices.

For up to date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at www.cypress.com/psoc.

5.1 Application Notes

Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here:

www.cypress.com/psoc. Select Application Notes under the

Documentation tab.

Size

5.2 Development Kits

PSoC Development Kits are available online from Cypress at

www.cypress.com/shop and through a growing number of

regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark.

5.3 Training

Free PSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs.

5.4 CYPros Consultants

Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros.

Document Number: 38-12013 Rev. *M Page 5 of 47

5.5 Solutions Library

Visit our growing library of solution focused designs at

www.cypress.com/solutions. Here you can find various

application designs that include firmware and hardware design files that enable you to complete your designs quickly.

5.6 Technical Support

For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736.

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6. Development Tools

PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista.

This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built in support for third party assemblers and C compilers.

PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family.

6.1 PSoC Designer Software Subsystems

6.1.1 System-Level View

A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC Programmable System-on-Chip Controllers that match your system requirements.

PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device.

6.1.2 Chip-Level View

The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.4. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application.

The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.

6.1.3 Hybrid Designs

You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools.

6.1.4 Code Generation Tools

PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours.

Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing.

C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices.

The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

6.1.5 Debugger

The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.

6.1.6 Online Help System

The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.

6.2 In-Circuit Emulator

A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices.

The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.

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7. Designing with PSoC Designer

The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user selectable functions.

The PSoC development process can be summarized in the following four steps:

1. Select Components

2. Configure Components

3. Organize and Connect

4. Generate, Verify, and Debug

7.1 Select Components

Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called “drivers” and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces

C-bus, for example), and the logic to control how they interact

with one another (called valuators).

In the chip-level view, the components are called “user modules”. User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and programmable system-on-chip varieties.

7.2 Configure Components

Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus.

Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in the PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design.

7.3 Organize and Connect

You can build signal chains at the chip level by interconnecting user modules to each other and the I/O pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions.

In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer’s output to a digital signal, and a PWM to control the fan.

In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources.

7.4 Generate, Verify, and Debug

When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system.

Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code.

A complete code development environment allows you to develop and customize your applications in C, assembly language, or both.

The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the ICE where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.

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8. Document Conventions

8.1 Acronyms Used

This table lists the acronyms used in this data sheet.

Table 8-1. Acronyms

Acronym Description

AC alternating current

ADC analog-to-digital converter

API application programming interface

CPU central processing unit

CT continuous time

DAC digital-to-analog converter

DC direct current

EEPROM electrically erasable programmable read-only

FSR full scale range

GPIO general purpose I/O

ICE in-circuit emulator

IDE integrated development environment

I/O input/output

ISSP in-system serial programming

IPOR imprecise power on reset

LSb least-significant bit

LVD low voltage detect

MSb most-significant bit

PC program counter

PGA programmable gain amplifier

POR power on reset

PPOR precision power on reset

PSoC

PWM pulse width modulator

ROM read only memory

SC switched capacitor

SMP switch mode pump

SRAM static random access memory

memory

Programmable System-on-Chip™

8.2 Units of Measure

A units of measure table is located in the section

Electrical Specifications on page 20. Table 12-1 on page 20 lists

all the abbreviations used to measure the PSoC devices.

8.3 Numeric Naming

Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.

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9. Pinouts

A, I, P0[7 ] A, IO, P0[5 ] A, IO, P0[3 ]

A, I, P0[1 ]

P2[ 7] P2[ 5]

A, I, P2[3 ]

A, I, P2[1 ]

SMP

I2 C SCL , P1[7 ]

I2 C SDA, P1 [5 ]

P1[ 3]

I2 C SCL , XTALi n , P1 [1 ]

Vss

Vdd P0[6 ], A, I P0[4 ], A, IO P0[2 ], A, IO P0[0 ], A, I P2[6], Ex ter n a l VREF P2[4], Ex ter n a l AGND P2[2 ], A, I P2[0 ], A, I XRES P1 [6] P1[4], EXT CL K P1 [2] P1[0 ], XTALou t, I2 C SDA

PDIP

SSOP

SOIC

1 2 3 4 5 6 7 8

9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

The CY8C29x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, SMP, and XRES are not capable of Digital I/O.

9.1 28-Pin Part Pinout

Table 9-1. 28-Pin Part Pinout (PDIP, SSOP, SOIC)

No.

1 I/O I P0[7] Analog column mux input. 2 I/O I/O P0[5] Analog column mux input and column output. 3 I/O I/O P0[3] Analog column mux input and column output. 4 I/O I P0[1] Analog column mux input. 5 I/O P2[7] 6 I/O P2[5] 7 I/O I P2[3] Direct switched capacitor block input. 8 I/O I P2[1] Direct switched capacitor block input. 9 Power SMP Switch Mode Pump (SMP) connection to

10 I/O P1[7] I2C Serial Clock (SCL). 11 I/O P1[5] I2C Serial Data (SDA). 12 I/O P1[3] 13 I/O P1[1] Crystal (XTALin), I2C Serial Clock (SCL),

14 Power Vss Ground connection. 15 I/O P1[0] Crystal (XTALout), I2C Serial Data (SDA),

16 I/O P1[2] 17 I/O P1[4] Optional External Clock Input (EXTCLK). 18 I/O P1[6] 19 Input XRES Active high external reset with internal pull

20 I/O I P2[0] Direct switched capacitor block input. 21 I/O I P2[2] Direct switched capacitor block input. 22 I/O P2[4] External Analog Ground (AGND). 23 I/O P2[6] External Voltage Reference (VREF). 24 I/O I P0[0] Analog column mux input. 25 I/O I/O P0[2] Analog column mux input and column output. 26 I/O I/O P0[4] Analog column mux input and column output. 27 I/O I P0[6] Analog column mux input. 28 Power Vdd Supply voltage.

LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.

Typ e

Digital Analog

Name

external components required.

ISSP-SCLK*.

ISSP-SDATA*.

down.

Description

Figure 9-1. CY8C29466 28-Pin PSoC Device

Document Number: 38-12013 Rev. *M Page 9 of 47

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CY8C29466, CY8C29566 CY8C29666, CY8C29866

9.2 44-Pin Part Pinout

TQFP

P3[1]

P2[7]

P2[5] P2[4], External AGND A, I, P2[3] P2[2], A, I A, I, P2[1] P2[0], A, I

P4[7]

P4[6]

P4[5]

P4[4]

P4[3]

P4[2]

P4[1]

P4[0]

SMP X RE S

P3[7]

P3[6] P3[5] P3[4] P3[3] P3[2]

I2C SCL, P1[7]

P0[1], A, I

I2C SDA, P1[5]

P0[3], A, IO

P1[3]

P0[5], A, IO

I2C SCL, XTALin, P1[1]

P0[7], A, I

Vss

Vdd

I2C SDA, XTALout, P1[0]

P0[6], A, I

P1[2]

P0[4], A, IO

EXTCLK, P1[4]

P0[2], A, IO

P1[6]

P0[0], A, I

P3[0]

P2[6], External VREF

33 32 31 30 29 28 27 26

25 24 23

1 2 3 4 5 6 7 8 9

4443424140393837363534

192021

Table 9-2. 44-Pin Part Pinout (TQFP)

Pin No.

1 I/O P2[5] 2 I/O I P2[3] Direct switched capacitor block input. 3 I/O I P2[1] Direct switched capacitor block input. 4 I/O P4[7] 5 I/O P4[5] 6 I/O P4[3] 7 I/O P4[1] 8 Power SMP Switch Mode Pump (SMP) connection to

9 I/O P3[7] 10 I/O P3[5] 11 I/O P3[3] 12 I/O P3[1] 13 I/O P1[7] I2C Serial Clock (SCL). 14 I/O P1[5] I2C Serial Data (SDA). 15 I/O P1[3] 16 I/O P1[1] Crystal (XTALin), I2C Serial Clock (SCL),

17 Power Vss Ground connection. 18 I/O P1[0] Crystal (XTALout), I2C Serial Data (SDA),

19 I/O P1[2] 20 I/O P1[4] Optional External Clock Input (EXTCLK). 21 I/O P1[6] 22 I/O P3[0] 23 I/O P3[2] 24 I/O P3[4] 25 I/O P3[6] 26 Input XRES Active high external reset with internal pull

27 I/O P4[0] 28 I/O P4[2] 29 I/O P4[4] 30 I/O P4[6] 31 I/O I P2[0] Direct switched capacitor block input. 32 I/O I P2[2] Direct switched capacitor block input. 33 I/O P2[4] External Analog Ground (AGND). 34 I/O P2[6] External Voltage Reference (VREF). 35 I/O I P0[0] Analog column mux input. 36 I/O I/O P0[2] Analog column mux input and column output. 37 I/O I/O P0[4] Analog column mux input and column output. 38 I/O I P0[6] Analog column mux input. 39 Power Vdd Supply voltage. 40 I/O I P0[7] Analog column mux input. 41 I/O I/O P0[5] Analog column mux input and column output. 42 I/O I/O P0[3] Analog column mux input and column output. 43 I/O I P0[1] Analog column mux input. 44 I/O P2[7]

LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-ChipTechnical Reference Manual for details.

Typ e

Digital Analog

Name

external components required.

ISSP-SCLK*.

ISSP-SDATA*.

down.

Description

Figure 9-2. CY8C29566 44-Pin PSoC Device

Document Number: 38-12013 Rev. *M Page 10 of 47

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9.3 48-Pin Part Pinouts

SSOP

A, I, P0[7]

Vdd

A, IO, P0[5]

P0[6], A, I

A, IO, P0[3]

P0[2], A, IO

A, I, P0[1]

P0[4], A, IO

P2[7]

P0[0], A, I

P2[5]

P2[6], External VREF

A, I, P2[3]

P2[4], External AGND

A, I, P2[1]

P2[2], A, I

P4[7]

P2[0], A, I

P4[5]

P4[6]

P4[3]

P4[4]

P4[1]

P4[2]

SMP

P4[0]

P3[7]

XRES

P3[5]

P3[6]

P3[3]

P3[4]

P3[1]

P3[2]

P5[3]

P3[0]

P5[1]

P5[2]

I2C SCL, P1[7]

P5[0]

I2C SDA, P1[5]

P1[6]

P1[3]

P1[4], EXT CLK

I2C SCL, XTALin, P1[1] P1[2]

Vss P1[0], XTALout, I2C SDA

1 2

3 4

6 7

9 10 11 12 13

16 17 18 19 20

22 23

48 47 46 45

39 38 37 36 35

32 31 30

29 28 27 26 25

Table 9-3. 48-Pin Part Pinout (SSOP)

Pin No.

14 I/O P3[7] 15 I/O P3[5] 16 I/O P3[3] 17 I/O P3[1] 18 I/O P5[3] 19 I/O P5[1] 20 I/O P1[7] I2C Serial Clock (SCL). 21 I/O P1[5] I2C Serial Data (SDA). 22 I/O P1[3] 23 I/O P1[1] Crystal (XTALin), I2C Serial Clock (SCL),

24 Power Vss Ground connection. 25 I/O P1[0] Crystal (XTALout), I2C Serial Data (SDA),

26 I/O P1[2] 27 I/O P1[4] Optional External Clock Input (EXTCLK). 28 I/O P1[6] 29 I/O P5[0] 30 I/O P5[2] 31 I/O P3[0] 32 I/O P3[2] 33 I/O P3[4] 34 I/O P3[6] 35 Input XRES Active high external reset with internal pull

36 I/O P4[0] 37 I/O P4[2] 38 I/O P4[4] 39 I/O P4[6] 40 I/O I P2[0] Direct switched capacitor block input. 41 I/O I P2[2] Direct switched capacitor block input. 42 I/O P2[4] External Analog Ground (AGND). 43 I/O P2[6] External Voltage Reference (VREF). 44 I/O I P0[0] Analog column mux input. 45 I/O I/O P0[2] Analog column mux input and column output. 46 I/O I/O P0[4] Analog column mux input and column output. 47 I/O I P0[6] Analog column mux input. 48 Power Vdd Supply voltage.

Document Number: 38-12013 Rev. *M Page 11 of 47

Typ e

Digital Analog

Name

external components required.

ISSP-SCLK*.

ISSP-SDATA*.

down.

Description

Figure 9-3. CY8C29666 48-Pin PSoC Device

[+] Feedback

CY8C29466, CY8C29566 CY8C29666, CY8C29866

QFN

(Top View)

P2[5]

P2[7]

P0 [1 ], A , I

P0 [3 ], A , IO

P0 [5 ], A , IO

P0 [7 ], A , I

Vdd

P0 [6 ], A , I

P0 [4 ], A , IO

P0 [2 ], A , IO

P0 [0 ], A , I

P2 [6 ], E xtern a l V REF

10 11

A, I, P2[3] A, I, P2[1]

P4[7] P4[5] P4[3] P4[1]

SMP P3[7] P3[5] P3[3] P3[1] P5[3]

35 34 33 32 31 30 29 28 27 26 25

4847464544

43424140393837

P2[2], A, I

P2[0], A, I P4[6] P4[4]

P4[2] P4[0] XRES

P3[6] P3[4]

P3[2] P3[0]

P2[4], External AGND

1 2

3 4 5 6

7 8 9

1314151617181920212223

P5[1]

I2C SCL, P1[7 ]

I2C SDA, P1[5]

P1[3]

I2C SCL, XTALi n, P1 [1 ]

Vss

I2C SDA , XTA Lo u t, P 1[0]

P1[2]

EXTCLK, P1[4]

P1[6]

P5[0]

P5[2]

Table 9-4. 48-Pin Part Pinout (QFN)**

Pin No.

1 I/O I P2[3] Direct switched capacitor block input.

2 I/O I P2[1] Direct switched capacitor block input.

3 I/O P4[7]

4 I/O P4[5]

5 I/O P4[3]

6 I/O P4[1]

7 Power SMP Switch Mode Pump (SMP) connection to

8 I/O P3[7]

9 I/O P3[5]

10 I/O P3[3]

11 I/O P3[1]

12 I/O P5[3]

13 I/O P5[1]

14 I/O P1[7] I2C Serial Clock (SCL).

15 I/O P1[5] I2C Serial Data (SDA).

16 I/O P1[3]

17 I/O P1[1] Crystal (XTALin), I2C Serial Clock (SCL),

18 Power Vss Ground connection.

19 I/O P1[0] Crystal (XTALout), I2C Serial Data (SDA),

20 I/O P1[2]

21 I/O P1[4] Optional External Clock Input (EXTCLK).

22 I/O P1[6]

23 I/O P5[0]

24 I/O P5[2]

25 I/O P3[0]

26 I/O P3[2]

27 I/O P3[4]

28 I/O P3[6]

29 Input XRES Active high external reset with internal pull

30 I/O P4[0]

31 I/O P4[2]

32 I/O P4[4]

33 I/O P4[6]

34 I/O I P2[0] Direct switched capacitor block input.

35 I/O I P2[2] Direct switched capacitor block input.

36 I/O P2[4] External Analog Ground (AGND).

37 I/O P2[6] External Voltage Reference (VREF).

38 I/O I P0[0] Analog column mux input.

39 I/O I/O P0[2] Analog column mux input and column output.

40 I/O I/O P0[4] Analog column mux input and column output.

41 I/O I P0[6] Analog column mux input.

42 Power Vdd Supply voltage.

43 I/O I P0[7] Analog column mux input.

44 I/O I/O P0[5] Analog column mux input and column output.

45 I/O I/O P0[3] Analog column mux input and column output.

46 I/O I P0[1] Analog column mux input.

47 I/O P2[7]

48 I/O P2[5]

Typ e

Digital Analog

Name

external components required.

ISSP-SCLK*.

ISSP-SDATA*.

down.

Description

Figure 9-4. CY8C29666 48-Pin PSoC Device

Document Number: 38-12013 Rev. *M Page 12 of 47

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9.4 100-Pin Part Pinout

Table 9-5. 100-Pin Part Pinout (TQFP)

Pin No.

1 NC No connection. 51 NC No connection. 2 NC No connection. 52 I/O P5[0] 3 I/O I P0[1] Analog column mux input. 53 I/O P5[2] 4 I/O P2[7] 54 I/O P5[4] 5 I/O P2[5] 55 I/O P5[6] 6 I/O I P2[3] Direct switched capacitor block input. 56 I/O P3[0] 7 I/O I P2[1] Direct switched capacitor block input. 57 I/O P3[2] 8 I/O P4[7] 58 I/O P3[4] 9 I/O P4[5] 59 I/O P3[6] 10 I/O P4[3] 60 NC No connection. 11 I/O P4[1] 61 NC No connection. 12 NC No connection. 62 Input XRES Active high external reset with internal pull

13 NC No connection. 63 I/O P4[0] 14 Power SMP Switch Mode Pump (SMP) connection to

15 Power Vss Ground connection. 65 Power Vss Ground connection. 16 I/O P3[7] 66 I/O P4[4] 17 I/O P3[5] 67 I/O P4[6] 18 I/O P3[3] 68 I/O I P2[0] Direct switched capacitor block input. 19 I/O P3[1] 69 I/O I P2[2] Direct switched capacitor block input. 20 I/O P5[7] 70 I/O P2[4] External Analog Ground (AGND). 21 I/O P5[5] 71 NC No connection. 22 I/O P5[3] 72 I/O P2[6] External Voltage Reference (VREF). 23 I/O P5[1] 73 NC No connection. 24 I/O P1[7] I2C Serial Clock (SCL). 74 I/O I P0[0] Analog column mux input. 25 NC No connection. 75 NC No connection. 26 NC No connection. 76 NC No connection. 27 NC No connection. 77 I/O I/O P0[2] Analog column mux input and column output. 28 I/O P1[5] I2C Serial Data (SDA). 78 NC No connection. 29 I/O P1[3] 79 I/O I/O P0[4] Analog column mux input and column output. 30 I/O P1[1] Crystal (XTALin), I2C Serial Clock (SCL),

31 NC No connection. 81 I/O I P0[6] Analog column mux input. 32 Power Vdd Supply voltage. 82 Power Vdd Supply voltage. 33 NC No connection. 83 Power Vdd Supply voltage. 34 Power Vss Ground connection. 84 Power Vss Ground connection. 35 NC No connection. 85 Power Vss Ground connection. 36 I/O P7[7] 86 I/O P6[0] 37 I/O P7[6] 87 I/O P6[1] 38 I/O P7[5] 88 I/O P6[2] 39 I/O P7[4] 89 I/O P6[3] 40 I/O P7[3] 90 I/O P6[4] 41 I/O P7[2] 91 I/O P6[5] 42 I/O P7[1] 92 I/O P6[6] 43 I/O P7[0] 93 I/O P6[7] 44 I/O P1[0] Crystal (XTALout), I2C Serial Data (SDA),

45 I/O P1[2] 95 I/O I P0[7] Analog column mux input. 46 I/O P1[4] Optional External Clock Input (EXTCLK). 96 NC No connection. 47 I/O P1[6] 97 I/O I/O P0[5] Analog column mux input and column output. 48 NC No connection. 98 NC No connection. 49 NC No connection. 99 I/O I/O P0[3] Analog column mux input and column output. 50 NC No connection. 100 NC No connection.

Typ e

Digital Analog Digital Analog

Name Description

external components required.

ISSP-SCLK*.

ISSP-SDATA*.

Pin No.

64 I/O P4[2]

80 NC No connection.

94 NC No connection.

Typ e

Name Description

down.

Document Number: 38-12013 Rev. *M Page 13 of 47

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Figure 9-5. CY8C29866 100-Pin PSoC Device

TQF P

NC NC

A, I, P0[1]

P2[7] P2[5]

A, I, P2[3]

A, I, P2[1]

P4[7] P4[5] P4[3]

P4[1]

NC NC

SMP

Vss P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1]

I2C SCL, P1[7]

Vss

P7[3]

EXTCLK, P1[4]

I2C SDA, P1[5]

P1[3]

XTALin, I2C SCL, P1[1]

Vdd

P7[7]

P7[6]

P7[5]

P7[4]

P7[2]

P7[1]

P7[0]

XTALout, I2C SDA, P1[0]

P1[2]

P1[6]

NCNCNC

NC P0[0], A, I NC P2[6], External VREF NC

P2[4], External AGND P2[2], A, I

P2[0], A, I P4[6] P4[4] Vss P4[2]

P4[0] XRES NC

NC P3[6] P3[4] P3[2] P3[0] P5[6]

P5[4] P5[2]

P5[0] NC

P0[3], A, IONCP0[5], A, IONCP0[7], A, INCP6[7]

P6[6]

P6[5]

P6[4]

P6[3]

P6[2]

P6[1]

P6[0]

Vss

Vdd

P0[6], A, INCP0[4], A, IONCP0[2], A, IO

75 74

73 72 71

70 69 68

67 66 65 64 63 62 61 60 59 58 57 56 55

54 53 52 51

100

9998979695949392919089888786858483828180797877

10 11 12 13 14 15 16 17 18

19 20

21 22 23 24 25

1 2 3 4 5 6 7 8 9

26272829303132333435363738394041424344454647485049

Document Number: 38-12013 Rev. *M Page 14 of 47

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9.5 100-Pin Part Pinout (On-Chip Debug)

The 100-pin TQFP part is for the CY8C29000 On-Chip Debug (OCD) PSoC device.

Note OCD parts are only used for in-circuit debugging. OCD parts are NOT available for production

Table 9-6. 100-Pin OCD Part Pinout (TQFP)

Pin No.

1 NC No internal connection. 51 NC No internal connection. 2 NC No internal connection. 52 I/O P5[0] 3 I/O I P0[1] Analog column mux input. 53 I/O P5[2] 4 I/O P2[7] 54 I/O P5[4] 5 I/O P2[5] 55 I/O P5[6] 6 I/O I P2[3] Direct switched capacitor block input. 56 I/O P3[0] 7 I/O I P2[1] Direct switched capacitor block input. 57 I/O P3[2] 8 I/O P4[7] 58 I/O P3[4] 9 I/O P4[5] 59 I/O P3[6] 10 I/O P4[3] 60 HCLK OCD high speed clock output 11 I/O P4[1] 61 CCLK OCD CPU clock output 12 OCDE OCD even data I/O 62 Input XRES Active high pin reset with internal pull down. 13 OCDO OCD odd data output 63 I/O P4[0] 14 Power SMP Switch Mode Pump (SMP) connection to

15 Power Vss Ground connection. 65 Power Vss Ground connection. 16 I/O P3[7] 66 I/O P4[4] 17 I/O P3[5] 67 I/O P4[6] 18 I/O P3[3] 68 I/O I P2[0] Direct switched capacitor block input. 19 I/O P3[1] 69 I/O I P2[2] Direct switched capacitor block input. 20 I/O P5[7] 70 I/O P2[4] External Analog Ground (AGND) input. 21 I/O P5[5] 71 NC No internal connection. 22 I/O P5[3] 72 I/O P2[6] External Voltage Reference (VREF) input. 23 I/O P5[1] 73 NC No internal connection. 24 I/O P1[7] I2C Serial Clock (SCL) 74 I/O I P0[0] Analog column mux input. 25 NC No internal connection. 75 NC No internal connection. 26 NC No internal connection. 76 NC No internal connection. 27 NC No internal connection. 77 I/O I/O P0[2] Analog column mux input and column output. 28 I/O P1[5] I2C Serial Data (SDA). 78 NC No internal connection. 29 I/O P1[3] I

30 I/O P1[1]* Crystal (XTALin), I2C Serial Clock (SCL), TC

31 NC No internal connection. 81 I/O I P0[6] Analog column mux input. 32 Power Vdd Supply voltage. 82 Power Vdd Supply voltage. 33 NC No internal connection. 83 Power Vdd Supply voltage. 34 Power Vss Ground connection. 84 Power Vss Ground connection. 35 NC No internal connection. 85 Power Vss Ground connection. 36 I/O P7[7] 86 I/O P6[0] 37 I/O P7[6] 87 I/O P6[1] 38 I/O P7[5] 88 I/O P6[2] 39 I/O P7[4] 89 I/O P6[3] 40 I/O P7[3] 90 I/O P6[4] 41 I/O P7[2] 91 I/O P6[5] 42 I/O P7[1] 92 I/O P6[6] 43 I/O P7[0] 93 I/O P6[7] 44 I/O P1[0]* Crystal (XTALout), I2C Serial Data (SDA), TC

45 I/O P1[2] V 46 I/O P1[4] Optional External Clock Input (EXTCLK) 96 NC No internal connection. 47 I/O P1[6] 97 I/O I/O P0[5] Analog column mux input and column output. 48 NC No internal connection. 98 NC No internal connection. 49 NC No internal connection. 99 I/O I/O P0[3] Analog column mux input and column output. 50 NC No internal connection. 100 NC No internal connection.

LEGEND A = Analog, I = Input, O = Output, NC = No Connection, TC/TM: Test.

Name Description

Digital

Analog

required external components.

79 I/O I/O P0[4] Analog column mux input and column output,

FMTEST

SCLK.

SDATA

FMTEST

* ISSP pin which is not HiZ at POR.

Pin No.

Digital

64 I/O P4[2]

80 NC No internal connection.

94 NC No internal connection.

95 I/O I P0[7] Analog column mux input.

Name Description

Analog

REF

Document Number: 38-12013 Rev. *M Page 15 of 47

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Figure 9-6. CY8C29000 OCD (Not for Production)

OCD TQFP

100

9998979695949392919089888786858483828180797877

10 11 12 13 14 15 16 17 18

19 20 21 22

23 24

1 2 3 4 5 6 7 8 9

AI, P0[1]

P2[7] P2[5]

AI, P2[3]

AI, P2[1]

P4[7] P4[5]

P4[3] P4[1]

OCDE

OCDO

SMP

Vss P3[7] P3[5]

P3[3] P3[1] P5[7]

P5[5] P5[3] P5[1]

I2C SCL, P1[7]

26272829303132333435363738394041424344454647485049

Vss

P7[3]

EXTCLK, P1[4]

I2C SDA, P1[5]

P1[3]

XTALin, I2C SCL, P1[1]

Vdd

P7[7]

P7[6]

P7[5]

P7[4]

P7[2]

P7[1]

P7[0]

XTALout, I2C SDA, P1[0]

P1[2]

P1[6]

NCNCNC

75 74

73 72 71

70 69 68

67 66 65 64 63 62 61 60 59 58 57 56 55

54 53 52

NC P0[0], AI

NC P2[6], External VREF

NC P2[4], External AGND P2[2], AI P2[0], AI P4[6] P4[4]

Vss P4[2]

P4[0] XRES

CCLK HCLK P3[6] P3[4] P3[2] P3[0] P5[6]

P5[4] P5[2] P5[0]

P0[3], AIONCP0[5], AIONCP0[7], AINCP6[7]

P6[6]

P6[5]

P6[4]

P6[3]

P6[2]

P6[1]

P6[0]

Vss

Vdd

P0[6], AINCP0[4], AIONCP0[2], AIO

Document Number: 38-12013 Rev. *M Page 16 of 47

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This section lists the registers of the CY8C29x66 PSoC device. For detailed register information, reference the PSoC Programmable System-on-Chip Technical Reference Manual.

10. Register Conventions

10.1 Abbreviations Used

The register conventions specific to this section are listed in the following table.

Convention Description

R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific

11. Register Mapping Tables

The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1.

Note In the following register mapping tables, blank fields are reserved and should not be accessed.

Document Number: 38-12013 Rev. *M Page 17 of 47

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Table 11-1. Register Map Bank 0 Table: User Space

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access

PRT0DR 00 RW DBB20DR0 40 # ASC10CR0 80 RW RDI2RI C0 RW PRT0IE 01 RW DBB20DR1 41 W ASC10CR1 81 RW RDI2SYN C1 RW PRT0GS 02 RW DBB20DR2 42 RW ASC10CR2 82 RW RDI2IS C2 RW PRT0DM2 03 RW DBB20CR0 43 # ASC10CR3 83 RW RDI2LT0 C3 RW PRT1DR 04 RW DBB21DR0 44 # ASD11CR0 84 RW RDI2LT1 C4 RW PRT1IE 05 RW DBB21DR1 45 W ASD11CR1 85 RW RDI2RO0 C5 RW PRT1GS 06 RW DBB21DR2 46 RW ASD11CR2 86 RW RDI2RO1 C6 RW PRT1DM2 07 RW DBB21CR0 47 # ASD11CR3 87 RW C7 PRT2DR 08 RW DCB22DR0 48 # ASC12CR0 88 RW RDI3RI C8 RW PRT2IE 09 RW DCB22DR1 49 W ASC12CR1 89 RW RDI3SYN C9 RW PRT2GS 0A RW DCB22DR2 4A RW ASC12CR2 8A RW RDI3IS CA RW PRT2DM2 0B RW DCB22CR0 4B # ASC12CR3 8B RW RDI3LT0 CB RW PRT3DR 0C RW DCB23DR0 4C # ASD13CR0 8C RW RDI3LT1 CC RW PRT3IE 0D RW DCB23DR1 4D W ASD13CR1 8D RW RDI3RO0 CD RW PRT3GS 0E RW DCB23DR2 4E RW ASD13CR2 8E RW RDI3RO1 CE RW PRT3DM2 0F RW DCB23CR0 4F # ASD13CR3 8F RW CF PRT4DR 10 RW DBB30DR0 50 # ASD20CR0 90 RW CUR_PP D0 RW PRT4IE 11 RW DBB30DR1 51 W ASD20CR1 91 RW STK_PP D1 RW PRT4GS 12 RW DBB30DR2 52 RW ASD20CR2 92 RW D2 PRT4DM2 13 RW DBB30CR0 53 # ASD20CR3 93 RW IDX_PP D3 RW PRT5DR 14 RW DBB31DR0 54 # ASC21CR0 94 RW MVR_PP D4 RW PRT5IE 15 RW DBB31DR1 55 W ASC21CR1 95 RW MVW_PP D5 RW PRT5GS 16 RW DBB31DR2 56 RW ASC21CR2 96 RW I2C_CFG D6 RW PRT5DM2 17 RW DBB31CR0 57 # ASC21CR3 97 RW I2C_SCR D7 # PRT6DR 18 RW DCB32DR0 58 # ASD22CR0 98 RW I2C_DR D8 RW PRT6IE 19 RW DCB32DR1 59 W ASD22CR1 99 RW I2C_MSCR D9 # PRT6GS 1A RW DCB32DR2 5A RW ASD22CR2 9A RW INT_CLR0 DA RW PRT6DM2 1B RW DCB32CR0 5B # ASD22CR3 9B RW INT_CLR1 DB RW PRT7DR 1C RW DCB33DR0 5C # ASC23CR0 9C RW INT_CLR2 DC RW PRT7IE 1D RW DCB33DR1 5D W ASC23CR1 9D RW INT_CLR3 DD RW PRT7GS 1E RW DCB33DR2 5E RW ASC23CR2 9E RW INT_MSK3 DE RW PRT7DM2 1F RW DCB33CR0 5F # ASC23CR3 9F RW INT_MSK2 DF RW DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW DBB00DR2 22 RW 62 A2 INT_VC E2 RC DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW DCB02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W DCB02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W DCB02DR2 2A RW 6A MUL1_DH AA R MUL0_DH EA R DCB02CR0 2B # 6B MUL1_DL AB R MUL0_DL EB R DCB03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW DCB03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW DCB03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW DCB03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW DBB10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0 DBB10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1 DBB10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2 DBB10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3 DBB11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4 DBB11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5 DBB11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6 DBB11CR0 37 # ACB01CR2 77 RW B7 CPU_F F7 RL DCB12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F8 DCB12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9 DCB12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FA DCB12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW FB DCB13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW FC DCB13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW FD DCB13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE # DCB13CR0 3F # ACB03CR2 7F RW BF CPU_SCR0 FF #

Blank fields are Reserved and should not be accessed. # Access is bit specific.

Document Number: 38-12013 Rev. *M Page 18 of 47

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Table 11-2. Register Map Bank 1 Table: Configuration Space

Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access

PRT0DM0 00 RW DBB20FN 40 RW ASC10CR0 80 RW RDI2RI C0 RW PRT0DM1 01 RW DBB20IN 41 RW ASC10CR1 81 RW RDI2SYN C1 RW PRT0IC0 02 RW DBB20OU 42 RW ASC10CR2 82 RW RDI2IS C2 RW PRT0IC1 03 RW 43 ASC10CR3 83 RW RDI2LT0 C3 RW PRT1DM0 04 RW DBB21FN 44 RW ASD11CR0 84 RW RDI2LT1 C4 RW PRT1DM1 05 RW DBB21IN 45 RW ASD11CR1 85 RW RDI2RO0 C5 RW PRT1IC0 06 RW DBB21OU 46 RW ASD11CR2 86 RW RDI2RO1 C6 RW PRT1IC1 07 RW 47 ASD11CR3 87 RW C7 PRT2DM0 08 RW DCB22FN 48 RW ASC12CR0 88 RW RDI3RI C8 RW PRT2DM1 09 RW DCB22IN 49 RW ASC12CR1 89 RW RDI3SYN C9 RW PRT2IC0 0A RW DCB22OU 4A RW ASC12CR2 8A RW RDI3IS CA RW PRT2IC1 0B RW 4B ASC12CR3 8B RW RDI3LT0 CB RW PRT3DM0 0C RW DCB23FN 4C RW ASD13CR0 8C RW RDI3LT1 CC RW PRT3DM1 0D RW DCB23IN 4D RW ASD13CR1 8D RW RDI3RO0 CD RW PRT3IC0 0E RW DCB23OU 4E RW ASD13CR2 8E RW RDI3RO1 CE RW PRT3IC1 0F RW 4F ASD13CR3 8F RW CF PRT4DM0 10 RW DBB30FN 50 RW ASD20CR0 90 RW GDI_O_IN D0 RW PRT4DM1 11 RW DBB30IN 51 RW ASD20CR1 91 RW GDI_E_IN D1 RW PRT4IC0 12 RW DBB30OU 52 RW ASD20CR2 92 RW GDI_O_OU D2 RW PRT4IC1 13 RW 53 ASD20CR3 93 RW GDI_E_OU D3 RW PRT5DM0 14 RW DBB31FN 54 RW ASC21CR0 94 RW D4 PRT5DM1 15 RW DBB31IN 55 RW ASC21CR1 95 RW D5 PRT5IC0 16 RW DBB31OU 56 RW ASC21CR2 96 RW D6 PRT5IC1 17 RW 57 ASC21CR3 97 RW D7 PRT6DM0 18 RW DCB32FN 58 RW ASD22CR0 98 RW D8 PRT6DM1 19 RW DCB32IN 59 RW ASD22CR1 99 RW D9 PRT6IC0 1A RW DCB32OU 5A RW ASD22CR2 9A RW DA PRT6IC1 1B RW 5B ASD22CR3 9B RW DB PRT7DM0 1C RW DCB33FN 5C RW ASC23CR0 9C RW DC PRT7DM1 1D RW DCB33IN 5D RW ASC23CR1 9D RW OSC_GO_EN DD RW PRT7IC0 1E RW DCB33OU 5E RW ASC23CR2 9E RW OSC_CR4 DE RW PRT7IC1 1F RW 5F ASC23CR3 9F RW OSC_CR3 DF RW DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW

DBB01FN 24 RW 64 A4 VLT_CMP E4 R DBB01IN 25 RW 65 A5 E5 DBB01OU 26 RW AMD_CR1 66 RW A6 E6

DCB02FN 28 RW ALT_CR1 68 RW A8 IMO_TR E8 W DCB02IN 29 RW CLK_CR2 69 RW A9 ILO_TR E9 W DCB02OU 2A RW 6A AA BDG_TR EA RW

DCB03FN 2C RW TMP_DR0 6C RW AC EC DCB03IN 2D RW TMP_DR1 6D RW AD ED DCB03OU 2E RW TMP_DR2 6E RW AE EE

DBB10FN 30 RW ACB00CR3 70 RW RDI0RI B0 RW F0 DBB10IN 31 RW ACB00CR0 71 RW RDI0SYN B1 RW F1 DBB10OU 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2

DBB11FN 34 RW ACB01CR3 74 RW RDI0LT1 B4 RW F4 DBB11IN 35 RW ACB01CR0 75 RW RDI0RO0 B5 RW F5 DBB11OU 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6

DCB12FN 38 RW ACB02CR3 78 RW RDI1RI B8 RW F8 DCB12IN 39 RW ACB02CR0 79 RW RDI1SYN B9 RW F9 DCB12OU 3A RW ACB02CR1 7A RW RDI1IS BA RW FLS_PR1 FA RW

DCB13FN 3C RW ACB03CR3 7C RW RDI1LT1 BC RW FC DCB13IN 3D RW ACB03CR0 7D RW RDI1RO0 BD RW FD DCB13OU 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #

Blank fields are Reserved and should not be accessed. # Access is bit specific.

23 AMD_CR0 63 RW A3 VLT_CR E3 RW

27 ALT_CR0 67 RW A7 DEC_CR2 E7 RW

2B 6B AB ECO_TR EB W

2F TMP_DR3 6F RW AF EF

33 ACB00CR2 73 RW RDI0LT0 B3 RW F3

37 ACB01CR2 77 RW B7 CPU_F F7 RL

3B ACB02CR2 7B RW RDI1LT0 BB RW FB

3F ACB03CR2 7F RW BF CPU_SCR0 FF #

Document Number: 38-12013 Rev. *M Page 19 of 47

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5.25

4.75

3.00

93 kHz 12 MHz 24 MHz

CPU Frequency

Vdd Vo l ta g e

5.25

4.75

3.00

93 kHz 12 MHz 24 MHz

IM O Freque ncy

Vdd Vo l ta ge

3.60

6 MHz

SLIMO Mode = 0

SLIMO

Mode=0

SLIMO

Mode=1

SLIMO

Mode=1

SLIMO

Mode=0

12. Electrical Specifications

This section presents the DC and AC electrical specifications of the CY8C29x66 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.

Specifications are valid for -40°C ≤ T on the internal main oscillator (IMO) using SLIMO mode.

≤ 85°C and TJ ≤ 100°C, except where noted. Refer to Table 12-17 for the electrical specifications

Figure 12-1. Voltage versus CPU Frequency Figure 12-2. IMO Frequency Options

The following table lists the units of measure that are used in this chapter.

Table 12-1. Units of Measure

Symbol Unit of Measure Symbol Unit of Measure

C degree Celsius μW microwatts

dB decibels mA milli-ampere

fF femto farad ms milli-second

Hz hertz mV milli-volts

KB 1024 bytes nA nanoampere

Kbit 1024 bits ns nanosecond

kHz kilohertz nV nanovolts

kΩ kilohm Ω ohm

MHz megahertz pA picoampere

MΩ megaohm pF picofarad

μA microampere pp peak-to-peak

μF microfarad ppm parts per million

μH microhenry ps picosecond

μs microsecond sps samples per second

μV microvolts σ sigma: one standard deviation

μVrms microvolts root-mean-square V volts

Document Number: 38-12013 Rev. *M Page 20 of 47

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12.1 Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Table 12-2. Absolute Maximum Ratings

Symbol Description Min Ty p Max Unit Notes

STG

Storage Temperature -55 25 +100

C Higher storage temperatures reduce

data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 65 reliability.

Ambient Temperature with Power Applied -40 – +85

Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 V

IOZ

MIO

MAIO

DC Input Voltage Vss- 0.5 – Vdd + 0.5 V

DC Voltage Applied to Tri-state Vss -

– Vdd + 0.5 V

0.5

Maximum Current into any Port Pin -25 – +50 mA

Maximum Current into any Port Pin Configured

-50 – +50 mA

as Analog Driver

ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD.

LU Latch up Current – – 200 mA

12.2 Operating Temperature

Table 12-3. Operating Temperature

C degrade

Symbol Description Min Ty p Max Unit Notes

Ambient Temperature -40 – +85 Junction Temperature -40 – +100

C The temperature rise from ambient

to junction is package specific. See

“Thermal Impedances” on page 42.

The user must limit the power consumption to comply with this requirement.

Document Number: 38-12013 Rev. *M Page 21 of 47

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12.3 DC Electrical Characteristics

12.3.1 DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

Table 12-4. DC Chip-Level Specifications

Symbol Description Min Ty p Max Units Notes

Vdd Supply Voltage 3.00 – 5.25 V See DC POR, SMP, and LVD Specifications on page 27.

DD3

DDP

SBH

SBXTL

SBXTLH

REF

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Supply Current – 8 14 mA Conditions are 5.0V, TA = 25oC, CPU = 3 MHz,

SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz.

Supply Current – 5 9 mA Conditions are Vdd = 3.3V, TA = 25oC, CPU = 3 MHz,

Supply current when IMO = 6 MHz using SLIMO

– 2 3 mA Conditions are Vdd = 3.3V, TA = 25oC, CPU = 0.75 MHz,

mode.

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active.

Sleep (Mode) Current with POR, LVD, Sleep Timer,

– 3 10 μA Conditions are with internal slow speed oscillator,

– 4 25 μA Conditions are with internal slow speed oscillator,

WDT, and internal slow oscillator active.

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator, and 32 kHz crystal

– 4 12 μA Conditions are with properly loaded, 1 μW max,

SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz.

SYSCLK doubler disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz.

Vdd = 3.3V, -40 oC ≤ TA ≤ 55oC.

Vdd = 3.3V, 55

C < TA ≤ 85oC.

32.768 kHz crystal. Vdd = 3.3V, -40oC ≤ TA ≤ 55oC.

oscillator active.

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and 32 kHz crystal oscillator active.

– 5 27 μA Conditions are with properly loaded, 1 μW max,

32.768 kHz crystal. Vdd = 3.3V, 55oC < TA ≤ 85oC.

Reference Voltage (Bandgap) 1.28 1.3 1.32 V Trimmed for appropriate Vdd.

12.3.2 DC General Purpose I/O Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Table 12-5. DC GPIO Specifications

Symbol Description Min Ty p Max Unit Notes

OUT

Pull up Resistor 4 5.6 8 kΩ

Pull down Resistor 4 5.6 8 kΩ

High Output Level Vdd

- 1.0

Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads,

––VIOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads,

4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined I

budget.

4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined I

budget.

High Level Source Current 10 – – mA VOH = Vdd-1.0V, see the limitations of the total current in

the note for VOH

Low Level Sink Current 25 – – mA VOL = 0.75V, see the limitations of the total current in the

note for VOL

Input Low Level – – 0.8 V Vdd = 3.0 to 5.25.

Input High Level 2.1 – – V Vdd = 3.0 to 5.25.

Input Hysterisis – 60 – mV

Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA.

Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent. Temp = 25oC.

Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dependent. Temp = 25oC.

Document Number: 38-12013 Rev. *M Page 22 of 47

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12.3.3 DC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 12-6. 5V DC Operational Amplifier Specifications

Symbol Description Min Ty p Max Unit Notes

OSOA

TCV

EBOA

INOA

CMOA

CMRR

OLOA

OHIGHO

OLOWOA

SOA

PSRR

Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

Average Input Offset Voltage Drift – 7.0 35.0 μV/oC

OSOA

–1.6

1.3

–

1.2

–

7.5

mV mV mV

Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.

Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25oC.

Common Mode Voltage Range. All Cases, except highest. Power = High, Opamp Bias = High

Common Mode Rejection Ratio 60 – – dB

0.0 – Vdd

0.5 –

Vdd - 0.5VV

Open Loop Gain 80 – – dB

High Output Voltage Swing (internal signals) Vdd - .01 – – V

Low Output Voltage Swing (internal signals) – – 0.1 V

Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High

Supply Voltage Rejection Ratio 67 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or

–

150

–

300

–

600

–

1200

–

2400

–

4600

200 400

800 1600 3200 6400

μA μA μA μA μA μA

(Vdd - 1.25V) ≤ VIN ≤ Vdd.

Table 12-7. 3.3V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Unit Notes

OSOA

Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High

–

1.65

–

1.32

10 8 mV

High Power is 5 Volts Only

TCV

EBOA

INOA

CMOA

CMRR

OLOA

OHIGHO

OLOWOA

SOA

PSRR

Average Input Offset Voltage Drift – 7.0 35.0 μV/oC

OSOA

Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.

Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25oC.

Common Mode Voltage Range 0 – Vdd V

Common Mode Rejection Ratio 60 – – dB

Open Loop Gain 80 – – dB

High Output Voltage Swing (internal signals) Vdd - .01 – – V

Low Output Voltage Swing (internal signals) – – .01 V

Supply Voltage Rejection Ratio 54 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or

–

150

–

300

–

600

–

1200

–

2400

–

200

400

800 1600 3200

–

μA μA μA μA μA

–

Not Allowed

(Vdd - 1.25V) ≤ VIN ≤ Vdd

Document Number: 38-12013 Rev. *M Page 23 of 47

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12.3.4 DC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T apply to 5V at 25°C and are for design guidance only.

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters

Table 12-8. DC Low Power Comparator Specifications

Symbol Description Min Ty p Max Unit

REFLPC

SLPC

OSLPC

Low power comparator (LPC) reference voltage range 0.2 – Vdd - 1 V

LPC supply current – 10 40 μA

LPC voltage offset – 2.5 30 mV

12.3.5 DC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Table 12-9. 5V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Unit

OSOB

TCV

OSOB

CMOB

OUTOB

OHIGHOB

OLOWOB

SOB

PSRR

Input Offset Voltage (Absolute Value) – 3 12 mV

Average Input Offset Voltage Drift – +6 – μV/°C

Common-Mode Input Voltage Range 0.5 – Vdd - 1.0 V

Output Resistance Power = Low Power = High

High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High

Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High

Supply Current Including Bias Cell (No Load) Power = Low Power = High

Supply Voltage Rejection Ratio 40 64 – dB

– –

0.5 x Vdd + 1.3

0.5 x Vdd

+ 1.3

– –

––0.5 x Vdd - 1.3

1.1

2.6

1 1

– –

0.5 x Vdd - 1.3VV

2 5

W W

V V

mA mA

Document Number: 38-12013 Rev. *M Page 24 of 47

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Table 12-10. 3.3V DC Analog Output Buffer Specifications

Note

3. L1 = 2 μH inductor, C1 = 10 μF capacitor, D1 = Schottky diode. See Figure 12-3..

Symbol Description Min Ty p Max Units

OSOB

TCV

OSOB

CMOB

OUTOB

OHIGHOB

OLOWOB

SOB

PSRR

Input Offset Voltage (Absolute Value) – 3 12 mV

Average Input Offset Voltage Drift – +6 – μV/°C

Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 V

Output Resistance Power = Low Power = High

– –

10 10

W W

High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High

Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High

Supply Current Including Bias Cell (No Load) Power = Low Power = High –

0.5 x Vdd + 1.0

0.5 x Vdd + 1.0––

– –

––0.5 x Vdd - 1.0

0.8

2.0

0.5 x Vdd

- 1.0

1 5

V V

mA mA

Supply Voltage Rejection Ratio 60 64 – dB

12.3.6 DC Switch Mode Pump Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Table 12-11. DC Switch Mode Pump (SMP) Specifications

Symbol Description Min Typ Max Unit Notes

5V 5V Output Voltage at Vdd from Pump 4.75 5.0 5.25 V Configuration of footnote.

PUMP

3V 3V Output Voltage at Vdd from Pump 3.00 3.25 3.60 V Configuration of footnote.

PUMP

5V Input Voltage Range from Battery 1.8 – 5.0 V Configuration of footnote.

BAT

3V Input Voltage Range from Battery 1.0 – 3.3 V Configuration of footnote.

BAT

BATSTART

ΔV

PUMP_Line

ΔV

PUMP_Load

ΔV

PUMP_Ripple

PUMP

Available Output Current V

= 1.5V, V

BAT

= 1.8V, V

BAT

Minimum Input Voltage from Battery

PUMP PUMP

= 3.25V = 5.0V

–

––mA

–

1.2 – – V Configuration of footnote.

to Start Pump

Line Regulation (over V

range) – 5 – %VOConfiguration of footnote.

BAT

Load Regulation – 5 – %VOConfiguration of footnote.

Output Voltage Ripple (depends on capacitor/load)

– 100 – mVppConfiguration of footnote.

Efficiency 35 50 – % Configuration of footnote.

Switching Frequency – 1.4 – MHz

Switching Duty Cycle – 50 – %

voltage is set to 5.0V.

voltage is set to 3.25V.

Configuration of footnote. SMP trip voltage is set to 3.25V.

SMP trip voltage is set to 5.0V.

specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 3-15 on page 27.

set to 3.25V.

[3]

Average, neglecting ripple. SMP trip

[3]

Average, neglecting ripple. SMP trip

[3]

SMP trip voltage is set to 5.0V.

[3]

SMP trip voltage is set to 3.25V.

[3] 0o

C ≤ TA ≤ 100. 1.25V at TA = -40oC.

[3]

VO is the “Vdd Value for PUMP Trip”

[3]

VO is the “Vdd Value for PUMP Trip”

[3]

Load is 5 mA.

[3]

Load is 5 mA. SMP trip voltage is

Document Number: 38-12013 Rev. *M Page 25 of 47

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Figure 12-3. Basic Switch Mode Pump Circuit

Batter y

PSoC

Vdd

Vss

SMP

BAT

PUMP

12.3.7 DC Analog Reference Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high.

Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the AGND.

Table 12-12. 5V DC Analog Reference Specifications

Symbol Description Min Ty p Max Unit

BG5

– AGND = Vdd/2 – AGND = 2 x BandGap – AGND = P2[4] (P2[4] = Vdd/2) – AGND = BandGap – AGND = 1.6 x BandGap – AGND Block to Block Variation (AGND = Vdd/2) – RefHi = Vdd/2 + BandGap Vdd/2 + 1.21 Vdd/2 + 1.3 Vdd/2 + 1.382 V – RefHi = 3 x BandGap 3.75 3.9 4.05 V – RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) P2[6] + 2.478 P2[6] + 2.6 P2[6] + 2.722 V – RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + 1.218 P2[4] + 1.3 P2[4] + 1.382 V – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] - 0.058 P2[4] + P2[6] P2[4] + P2[6] + 0.058 V – RefHi = 2 x BandGap 2.50 2.60 2.70 V – RefHi = 3.2 x BandGap 4.02 4.16 4.29 V – RefLo = BandGap BG - 0.082 BG + 0.023 BG + 0.129 V – RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134 V – RefLo = P2[4] – BandGap

– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110 V

Bandgap Voltage Reference 5V 1.28 1.30 1.32 V

(P2[4] = Vdd/2)

[4]

Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V

2.52 2.60 2.72 V

P2[4] - 0.013 P2[4] P2[4] + 0.013 V

1.27 1.3 1.34 V

[4]

2.03 2.08 2.13 V

-0.034 0.000 0.034 V

P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 V

Document Number: 38-12013 Rev. *M Page 26 of 47

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Note

4. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.

Table 12-13. 3.3V DC Analog Reference Specifications

Notes

5. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.

6. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.

Symbol Description Min Typ Max Unit

BG33

– AGND = Vdd/2

– AGND = 2 x BandGap – AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.009 P2[4] P2[4] + 0.009

– AGND = BandGap

– AGND = 1.6 x BandGap

– AGND Block to Block Variation (AGND = Vdd/2)

Bandgap Voltage Reference 3.3V 1.28 1.30 1.32

[4]

Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02

Not Allowed

1.27 1.30 1.34

2.03 2.08 2.13

[4]

-0.034 0.000 0.034

V V

V V V

– RefHi = Vdd/2 + BandGap Not Allowed – RefHi = 3 x BandGap Not Allowed – RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed – RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] - 0.042 P2[4] + P2[6] P2[4] + P2[6] + 0.042

– RefHi = 2 x BandGap 2.50 2.60 2.70

V V

– RefHi = 3.2 x BandGap Not Allowed – RefLo = Vdd/2 - BandGap

– RefLo = BandGap

– RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)

– RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

Not Allowed Not Allowed Not Allowed Not Allowed

12.3.8 DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Table 12-14. DC Analog PSoC Block Specifications

Symbol Description Min Typ Max Unit Notes

Resistor Unit Value (Continuous Time) – 12.2 – kΩ

Capacitor Unit Value (Switch Cap) – 80 – fF

12.3.9 DC POR, SMP, and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 12-15. DC POR, SMP, and LVD Specifications

Symbol Description Min Ty p Max Units Notes

Vdd Value for PPOR Trip (positive ramp)

PPOR0R

PPOR1R

PPOR2R

PPOR0

PPOR1

PPOR2

PH0

PH1

PH2

PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

–

– – –

2.91

4.39

4.55

2.82

4.39

4.55

0 0

–

– – –

V V V

mV mV mV

Document Number: 38-12013 Rev. *M Page 27 of 47

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Table 12-15. DC POR, SMP, and LVD Specifications (continued)

Symbol Description Min Ty p Max Units Notes

LVD 0

LVD 1

LVD 2

LVD 3

LVD 4

LVD 5

LVD 6

LVD 7

PUMP0

PUMP1

PUMP2

PUMP3

PUMP4

PUMP5

PUMP6

PUMP7

Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b

Vdd Value for SMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b

2.86

2.96

3.07

3.92

4.39

4.55

4.63

4.72

2.96

3.03

3.18

4.11

4.55

4.63

4.72

4.90

2.92

3.02

3.13

4.00

4.48

4.64

4.73

4.81

3.02

3.10

3.25

4.19

4.64

4.73

4.82

5.00

2.98

3.08

3.20

4.08

4.57

4.74

4.82

4.91

3.08

3.16

3.32

4.28

4.74

4.82

4.91

5.10

[5]

[6]

V V V V V V V V V

12.3.10 DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Table 12-16. DC Programming Specifications

Symbol Description Min Typ Max Units Notes

DDP

ILP

IHP

ILP

IHP

OLV

OHV

Flash

Supply Current During Programming or Verify – 10 30 mA

Input Low Voltage During Programming or Verify – – 0.8 V

Input High Voltage During Programming or Verify 2.2 – – V

Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify

Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify

– – 0.2 mA Driving internal pull down resistor.

– – 1.5 mA Driving internal pull down resistor.

Output Low Voltage During Programming or Verify – – Vss + 0.75 V

Output High Voltage During Programming or Verify Vdd - 1.0 – Vdd V

Flash Endurance (per block) 50,000

ENPB

Flash Endurance (total)

ENT

Flash Data Retention 10 – – Ye ar s

[8]

[7]

– – – Erase/write cycles per block.

1,800,000 – – – Erase/write cycles.

Document Number: 38-12013 Rev. *M Page 28 of 47

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12.4 AC Electrical Characteristics

Notes

7. The 50,000 cycle flash endurance per block will only be guaranteed if the flash is operating within one voltage range. Voltage ranges are 3.0V to 3.6V and 4.75V to 5.25V.

8. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

9. 4.75V < Vdd < 5.25V.

10. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.

11. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.

12. See the individual user module data sheets for information on maximum frequencies for user modules

12.4.1 AC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

Note See the individual user module data sheets for information on maximum frequencies for user modules.

Table 12-17. AC Chip-Level Specifications

Symbol Description Min Ty p Max Units Notes

IMO24

IMO6

CPU1

CPU2

48M

24M

32K1

32K2

Internal Low Speed Oscillator (ILO) Untrimmed

32K_U

PLL

Jitter24M2 24 MHz Period Jitter (PLL) – – 600 ps

PLLSLEW

PLLSLEWLOW

OSACC

Jitter32k 32 kHz Period Jitter – 100 – ns

XRST

DC24M 24 MHz Duty Cycle 40 50 60 %

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Internal Main Oscillator Frequency for 24 MHz 23.4 24 24.6

Internal Main Oscillator Frequency for 6 MHz 5.5 6 6.5

[9,10,11]

MHz Trimmed for 5V or 3.3V

operation using factory trim values. See the figure on page 19. SLIMO Mode = 0.

MHz Trimmed for 5V or 3.3V

operation using factory trim values. See the figure on page 19. SLIMO Mode = 1.

CPU Frequency (5V Nominal) 0.93 24 24.6

CPU Frequency (3.3V Nominal) 0.93 12 12.3

Digital PSoC Block Frequency 0 48 49.2

Digital PSoC Block Frequency 0 24 24.6

[9,10]

[10,11]

[9,10, 12]

[10, 12]

MHz

MHz Refer to the AC Digital Block

Specifications below.

MHz

Internal Low Speed Oscillator Frequency 15 32 64 kHz

External Crystal Oscillator – 32.768 – kHz Accuracy is capacitor and

crystal dependent. 50% duty cycle

Frequency

PLL Frequency – 23.986 – MHz A multiple (x732) of crystal

5 – – kHz After a reset and before the m8c

starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on timing this

frequency.

PLL Lock Time 0.5 – 10 ms

PLL Lock Time for Low Gain Setting 0.5 – 50 ms

External Crystal Oscillator Startup to 1% – 250 500 ms

External Crystal Oscillator Startup to 100 ppm – 300 600 ms The crystal oscillator frequency

is within 100 ppm of its final value by the end of the T period. Correct operation assumes a properly loaded 1 uW maximum drive level

32.768 kHz crystal. 3.0V

≤ 5.5V, -40°C ≤ T

≤ 85°C.

osacc

≤ Vdd

External Reset Pulse Width 10 – – μs

Document Number: 38-12013 Rev. *M Page 29 of 47

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Table 12-17. AC Chip-Level Specifications (continued)

24 MHz

PLL

Enable

PLLSLEW

PLL

Gai n

24 MHz

PLL

Enable

PLLSLEWLOW

PLL

Gai n

32 kHz

32K2

32K

Select

Jitter24M1

24M

Jitter32k

32K2

Symbol Description Min Ty p Max Units Notes

ILO

Step24M 24 MHz Trim Step Size – 50 – kHz

Fout48M 48 MHz Output Frequency 46.8 48.0 49.2

Jitter24M1 24 MHz Period Jitter (IMO) – 600 – ps

MAX

POWER_UP

POWERUP

Internal Low Speed Oscillator Duty Cycle 20 50 80 %

[9, 11]

Maximum frequency of signal on row input or row output.

Power Supply Slew Rate – – 250 V/ms Vdd slew rate during power up.

Time from end of POR to CPU executing code – 16 100 ms Power up from 0V. See the

– – 12.3 MHz

MHz Trimmed. Using factory trim

values.

System Resets section of the PSoC Technical Reference Manual.

Figure 12-4. PLL Lock Timing Diagram

Figure 12-5. PLL Lock for Low Gain Setting Timing Diagram

Figure 12-6. External Crystal Oscillator Startup Timing Diagram

Figure 12-7. 24 MHz Period Jitter (IMO) Timing Diagram

Figure 12-8. 32 kHz Period Jitter (ECO) Timing Diagram

Document Number: 38-12013 Rev. *M Page 30 of 47

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12.4.2 AC General Purpose I/O Specifications

TFallF TFallS

TRiseF

TRiseS

90%

10%

GPIO

Output

Voltage

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

°C ≤ T

are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Table 12-18. AC GPIO Specifications

Symbol Description Min Typ Max Unit Notes

GPIO

TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.75 to 5.25V, 10% - 90%

TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.75 to 5.25V, 10% - 90%

TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10% - 90%

TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10% - 90%

GPIO Operating Frequency 0 – 12.3 MHz Normal Strong Mode

Figure 12-9. GPIO Timing Diagram

12.4.3 AC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

°C ≤ T

are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.

Power = High and Opamp Bias = High is not supported at 3.3V.

Table 12-19. 5V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Unit

ROA

SOA

ROA

FOA

NOA

Rising Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

Falling Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

– – –

0.15

1.7

6.5

0.01

0.5

4.0

0.75

3.1

5.4

– – –

3.9

0.72

0.62

5.9

0.92

0.72

– – –

μs μs μs

μs

MHz MHz MHz

Document Number: 38-12013 Rev. *M Page 31 of 47

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Table 12-20. 3.3V AC Operational Amplifier Specifications

100

1000

10000

0.001 0.01 0.1 1 10 100Freq ( kHz)

dBV/rtHz

0.01

0.1

1.0 10

Symbol Description Min Typ Max Units

ROA

SOA

ROA

FOA

NOA

Rising Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High –

Falling Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High –

Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High 0.31

Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High 0.24

Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High

Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

–

2.7

1.8

0.67

2.8

–

3.92

–

0.72

–

5.41

–

0.72

– –

μs μs

μs

MHz MHz

When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.

Figure 12-10. Typical AGND Noise with P2[4] Bypass

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level.

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Figure 12-11. Typical Opamp Noise

100

1000

10000

0.001 0.01 0.1 1 10 100

Freq (kHz )

nV/rtHz

PH_ BH PH_ BL PM_ BL PL _B L

Note

13. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

12.4.4 AC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

°C ≤ T

and -40 apply to 5V at 25

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters

°C and are for design guidance only.

Table 12-21. AC Low Power Comparator Specifications

Symbol Description Min Ty p Max Unit Notes

RLPC

LPC response time – – 50 μs ≥ 50 mV overdrive comparator reference set within V

REFLPC

12.4.5 AC Digital Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

°C ≤ T

are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Table 12-22. AC Digital Block Specifications

Function Description Min Typ Max Unit Notes

All Functions

Timer Capture Pulse Width 50

Counter Enable Pulse Width 50

Dead Band Kill Pulse Width:

Maximum Block Clocking Frequency (> 4.75V) 49.2 MHz 4.75V < Vdd < 5.25V.

Maximum Block Clocking Frequency (< 4.75V) 24.6 MHz 3.0V < Vdd < 4.75V.

Maximum Frequency, No Capture – – 49.2 MHz 4.75V < Vdd < 5.25V.

Maximum Frequency, With Capture – – 24.6 MHz

Maximum Frequency, No Enable Input – – 49.2 MHz 4.75V < Vdd < 5.25V.

Maximum Frequency, Enable Input – – 24.6 MHz

Asynchronous Restart Mode 20 – – ns

Synchronous Restart Mode 50

Disable Mode 50

Maximum Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.

[13]

– – ns

[13]

– – ns

[13]

– – ns

[13]

– – ns

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Table 12-22. AC Digital Block Specifications (continued)

Function Description Min Typ Max Unit Notes

CRCPRS (PRS Mode)

CRCPRS (CRC Mode)

SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due to 2 x over clocking.

SPIS Maximum Input Clock Frequency – – 4.1 MHz

Transmitter Maximum Input Clock Frequency

Receiver Maximum Input Clock Frequency

Maximum Input Clock Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V.

Maximum Input Clock Frequency – – 24.6 MHz

Width of SS_ Negated Between Transmissions 50

≥ 4.75V, 2 Stop Bits

Vdd

≥ 4.75V, 2 Stop Bits

Vdd

[13]

– – MHz

––––24.6

49.2

––––24.6

49.2

MHz

Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking.

MHz

Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking.

MHz

12.4.6 AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40 are for design guidance only.

°C ≤ T

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Table 12-23. 5V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Unit

ROB

SOB

ROB

FOB

Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High

Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High

Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High

Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High

Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High

– –

0.5

0.55

0.8

300 300

– –

3.4

4 4

– –

μs μs

V/μs

μs

V/μs

μs

MHz MHz

kHz kHz

Table 12-24. 3.3V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Unit

ROB

SOB

ROB

FOB

Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High

Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High

Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High

Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High

Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High

– –

.36 .36

.4 .4

0.7

200 200

– –

4.7

μs μs

4 4

– –

μs μs

V/μs

μs

V/μs

μs

MHz MHz

kHz kHz

Document Number: 38-12013 Rev. *M Page 34 of 47

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12.4.7 AC External Clock Specifications

Note

14. For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

°C ≤ T

are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Table 12-25. 5V AC External Clock Specifications

Symbol Description Min Typ Max Unit

OSCEXT

– High Period 20.6

– Low Period 20.6

– Power Up IMO to Switch 150

Frequency 0.093 – 24.6 MHz

– 5300 ns

– –ns

– –ms

Table 12-26. 3.3V AC External Clock Specifications

Symbol Description Min Typ Max Unit

OSCEXT

– High Period with CPU Clock divide by 1 41.7

– Low Period with CPU Clock divide by 1 41.7

– Power Up IMO to Switch 150

Frequency with CPU Clock divide by 1 0.093 – 12.3 MHz

Frequency with CPU Clock divide by 2 or greater 0.186 – 24.6 MHz

– 5300 ns

– –ns

– – μs

12.4.8 AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

°C ≤ T

are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

Table 12-27. AC Programming Specifications

Symbol Description Min Ty p Max Unit Notes

RSCLK

FSCLK

SSCLK

HSCLK

SCLK

ERASEB

WRITE

DSCLK

DSCLK3

ERASEALL

PROGRAM_HOT

PROGRAM_COLD

Flash Erase Time (Bulk) – 80 – ms Erase all Blocks and

Rise Time of SCLK 1 – 20 ns

Fall Time of SCLK 1 – 20 ns

Data Set up Time to Falling Edge of SCLK 40 – – ns

Data Hold Time from Falling Edge of SCLK 40 – – ns

Frequency of SCLK 0 – 8 MHz

Flash Erase Time (Block) – 10 – ms

Flash Block Write Time – 40 – ms

Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6

Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6

protection fields at once

Flash Block Erase + Flash Block Write Time – – 100

Flash Block Erase + Flash Block Write Time – – 200

[14]

ms 0°C ≤ Tj ≤ 100°C

[14]

ms -40°C ≤ Tj ≤ 0°C

Document Number: 38-12013 Rev. *M Page 35 of 47

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12.4.9 AC I2C Specifications

Note

15. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t

SU;DAT

>= 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t

rmax

+ t

SU;DAT

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

SDA

SCL

Sr SP

BUF I2C

SPI2C

HDSTAI2C

SUSTOI2C

SUSTAI2C

LOWI2C

HIGHI2C

HDDATI2C

HDSTAI2C

SUDATI2C

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40

°C ≤ T

are for design guidance only.

Table 12-28. AC Characteristics of the I

Symbol Description

SCLI2C

HDSTAI2C

LOWI2C

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

SPI2C

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

C SDA and SCL Pins

Standard Mode Fast Mode

Min Max Min Max

SCL Clock Frequency 0 100 0 400 kHz

Hold Time (repeated) START Condition. After this period, the first clock pulse is generated.

LOW Period of the SCL Clock 4.7 –1.3– μs

HIGH Period of the SCL Clock 4.0 –0.6– μs

Set-up Time for a Repeated START Condition 4.7 –0.6– μs

Data Hold Time 0 –0– μs

Data Set-up Time 250 – 100

Set-up Time for STOP Condition 4.0 –0.6– μs

Bus Free Time Between a STOP and START Condition 4.7 –1.3– μs

Pulse Width of spikes are suppressed by the input filter. – – 0 50 ns

4.0 –0.6– μs

[15]

Unit

–ns

Figure 12-12. Definition for Timing for Fast/Standard Mode on the I2C Bus

Document Number: 38-12013 Rev. *M Page 36 of 47

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13. Packaging Information

DIMENSIONS IN INCHES[MM]

MIN. MAX.

SEATING PLANE

0.260[6.60]

0.295[7.49]

0.090[2.28]

0.110[2.79]

0.055[1.39]

0.065[1.65]

0.015[0.38]

0.020[0.50]

0.015[0.38]

0.060[1.52]

0.120[3.05]

0.140[3.55]

0.009[0.23]

0.012[0.30]

0.310[7.87]

0.385[9.78 ]

0.290[7.36]

0.325[8.25]

0.030[0.76]

0.080[2.03]

0.115[2.92]

0.160[4.06]

0.140[3.55]

0.190[4.82]

1.345[34.16]

1.385[35.18]

3° MIN.

114

15 28

REFERENCE JEDEC MO-095

PART #

P28.3 STANDARD PKG.

LEAD FREE PKG.PZ28.3

LEAD END OPTION

SEE LEAD END OPTION

(LEAD #1, 14, 15 & 28)

PACKAGE WEIGHT: 2.15gms

51-85014 *E

This section illustrates the packaging specifications for the CY8C29x66 PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of

the emulation tools’ dimensions, refer to the document titled

http://www.cypress.com/design/MR10161.

13.1 Packaging Dimensions

Figure 13-1. 28-Pin (300 mil) Molded DIP

PSoC Emulator Pod Dimensions at

Document Number: 38-12013 Rev. *M Page 37 of 47

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Figure 13-2. 28-Pin (210-Mil) SSOP

51-85079 *C

51-85079 *D

51-85026 *D

Figure 13-3. 28-Pin (300-Mil) SOIC

Document Number: 38-12013 Rev. *M Page 38 of 47

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Figure 13-4. 44-Pin TQFP

51-85064 *C

TOP VIEW

0.80 DIA.

6.70

6.90

1.00 MAX.

BOTTOM VIEW

SEATING PLANE

0.23±0.05

0.50

0.08

0°-12°

0.30-0.45

0.05 MAX.

0.20 REF.

0.80 MAX.

PIN1 ID

5.45

0.42±0.18 (4X)

SIDE VIEW

7.10

6.80

6.70

6.80

7.10

6.90

5.55

5.45

5.55

0.20 R.

0.45

5.1

1. HATCH AREA IS SOLDERABLE EXPOSED METAL.

2. REFERENCE JEDEC#: MO-220

4. ALL DIMENSIONS ARE IN MM [MIN/MAX]

NOTES

PART #

LEAD FREE

STANDARD

LY48A

5. PACKAGE CODE

DESCRIPTION

3. PACKAGE WEIGHT: 0.13g

LF48A

PAD

EXPOSED

SOLDERABLE

001-12919 *B

Document Number: 38-12013 Rev. *M Page 39 of 47

Figure 13-5. 48-Pin (7x7 mm) QFN

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Figure 13-6. 48-Pin (300-Mil) SSOP

51-85061-C

51-85061 *C

TOP VIEW

BOTTOM VIEW

0.40±0.10

0.200 REF.

PIN1 ID

SIDE VIEW

R 0.20

0.45

1. HATCH AREA IS SOLDERABLE EXPOSED METAL.

2. REFERENCE JEDEC#: MO-220

4. ALL DIMENSIONS ARE IN MILLIMETERS

NOTES

3. PACKAGE WEIGHT: 0.13g

PAD

EXPOSED

SOLDERABLE

LASER MARK

7.00±0.100

5.100 REF

PIN 1 DOT

13 24

SEATING PLANE

0.08

0.020

+0.025

-0.00

0.900±0.100

5.500±0.100

0.25

+0.05

-0.07

0.50 PITCH

001-13191 *E

Figure 13-7. 48-Pin QFN 7x7x 0.90 MM (Sawn Type)

Document Number: 38-12013 Rev. *M Page 40 of 47

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Figure 13-8. 100-Pin TQFP

51-85048 **51-85048 **

51-85048 *C

Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at

http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.

Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device.

Document Number: 38-12013 Rev. *M Page 41 of 47

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13.1 Thermal Impedances 13.2 Capacitance on Crystal Pins

Table 13-1. Thermal Impedances per Package

Package Typical θ

28 PDIP 69 oC/W

28 SSOP 94 oC/W

28 SOIC 67 oC/W

44 TQFP 60 oC/W

48 SSOP 69 oC/W

48 QFN** 28 oC/W

100 TQFP 50 oC/W

* TJ = TA + POWER x θ

** To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.

Table 13-2. Typical Package Capacitance on Crystal Pins

Package Package Capacitance

28 PDIP 3.5 pF

28 SSOP 2.8 pF

28 SOIC 2.7 pF

44 TQFP 2.6 pF

48 SSOP 3.3 pF

48 QFN 1.8 pF

100 TQFP 3.1 pF

13.3 Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 13-3. Solder Reflow Peak Temperature

Package

28 PDIP 220oC 260oC

28 SSOP 240oC 260oC

28 SOIC 220oC 260oC

44 TQFP 220oC 260oC

48 SSOP 220oC 260oC

48 QFN 220oC 260oC

100 TQFP 220oC 260oC

*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5

C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.

Minimum Peak Tempera-

ture*

Maximum Peak Temperature

Document Number: 38-12013 Rev. *M Page 42 of 47

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14. Development Tool Selection

This section presents the development tools available for all current PSoC device families including the CY8C29x66 family.

14.1 Software

14.1.1 PSoC Designer

At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at

http://www.cypress.com/psocdesigner and includes a free C

compiler.

14.1.2 PSoC Programmer

Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocpro-

grammer.

14.2 Development Kits

All development kits can be purchased from the Cypress Online Store.

14.2.1 CY3215-DK Basic Development Kit

The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes:

■ PSoC Designer Software CD

■ ICE-Cube In-Circuit Emulator

■ ICE Flex-Pod for CY8C29x66 Family

■ Cat-5 Adapter

■ Mini-Eval Programming Board

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

™

■ iMAGEcraft C Compiler (Registration Required)

■ ISSP Cable

■ USB 2.0 Cable and Blue Cat-5 Cable

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

14.3 Evaluation Tools

All evaluation tools can be purchased from the Cypress Online Store.

14.3.1 CY3210-MiniProg1

The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:

■ MiniProg Programming Unit

■ MiniEval Socket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

14.3.2 CY3210-PSoCEval1

The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

■ Evaluation Board with LCD Module

■ MiniProg Programming Unit

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

Document Number: 38-12013 Rev. *M Page 43 of 47

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14.3.3 CY3214-PSoCEvalUSB

Notes

16. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.

17. Foot kit includes surface mount feet that can be soldered to the target PCB.

18. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at

http://www.emulation.com

The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes:

■ PSoCEvalUSB Board

■ LCD Module

■ MIniProg Programming Unit

■ Mini USB Cable

■ PSoC Designer and Example Projects CD

■ Getting Started Guide

■ Wire Pack

14.4 Device Programmers

All device programmers can be purchased from the Cypress Online Store.

14.4.1 CY3216 Modular Programmer

The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular

programmer includes three programming module cards and supports multiple Cypress products. The kit includes:

■ Modular Programmer Base

■ 3 Programming Module Cards

■ MiniProg Programming Unit

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

14.4.2 CY3207ISSP In-System Serial Programmer (ISSP)

The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment.

Note: CY3207ISSP needs special software and is not

compatible with PSoC Programmer. The kit includes:

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

15. Accessories (Emulation and Programming)

Table 15-1. Emulation and Programming Accessories

Part #

Package

Flex-Pod Kit

CY8C29466-24PXI 28 PDIP CY3250-29XXX CY3250-28PDIP-FK Adapters can be found at

CY8C29466-24PVXI 28 SSOP CY3250-29XXX CY3250-28SSOP-FK

CY8C29466-24SXI 28 SOIC CY3250-29XXX CY3250-28SOIC-FK

CY8C29566-24AXI 44 TQFP CY3250-29XXX CY3250-44TQFP-FK

CY8C29666-24PVXI 48 SSOP CY3250-29XXX CY3250-48SSOP-FK

CY8C29666-24LFXI 48 QFN CY3250-29XXXQFN CY3250-48QFN-FK

CY8C29866-24AXI 100 TQFP CY3250-29XXX CY3250-100TQFP-FK

CY8C29466-24PXI 28 PDIP CY3250-29XXX CY3250-28PDIP-FK Adapters can be found at

15.1 Third Party Tools

Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards.

[16]

Foot Kit

[17]

Adapter

[18]

http://www.emulation.com.

15.2 Build a PSoC Emulator into Your Board

For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note “Debugging - Build a PSoC

Emulator into Your Board - AN2323”.

Document Number: 38-12013 Rev. *M Page 44 of 47

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16. Ordering Information

Note

19. This part may be used for in-circuit debugging. It is NOT available for production.

CY 8 C 29 xxx-SPxx

Package Type: Thermal Rating:

PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free

Speed: 24 MHz

Part Number

Family Code

Technology Code: C = CMOS

Marketing Code: 8 = Cypress PSoC

Company ID: CY = Cypress

The following table lists the CY8C29x66 PSoC device’s key package features and ordering codes.

Package

28 Pin (300 Mil) DIP CY8C29466-24PXI 32K 2K Yes -40C to +85C 16 12 24 12 4 Ye s 28 Pin (210 Mil) SSOP CY8C29466-24PVXI 32K 2K Ye s -40C to +85C 16 12 24 12 4 Yes 28 Pin (210 Mil) SSOP

(Tape and Reel) 28 Pin (300 Mil) SOIC CY8C29466-24SXI 32K 2K Ye s -40C to +85C 16 12 24 12 4 Yes 28 Pin (300 Mil) SOIC (Tape and Reel) 44 Pin TQFP CY8C29566-24AXI 32K 2K Ye s -40C to +85C 16 12 40 12 4 Ye s 44 Pin TQFP

(Tape and Reel) 48 Pin (300 Mil) SSOP CY8C29666-24PVXI 32K 2K Ye s -40C to +85C 16 12 44 12 4 Yes 48 Pin (300 Mil) SSOP

(Tape and Reel) 48 Pin QFN CY8C29666-24LFXI 32K 2K Yes -40C to +85C 16 12 44 12 4 Ye s 100 Pin TQFP CY8C29866-24AXI 32K 2K Yes -40C to +85C 16 12 64 12 4 Ye s

100 Pin OCD TQFP 48-Pin (7X7X 1.0 MM) QFN

(Sawn) 48-Pin (7X7X 1.0 MM) QFN

(Sawn)

[19]

CY8C29466-24PVXIT 32K 2K Yes -40C to +85C 16 12 24 12 4 Ye s

CY8C29466-24SXIT 32K 2K Yes -40C to +85C 16 12 24 12 4 Ye s

CY8C29566-24AXIT 32K 2K Yes -40C to +85C 16 12 40 12 4 Ye s

CY8C29666-24PVXIT 32K 2K Yes -40C to +85C 16 12 44 12 4 Ye s

CY8C29000-24AXI 32K 2K Yes -40C to +85C 16 12 64 12 4 Ye s

CY8C29666-24LTXI 32K 2K Yes -40C to +85C 16 12 44 12 4 Ye s

CY8C29666-24LTXIT 32K 2K Yes -40C to +85C 16 12 44 12 4 Ye s

Ordering

Code

Flash

RAM

(Bytes)

Pump

Switch Mode

Range

Temperature

Blocks

Digital PSoC

Blocks

Analog PSoC

Digital I/O

Pins

Analog

Inputs

Analog

Outputs

Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).

17. Ordering Code Definitions

XRES Pin

Document Number: 38-12013 Rev. *M Page 45 of 47

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18. Document History Page

Document Title: CY8C29466, CY8C29566, CY8C29666, and CY8C29866 PSoC®Programmable System-on-Chip

Document Number: 38-12013

Revision ECN No.

Submission

Date

** 131151 11/13/2003 New Silicon New document (Revision **).

*A 132848 01/21/2004 NWJ New information. First edition of preliminary data sheet.

*B 133205 01/27/2004 NWJ Changed part numbers, increased SRAM data storage to 2K bytes.

*C 133656 02/09/2004 SFV Changed part numbers and removed a 28-pin SOIC.

*D 227240 06/01/2004 SFV Changes to Overview section, 48-pin MLF pinout, and significant changes

*E 240108 See ECN SFV Added a 28-lead (300 mil) SOIC part.

*F 247492 See ECN SFV New information added to the Electrical Specifications chapter.

*G 288849 See ECN HMT Add DS standards, update device table, fine-tune pinouts, add Reflow Peak

*H 722736 See ECN HMT Add QFN package clarifications. Add new QFN diagram. Add Low Power

*I 2503350 See ECN DFK/PYRS Pinout for CY8C29000 OCD wrongly included details of CY8C24X94. The

*J 2545030 07/29/08 YAR A Added note to Ordering Information

*K 2708295 04/22/2009 JVY Changed title from “CY8C29466, CY8C29566, CY8C29666, and

*L 2761941 09/10/2009 DRSW/AESA

*M 2842762 01/08/2010 DRSW

Origin of

Change

Description of Change

to the Electrical Specs.

Temp. table. Finalize.

Comparator (LPC) AC/DC electrical spec. tables. Add CY8C20x34 to PSoC Device Characteristics table. Update emulation pod/feet kit part numbers. Add OCD non-production pinouts and package diagrams. Add ISSP note to pinout tables. Update package diagram revisions. Update typical and recommended Storage Temperature per industrial specs. Update CY branding and QFN convention. Add new Dev. Tool section. Update copyright and trademarks.

correct pinout for CY8C29000 is included in this version. Added note on digital signaling in “DC Analog Reference Specifications” section.

CY8C29866 PSoC Mixed Signal Array Final Data Sheet” to “CY8C29466, CY8C29566, CY8C29666, and CY8C29866 PSoC® Programmable System-on-Chip™” Updated to data sheet template Added 48-Pin QFN (Sawn) package diagram and CY8C29666-24LTXI and CY8C29666-24LTXIT part details in the Ordering Information table Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as follows: Modified F Added I T

POWERUP

PROGRAM_COLD

Added SR

IMO6

(page 21), I

(page 28), T

POWER_UP

(page 27), T

(page 21), DC

ERASEALL

(page 34) specifications

specifications (page 34)

WRITE

(page 34), T

parameter in AC specs table..

(page 28), F

ILO

PROGRAM_HOT

(page 27),

32K_U

(page 34), and

Corrected Notes for Vdd parameter in Table 12-4, “DC Chip-Level Specifi-

cations,” on page 22.

Added “Contents” on page 2.

Document Number: 38-12013 Rev. *M Page 46 of 47

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19. Sales, Solutions, and Legal Information

19.1 Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

19.2 Products

Automotive cypress.com/go/automotive

Clocks & Buffers cypress.com/go/clocks

Interface cypress.com/go/interface

Lighting & Power Control cypress.com/go/powerpsoc

cypress.com/go/plc

Memory cypress.com/go/memory

Optical & Image Sensing cypress.com/go/image

PSoC cypress.com/go/psoc

Touch Sensing cypress.com/go/touch

USB Controllers cypress.com/go/USB

Wireless/RF cypress.com/go/wireless

19.3 PSoC Solutions

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PSoC 1 | PSoC 3 | PSoC 5

© Cypress Semiconductor Corporation, 2003-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress prod ucts are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Sou rce Code and derivative works for the sole purpose of cr eating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described h erein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-12013 Rev. *M Revised January 11, 2010 Page 47 of 47

PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.

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Cypress Semiconductor CY8C29466, CY8C29566, CY8C29666, CY8C29866 User manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Features

2. Logic Block Diagram

3. Contents

4. PSoC Functional Overview

4.2 Digital System

4.1 PSoC Core

4.3 Analog System

4.4 Additional System Resources

4.5 PSoC Device Characteristics

5. Getting Started

5.1 Application Notes

5.2 Development Kits

5.3 Training

5.4 CYPros Consultants

5.5 Solutions Library

5.6 Technical Support

6. Development Tools

6.1 PSoC Designer Software Subsystems

6.1.1 System-Level View

6.1.2 Chip-Level View

6.1.3 Hybrid Designs

6.1.4 Code Generation Tools

6.1.5 Debugger

6.1.6 Online Help System

6.2 In-Circuit Emulator

7. Designing with PSoC Designer

7.1 Select Components

7.2 Configure Components

7.3 Organize and Connect

7.4 Generate, Verify, and Debug

8. Document Conventions

8.1 Acronyms Used

8.2 Units of Measure

8.3 Numeric Naming

9. Pinouts

9.1 28-Pin Part Pinout

9.2 44-Pin Part Pinout

9.3 48-Pin Part Pinouts

9.4 100-Pin Part Pinout

9.5 100-Pin Part Pinout (On-Chip Debug)

10. Register Conventions

10.1 Abbreviations Used

11. Register Mapping Tables

12. Electrical Specifications

12.1 Absolute Maximum Ratings

12.2 Operating Temperature

12.3 DC Electrical Characteristics

12.3.1 DC Chip-Level Specifications

12.3.2 DC General Purpose I/O Specifications

12.3.3 DC Operational Amplifier Specifications

12.3.4 DC Low Power Comparator Specifications

12.3.5 DC Analog Output Buffer Specifications

12.3.6 DC Switch Mode Pump Specifications

12.3.7 DC Analog Reference Specifications

12.3.8 DC Analog PSoC Block Specifications

12.3.9 DC POR, SMP, and LVD Specifications

12.3.10 DC Programming Specifications

12.4 AC Electrical Characteristics

12.4.1 AC Chip-Level Specifications

12.4.2 AC General Purpose I/O Specifications

12.4.3 AC Operational Amplifier Specifications

12.4.4 AC Low Power Comparator Specifications

12.4.5 AC Digital Block Specifications

12.4.6 AC Analog Output Buffer Specifications

12.4.7 AC External Clock Specifications

12.4.8 AC Programming Specifications

12.4.9 AC I2C Specifications

13. Packaging Information

13.1 Packaging Dimensions

13.1 Thermal Impedances 13.2 Capacitance on Crystal Pins

13.3 Solder Reflow Peak Temperature

14. Development Tool Selection

14.1 Software

14.1.2 PSoC Programmer

14.2 Development Kits

14.2.1 CY3215-DK Basic Development Kit