Cypress Semiconductor CY8C27143, CY8C27243, CY8C27443, CY8C27543, CY8C27643 User guide
PSoCĀ® Programmable System-on-Chip
CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
Features
DIGITAL SYSTEM
SRAM
256 Bytes
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Inc ludes I MO, I LO, PLL, and E CO)
Global Digital Interconnect
Global Analog Interconnect
PSoC
CORE
CPU Core (M8C)
SROM Flash 16K
Digital
Block
Array
Multiply
Accum.
Switch
Mod e
Pump
Internal
Voltage
Ref.
Digital
Clocks
POR and LVD
System Resets
Decimator
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref.
Analog
Input
Muxing
I C
2
Por t 4 Por t 3 Por t 2 Por t 1 Port 0
Analog
Drivers
System Bus
Analog
Block
Array
Por t 5
Logic Block Diagram
ā
Powerful Harvard Architecture Processor
ā
M8C processor speeds to 24 MHz
ā
8x8 multiply, 32-bit accumulate
ā
Low power at high speed
ā
3.0 to 5.25V operating voltage
ā
Operating voltages down to 1.0V using on-chip switch mode
pump (SMP)
ā
Industrial temperature range: -40Ā°C to +85Ā°C
ā
Advanced Peripherals (PSoCĀ® Blocks)
ā
12 rail-to-rail analog PSoC blocks provide:
ā¢ Up to 14-Bit ADCs
ā¢ Up to 9-Bit DACs
ā¢ Programmable Gain Amplifiers
ā¢ Programmable filters and comparators
ā
Eight digital PSoC blocks provide:
ā¢ 8- to 32-bit timers, counters, and PWMs
ā¢ CRC and PRS modules
ā¢ Up to two full-duplex UARTs
ā¢ Multiple SPIā¢ Masters or Slaves
ā¢ Connectable to all GPIO pins
ā
Complex peripherals by combining blocks
ā
Precision, Programmable Clocking
ā
Internal 2.5% 24/48 MHz oscillator
ā
24/48 MHz with optional 32 kHz crystal
ā
Optional external oscillator, up to 24 MHz
ā
Internal oscillator for watchdog and sleep
ā
Flexible On-Chip Memory
ā
16K Flash program storage 50,000 erase/write cycles
ā
256 bytes SRAM data storage
ā
In-System Serial Programming (ISSP)
ā
Partial Flash updates
ā
Flexible protection modes
ā
EEPROM emulation in Flash
ā
Programmable Pin Configuratio n s
ā
25 mA Sink, 10 mA Source on all GPIO
ā
Pull up, pull down, high Z, strong, or open drain drive modes
on all GPIO
ā
Eight standard analog inputs on GPIO, plus four additional
analog inputs with restricted routing
ā
Four 30 mA analog outputs on GPIO
ā
Configurable interrupt on all GPIO
ā
Additional System Resources
ā
I2C slave, master, and multi-master to 400 kHz
ā
Watchdog and sleep timers
ā
User-configurable low voltage detection
ā
Integrated supervisory circuit
ā
On-chip precision voltage reference
ā
Complete Development T ools
ā
Free development software (PSoC Designerā¢)
ā
Full featured, In-Circuit Emulator and Programmer
ā
Full speed emulation
ā
Complex breakpoint structure
ā
128K trace memory
Cypress Semiconductor Corporation ā¢ 198 Champion Court ā¢ San Jose,CA 95134-1709 ā¢ 408-943-2600
Document Number: 38-12012 Rev. *O Revised November 20, 2009
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Contents
Features ............................................................................... 1
Logic Block Diagram ....................................... ...................1
Contents .............................................................................. 2
PSoC Functional Overview ................................................3
PSoC Core ....................................................................3
Digital System ...............................................................3
Analog System ................................................... ... ........4
Additional System Resources .......................................5
PSoC Device Characteristics ........................................5
Getting Started ....................................................................5
Application Notes ..........................................................5
Development Kits .................................................. ........5
Training .........................................................................5
CYPros Consultants ......................................................5
Solutions Library ............................................................5
Technical Support .........................................................5
Development Tools ............................................................6
PSoC Designer Software Subsystems ..........................6
In-Circuit Emulator .........................................................6
Designing with PSoC Designer .........................................7
Select Components .......................................................7
Configure Components .................................................7
Organize and Connect ..................................................7
Generate, Verify, and Debug .........................................7
Document Conventions ................................................... ..8
Acronyms Used .............................................................8
Units of Measure ...........................................................8
Numeric Naming .............................................. ... ...........8
Pinouts ................................................................................9
8-Pin Part Pinout ..........................................................9
20-Pin Part Pinout ........................................................9
28-Pin Part Pinout ......................................................10
44-Pin Part Pinout ......................................................11
48-Pin Part Pinout .......................................................12
56-Pin Part Pinout .......................................................14
Register Reference .................................................... .. .....16
Register Conventions ..................................................16
Register Mapping Tables ............................................16
Electrical Specifications ..................................... ... ..........19
Absolute Maximum Ratings .........................................20
Operating Temperature ..............................................20
DC Electrical Characteristics .......................................21
AC Electrical Characteristics .......................................32
Packaging Information .....................................................41
Packaging Dimensions ................................................41
Thermal Impedances ........................................ ..........46
Capacitance on Crystal Pins ......................................46
Solder Reflow Peak Temperature ...............................47
Development Tool Selection ...........................................48
Software ......................................................................48
Development Kits ........................................................48
Evaluation Tools ..........................................................48
Device Programmers ...................................................49
Accessories (Emulation and Programming) ..................49
Third-Party Tools .........................................................49
Build a PSoC Emulator into Your Board ......................49
Ordering Information ........................................................50
Ordering Code Definitions ..........................................51
Document History Page ..................................................52
Sales, Solutions, and Legal Information ........................53
Worldwide Sales and Design Support .........................53
Products ......................................................................53
Document Number: 38-12012 Rev. *O Page 2 of 53
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PSoC Functional Overview
DIGITAL SYSTEM
To System Bus
D
i
g
i
t
a
l
C
l
o
c
k
s
F
r
o
m
C
o
r
e
Digita l PS oC Block A rray
To Analog
System
8
Row Input
Configuration
Row Output
Configuration
88
8
Row 1
DBB10 DBB11 DCB12 DCB13
Row Input
Configuration
4
4
Row Output
Configuration
Row 0
DBB00 DBB01 DCB02 DCB03
4
4
GI E[7:0]
GIO[7:0]
GOE[7:0]
GOO [7:0]
Global Digital
Interconnect
Por t 4
Por t 3
Por t 2
Por t 1
Por t 0
Port 5
The PSoC family consists of many Programmable
System-on-Chip Controller devices. These devices are designed
to replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
Digital System
The Digital System is composed of 8 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.
Figure 1. Digital System Block Diagram
as well as programmable interconnects. This architecture allows
the user to create customized peripheral configurations that
match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable I/O are included in a range of conveĀnient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: PSoC Core, Digital System, Analog System,
and System Resources. Configurable global busing allows all
the device resources to be combined into a complete custom
system. The PSoC CY8C27x43 family can have up to five I/O
ports that connect to the global digital and analog interconnects,
providing access to 8 digital blocks and 12 analog blocks.
PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory , clocks, and configurable
GPIO (General Purpose I/O).
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture microproĀcessor. The CPU utilizes an interrupt controller with 17 vectors,
to simplify programming of real time embedded events. Program
execution is timed and protected using the included Sle ep and
Watch Dog Timers (WDT).
Memory encompasses 16K of Flash for program storage, 256
bytes of SRAM for data storage, and up to 2K of EEPROM
emulated using the Flash. Program Flash utilizes four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates fl exible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to
2.5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pinās drive mode may be selected
from eight options, allowing great flexibility in external interĀfacing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.
Document Number: 38-12012 Rev. *O Page 3 of 53
Digital peripheral configurations include those listed below.
ā
PWMs (8 to 32 bit)
ā
PWMs with Dead band (8 to 32 bit)
ā
Counters (8 to 32 bit)
ā
Timers (8 to 32 bit)
ā
UART 8 bit with selectab l e parity (up to 2)
ā
SPI slave and master (up to 2)
ā
I2C slave and multi-master (1 available as a System Resource)
ā
Cyclical Redundancy Checker/Generator (8 to 32 bit)
ā
IrDA (up to 2)
ā
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled āPSoC Device Character-
isticsā on page 5.
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Analog System
ACB00 ACB01
Bloc k Arr a y
Arra y Input Configura tion
ACI1[1:0] ACI2[1:0]
ACB02 ACB03
ASC12 ASD13
ASD22 ASC23ASD20
ACI0[1:0] ACI3[1:0]
P0[ 6]
P0[ 4]
P0[ 2]
P0[ 0]
P2[ 2]
P2[ 0]
P2[ 6]
P2[ 4]
RefIn
AGNDIn
P0[ 7]
P0[ 5]
P0[ 3]
P0[ 1]
P2[ 3]
P2[ 1]
Refere n ce
Gene rators
AGNDIn
Ref In
Bandgap
Ref Hi
Ref Lo
AGND
ASD11
ASC21
ASC10
Interface to
Digital System
M8C Interface (Address Bus, Data Bus, Etc.)
Anal og Refe ren ce
The Analog System is composed of 12 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are listed below.
ā
Analog-to-digital converters (up to 4, with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
ā
Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch)
ā
Amplifiers (up to 4, with selectable gain to 48x)
ā
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
ā
Comparators (up to 4, with 16 selectable thresholds)
ā
DACs (up to 4, with 6- to 9-bit resolution)
ā
Multiplying DACs (up to 4, with 6- to 9-bit resolution)
ā
High current output drivers (four with 30 mA drive as a Core
Resource)
ā
1.3V reference (as a System Resource)
ā
DTMF Dialer
ā
Modulators
ā
Correlators
ā
Peak detectors
ā
Many other topologies possible
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.
Figure 2. Analog System Block Diagram
Document Number: 38-12012 Rev. *O Page 4 of 53
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Additional System Resources
Notes
1. Limited analog functionality
.
2. Two analog blocks and one CapSense.
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Statements
describing the merits of each system resource are below.
ā
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
ā
Multiply accumulate (MAC) provides fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
ā
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
ā
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
ā
Low Voltage Detection (LVD) interrupts can signal the appliĀcation of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
ā
An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
ā
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources available
for specific PSoC device groups.The PSoC device covered by
this data sheet is highlighted below.
Table 1. PSoC Device Characteristics
PSoC Part
Number
CY8C29x66
CY8C27x43
CY8C24x94 49 1 4 48 2 2 6 1K 16K
CY8C24x23
CY8C24x23A
CY8C21x34
CY8C21x23
CY8C20x34
I/O
Digital
up to
64
up to
44
up to
24
up to
24
up to
28
16 1 4 8 0 2
up to
28
Rows
Digital
4 16 12 4 4 12 2K 32K
2 8 12 4 4 12
1 4 12 2 2 6
1412226
142802
0 0 28 0 0
Inputs
Digital
Blocks
Analog
Analog
Analog
Outputs
Columns
Blocks
Analog
[1]
4
[2]
4
[2]
3
SRAM
256
Bytes
256
Bytes
256
Bytes
512
Bytes
256
Bytes
512
Bytes
Size
Flash
16K
4K
4K
8K
4K
8K
Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming inforĀmation, see the PSoC
Technical Reference Manual for CY8C28xxx PSoC devices.
For up to date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various
Size
application designs that include firmware and hardwa re design
files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Ā®
Programmable System-on-Chipā¢
Document Number: 38-12012 Rev. *O Page 5 of 53
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Development Tools
PSoC Designer is a MicrosoftĀ® Windows-based, integrated
development environment for the Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built in support for third party
assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication
interfaces. You define when and how an output device changes
state based upon any or all other system devices. Based upon
the design, PSoC Designer automatically selects one or more
PSoC Programmable System-on-Chip Controllers that match
your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional IDE. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder , and common debug, emulation, and programming
tools.
Code Generation Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear b reakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Document Number: 38-12012 Rev. *O Page 6 of 53
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called ādriversā and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
2
(I
C-bus, for example), and the logic to control how they interact
with one another (called valuators).
In the chip-level view, the components are called āuser modulesā.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and progra mma ble
system-on-chip varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly o r
by selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Organize and Connect
You can build signal chains at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometerās output to
a digital signal, and a PWM to control the fan.
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the āGenerate
Applicationā step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designerās Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you define complex breakpoint events that
include monitoring address and data bus values, memory
locations and external signals.
Document Number: 38-12012 Rev. *O Page 7 of 53
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Document Conventions
Acronyms Used
This table lists the acronyms used in this data sheet.
Table 2. Acronyms
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
EEPROM electrically erasable programmable read-only
FSR full scale range
GPIO general purpose I/O
ICE in-circuit emulator
IDE integrated development environment
I/O input/output
ISSP in-system serial programming
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PGA programmable gain amplifier
POR power on reset
PPOR precision power on reset
Ā®
PSoC
PWM pulse width modulator
ROM read only memory
SC switched capacitor
SMP switch mode pump
SRAM static random access memory
memory
Programmable System-on-Chipā¢
Units of Measure
A units of measure table is located in the section
Electrical S pecificat ions on page 19. Table 13 on page 19 lists all
the abbreviations used to measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase āhā (for example, ā14hā or
ā3Ahā). Hexadecimal numbers may also be represented by a ā0xā
prefix, the C coding convention. Binary numbers have an
appended lowercase ābā (for example, 01010100bā or
ā01000011bā). Numbers not indicated by an āhā, ābā, or 0x are
decimal.
Document Number: 38-12012 Rev. *O Page 8 of 53
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Pinouts
PDIP
1
2
3
4
A, IO, P 0[5]
A, IO, P 0[3]
I2C S CL, XTALin, P1[1]
Vss
8
7
6
5
Vdd
P0[4], A, IO
P0[2], A, IO
P1[0], XTALout, I2C SDA
SSOP
SOIC
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P 0[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
The CY8C27x43 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a āPā) is capable of Digital I/O. However, Vss, Vdd, SMP, and XRES are not capable of Digital I/O.
8-Pin Part Pinout
Table 3. Pin Definitions - 8-Pin PDIP
Pin
No.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference
Manual for details.
20-Pin Part Pinout
Table 4. Pin Definitions - 20-Pin SSOP, SOIC
Pin
No.
10 Power Vss Ground connection.
12 I/O P1[2]
13 I/O P1[4] Optional External Clock Input (EXTCLK).
14 I/O P1[6]
15 Input XRES Active high external reset with internal pull down.
16 I/O I P0[0] Analog column mux input.
17 I/O I/O P0[2] Analog column mux input and column output.
18 I/O I/O P0[4] Analog column mux input and column output.
19 I/O I P0[6] Analog column mux input.
20 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. *O Page 9 of 53
Type
Digital Analog
Pin
Name
Description
1 I/O I/O P0[5] Analog column mux input and column output.
2 I/O I/O P0[3] Analog column mux input and column output.
3 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
4 Power Vss Ground connection.
5 I/O P1[0] Crystal Output (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
6 I/O I/O P0[2] Analog column mux input and column output.
7 I/O I/O P0[4] Analog column mux input and column output.
8 Power Vdd Supply voltage.
Type
Digital Analog
Pin
Name
Description
1 I/O I P0[7] Analog column mux input.
2 I/O I/O P0[5] Analog column mux input and column output.
3 I/O I/O P0[3] Analog column mux input and column output.
4 I/O I P0[1] Analog column mux input.
5 Power SMP Switch Mode Pump (SMP) connection to external
components required.
6 I/O P1[7] I2C Serial Clock (SCL).
7 I/O P1[5] I2C Serial Data (SDA).
8 I/O P1[3]
9 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
11 I/O P1[0] Crystal Output (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
Figure 3. CY8C27143 8-Pin PSoC Device
Figure 4. CY8C27243 20-Pin PSoC Device
[+] Feedback
CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
28-Pin Part Pinout
A, I, P0[7]
A, IO, P 0[5]
A, IO, P 0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VRef
P2[4], External AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
PDIP
SSOP
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TQFP
P3[1]
P2[7]
P2[5] P2[4], External AGND
A, I, P2[3] P2[2], A, I
A, I, P2[1] P2[0], A, I
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
P4[1]
P4[0]
SMP XRES
P3[7]
P3[6]
P3[5] P3[4]
P3[3] P3[2]
I2C SC L, P1[7]
P0[1], A, I
I2C SDA, P1[5]
P0[3], A, IO
P1[3]
P0[5], A, IO
I2C SCL, XTALin, P1[1]
P0[7], A, I
Vss
Vdd
I2C SDA, XTALout, P1[0 ]
P0[6], A, I
P1[2]
P0[4], A, IO
EXTCLK, P1[4]
P0[2], A, IO
P1[6]
P0[0], A, I
P3[0]
P2[6], External VRef
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
4443424140393837363534
13
14
15
16
17
18
192021
22
12
Table 5. Pin Definitions - 28-Pin PDIP, SSOP, SOIC
Pin No.
Type
Digital Analog
1 I/O I P0[7] Analog column mux input.
2 I/O I/O P0[5] Analog column mux input and column output.
3 I/O I/O P0[3] Analog column mux input and column output.
4 I/O I P0[1] Analog column mux input.
5 I/O P2[7]
6 I/O P2[5]
7 I/O I P2[3] Direct switched capacitor block input.
8 I/O I P2[1] Direct switched capacitor block input.
9 Power SMP Switch Mode Pump (SMP) connection to external
10 I/O P1[7] I2C Serial Clock (SCL).
11 I/O P1[5] I2C Serial Data (SDA).
12 I/O P1[3]
13 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL),
14 Power Vss Ground connection.
15 I/O P1[0] Crystal Output (XT ALout), I2C Serial Data (SDA),
16 I/O P1[2]
17 I/O P1[4] Optional External Clock Input (EXTCLK).
18 I/O P1[6]
19 Input XRES Active high external reset with internal pull down.
20 I/O I P2[0] Direct switched capacitor block input.
21 I/O I P2[2] Direct switched capacitor block input.
22 I/O P2[4] External Analog Ground (AGND).
23 I/O P2[6] External Voltage Reference (VRef).
24 I/O I P0[0] Analog column mux input.
25 I/O I/O P0[2] Analog column mux input and column output.
26 I/O I/O P0[4] Analog column mux input and column output.
27 I/O I P0[6] Analog column mux input.
28 Power Vdd Supply voltage.
Pin
Name
Description
components required.
ISSP-SCLK*.
ISSP-SDATA*.
Figure 5. CY8C27443 28-Pin PSoC Device
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSo C ProgrammaĀble System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. *O Page 10 of 53
[+] Feedback
CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
44-Pin Part Pinout
Table 6. Pin Definitions - 44-Pin TQFP
Pin
No.
1 I/O P2[5]
2 I/O I P2[3] Direct switched capacitor block input.
3 I/O I P2[1] Direct switched capacitor block input.
4 I/O P4[7]
5 I/O P4[5]
6 I/O P4[3]
7 I/O P4[1]
8 Power SMP Switch Mode Pump (SMP) connection to external
9 I/O P3[7]
10 I/O P3[5]
11 I/O P3[3]
12 I/O P3[1]
13 I/O P1[7] I2C Serial Clock (SCL).
14 I/O P1[5] I2C Serial Data (SDA).
15 I/O P1[3]
16 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL),
17 Power Vss Ground connection.
18 I/O P1[0] Crystal Output (XT ALout), I2C Serial Data (SDA),
19 I/O P1[2]
20 I/O P1[4] Optional External Clock Input (EXTCLK).
21 I/O P1[6]
22 I/O P3[0]
23 I/O P3[2]
24 I/O P3[4]
25 I/O P3[6]
26 Input XRES Active high external reset with internal pull down.
27 I/O P4[0]
28 I/O P4[2]
29 I/O P4[4]
30 I/O P4[6]
31 I/O I P2[0] Direct switched capacitor block input.
32 I/O I P2[2] Direct switched capacitor block input.
33 I/O P2[4] External Analog Ground (AGND).
34 I/O P2[6] External Voltage Reference (VRef).
35 I/O I P0[0] Analog column mux input.
36 I/O I/O P0[2] Analog column mux input and column output.
37 I/O I/O P0[4] Analog column mux input and column output.
38 I/O I P0[6] Analog column mux input.
39 Power Vdd Supply voltage.
40 I/O I P0[7] Analog column mux input.
41 I/O I/O P0[5] Analog column mux input and column output.
42 I/O I/O P0[3] Analog column mux input and column output.
43 I/O I P0[1] Analog column mux input.
44 I/O P2[7]
Type
Digital Analog
Pin Name Description
components required.
ISSP-SCLK*.
ISSP-SDATA*.
Figure 6. CY8C27543 44-Pin PSoC Device
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 38-12012 Rev. *O Page 11 of 53
[+] Feedback
CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
48-Pin Part Pinout
SSOP
A, I, P0[7]
Vdd
A, IO, P0[5]
P0[6], A, I
A, IO, P0[3]
P0[4], A, IO
A, I, P0[1] P0[2], A, IO
P2[7]
P0[0], A, I
P2[5]
P2[6], External VRef
A, I, P2[3]
P2[4], External AGND
A, I, P2[1]
P2[2], A, I
P4[7]
P2[0], A, I
P4[5]
P4[6]
P4[3]
P4[4]
P4[1]
P4[2]
SMP
P4[0]
P3[7]
XRES
P3[5]
P3[6]
P3[3]
P3[4]
P3[1]
P3[2]
P5[3]
P3[0]
P5[1]
P5[2]
I2C SCL, P1[7]
P5[0]
I2C SDA, P1[5]
P1[6]
P1[3]
P1[4], EXT CLK
I2C SCL, XTALin, P1[1] P1[2]
Vss P1[0], XTALout, I2C SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
43
44
42
40
41
39
38
37
36
35
33
34
32
31
30
29
28
27
26
25
Table 7. 48-Pin Part Pinout (SSOP)
Pin
No.
1 I/O I P0[7] Analog column mux input.
2 I/O I/O P0[5] Analog column mux input and column output.
3 I/O I/O P0[3] Analog column mux input and column output.
4 I/O I P0[1] Analog column mux input.
5 I/O P2[7]
6 I/O P2[5]
7 I/O I P2[3] Direct switched capacitor block input.
8 I/O I P2[1] Direct switched capacitor block input.
9 I/O P4[7]
10 I/O P4[5]
11 I/O P4[3]
12 I/O P4[1]
13 Power SMP Switch Mode Pump (SMP) connection to
14 I/O P3[7]
15 I/O P3[5]
16 I/O P3[3]
17 I/O P3[1]
18 I/O P5[3]
19 I/O P5[1]
20 I/O P1[7] I2C Serial Clock (SCL).
21 I/O P1[5] I2C Serial Data (SDA).
22 I/O P1[3]
23 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock
24 Power Vss Ground connection.
25 I/O P1[0] Crystal Output (XTALout), I2C Serial Data
26 I/O P1[2]
27 I/O P1[4] Optional External Clock Input (EXTCLK).
28 I/O P1[6]
29 I/O P5[0]
30 I/O P5[2]
31 I/O P3[0]
32 I/O P3[2]
33 I/O P3[4]
34 I/O P3[6]
35 Input XRES Active high external reset with internal pull
36 I/O P4[0]
37 I/O P4[2]
38 I/O P4[4]
39 I/O P4[6]
40 I/O I P2[0] Direct switched capacitor block input.
41 I/O I P2[2] Direct switched capacitor block input.
42 I/O P2[4] External Analog Ground (AGND).
43 I/O P2[6] External Voltage Reference (VRef).
44 I/O I P0[0] Analog column mux input.
45 I/O I/O P0[2] Analog column mux input and column output.
46 I/O I/O P0[4] Analog column mux input and column output.
47 I/O I P0[6] Analog column mux input.
48 Power Vdd Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Document Number: 38-12012 Rev. *O Page 12 of 53
Type
Digital Analog
Pin
Name
external components required.
(SCL), ISSP-SCLK*.
(SDA), ISSP-SDATA.*
down.
Description
Figure 7. CY8C27643 48-Pin PSoC Device
[+] Feedback
CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
QFN
(Top View)
P2[5]
P2[7]
P0[1], A, I
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VRef
10
11
12
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
35
34
33
32
31
30
29
28
27
26
25
36
4847464544
43424140393837
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P2[4], External AGND
1
2
3
4
5
6
7
8
9
1314151617181920212223
24
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
P5[0]
P5[2]
Table 8. 48-Pin Part Pinout (QFN)*
Pin
No.
1 I/O I P2[3] Direct switched capacitor block input.
2 I/O I P2[1] Direct switched capacitor block input.
3 I/O P4[7]
4 I/O P4[5]
5 I/O P4[3]
6 I/O P4[1]
7 Power SMP Switch Mode Pump (SMP) connection to
8 I/O P3[7]
9 I/O P3[5]
10 I/O P3[3]
11 I/O P3[1]
12 I/O P5[3]
13 I/O P5[1]
14 I/O P1[7] I2C Serial Clock (SCL).
15 I/O P1[5] I2C Serial Data (SDA).
16 I/O P1[3]
17 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL),
18 Power Vss Ground connection.
19 I/O P1[0] Crystal Output (XTALout), I2C Serial Data
20 I/O P1[2]
21 I/O P1[4] Optional External Clock Input (EXTCLK).
22 I/O P1[6]
23 I/O P5[0]
24 I/O P5[2]
25 I/O P3[0]
26 I/O P3[2]
27 I/O P3[4]
28 I/O P3[6]
29 Input XRES Active high external reset with internal pull
30 I/O P4[0]
31 I/O P4[2]
32 I/O P4[4]
33 I/O P4[6]
34 I/O I P2[0] Direct switched capacitor block input.
35 I/O I P2[2] Direct switched capacitor block input.
36 I/O P2[4] External Analog Ground (AGND).
37 I/O P2[6] External Voltage Reference (VRef).
38 I/O I P0[0] Analog column mux input.
39 I/O I/O P0[2] Analog column mux input and column output.
40 I/O I/O P0[4] Analog column mux input and column output.
41 I/O I P0[6] Analog column mux input.
42 Power Vdd Supply voltage.
43 I/O I P0[7] Analog column mux input.
44 I/O I/O P0[5] Analog column mux input and column output.
45 I/O I/O P0[3] Analog column mux input and column output.
46 I/O I P0[1] Analog column mux input.
47 I/O P2[7]
48 I/O P2[5]
LEGEND: A = Analog, I = Input, and O = Output.
* The QFN package has a center pad that must be connected to ground (Vss).
** These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
Type
Digital Analog
Pin
Name
Description
external components required.
ISSP-SCLK**.
(SDA), ISSP-SDATA**.
down.
Figure 8. CY8C27643 48-Pin PSoC Device
Document Number: 38-12012 Rev. *O Page 13 of 53
[+] Feedback
CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
56-Pin Part Pinout
SSOP
1
56
255
354
453
5
52
6
51
750
849
948
10
47
11 46
12 45
13
44
14 43
15
42
16
41
17
40
18 39
19 38
20
37
21 36
22
35
23 34
24 33
25 32
26 31
27
30
28
29
Vdd
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
P2[6], Externa l V R e f
P2[4], Externa l A GND
P2[2], AI
P2[0], AI
P4[6]
P4[4]
P4[2]
P4[0]
CCLK
HCLK
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P5[2]
P5[0]
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALOut, I2C SDA, SDATA
NC
NC
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
OCDE
OCDO
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
NC
P1[3]
SCLK, I2C SCL, XTALIn, P1[1]
Vss
NC
The 56-pin SSOP part is for the CY8C27002 On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 9. 56-Pin Part Pinout (SSOP)
Pin
No.
Type
Digital Analog
Pin
Name
Description
1 NC No connection.
2 I/O I P0[7] Analog column mux input.
3 I/O I P0[5] Analog column mux input and column
output.
4 I/O I P0[3] Analog column mux input and column
output.
5 I/O I P0[1] Analog column mux input.
6 I/O P2[7]
7 I/O P2[5]
8 I/O I P2[3] Direct switched capacitor block input.
9 I/O I P2[1] Direct switched capacitor block input.
10 I/O P4[7]
11 I/O P4[5]
12 I/O IP4[3]
13 I/O IP4[1]
14 OCD OCDE OCD even data I/O.
15 OCD OCDO OCD odd data output.
16 Power SMP Switch Mode Pump (SMP) connection to
required external components.
17 I/O P3[7]
18 I/O P3[5]
19 I/O P3[3]
20 I/O P3[1]
21 I/O P5[3]
22 I/O P5[1]
23 I/O P1[7] I2C Serial Clock (SCL).
24 I/O P1[5] I2C Serial Data (SDA).
25 NC No connection.
26 I/O P1[3]
27 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*.
28 Power Vdd Supply voltage.
29 NC No connection.
30 NC No connection..
31 I/O P1[0] Crystal Output (XTALout), I2C Serial
32 I/O P1[2]
33 I/O P1[4] Optional External Clock Input (EXTCLK).
34 I/O P1[6]
35 I/O P5[0]
36 I/O P5[2]
37 I/O P3[0]
38 I/O P3[2]
39 I/O P3[4]
40 I/O P3[6]
41 Input XRES Active high external reset with internal
Document Number: 38-12012 Rev. *O Page 14 of 53
Data (SDA), ISSP-SDATA*.
pull down.
Figure 9. CY8C27002 56-Pin PSoC Device
Not for Production
[+] Feedback
CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
Table 9. 56-Pin Part Pinout (SSOP)
42 OCD HCLK OCD high-speed clock output.
43 OCD CCLK OCD CPU clock output.
44 I/O P4[0]
45 I/O P4[2]
46 I/O P4[4]
47 I/O P4[6]
48 I/O I P2[0] Direct switched capacitor block input.
49 I/O I P2[2] Direct switched capacitor block input.
50 I/O P2[4] External Analog Ground (AGND).
51 I/O P2[6] External Voltage Reference (VRef).
52 I/O I P0[0] Analog column mux input.
53 I/O I P0[2] Analog column mux input and column
54 I/O I P0[4] Analog column mux input and column
55 I/O I P0[6] Analog column mux input.
56 Power Vdd Supply voltage.
output.
output.
LEGEND
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
Document Number: 38-12012 Rev. *O Page 15 of 53
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CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
Register Reference
This chapter lists the registers of the CY8C27x43 PSoC device.
For detailed register information, reference the
PSoC Programmable System-on-Chip Technical Reference
Manual.
Register Conventions
The register conventions specific to this section are listed in the
Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are
reserved and must not be accessed.
following table.
Table 10. Register Conventions
Convention Description
R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific
Table 11. Register Map Bank 0 Table: User Space
Name
PRT0DR 00 RW 40 ASC10CR0 80 RW C0
PRT0IE 01 RW 41 ASC10CR1 81 RW C1
PRT0GS 02 RW 42 ASC10CR2 82 RW C2
PRT0DM2 03 RW 43 ASC10CR3 83 RW C3
PRT1DR 04 RW 44 ASD11CR0 84 RW C4
PRT1IE 05 RW 45 ASD11CR1 85 RW C5
PRT1GS 06 RW 46 ASD11CR2 86 RW C6
PRT1DM2 07 RW 47 ASD11CR3 87 RW C7
PRT2DR 08 RW 48 ASC12CR0 88 RW C8
PRT2IE 09 RW 49 ASC12CR1 89 RW C9
PRT2GS 0A RW 4A ASC12CR2 8A RW CA
PRT2DM2 0B RW 4B ASC12CR3 8B RW CB
PRT3DR 0C RW 4C ASD13CR0 8C RW CC
PRT3IE 0D RW 4D ASD13CR1 8D RW CD
PRT3GS 0E RW 4E ASD13CR2 8E RW CE
PRT3DM2 0F RW 4F ASD13CR3 8F RW CF
PRT4DR 10 RW 50 ASD20CR0 90 RW D0
PRT4IE 11 RW 51 ASD20CR1 91 RW D1
PRT4GS 12 RW 52 ASD20CR2 92 RW D2
PRT4DM2 13 RW 53 ASD20CR3 93 RW D3
PRT5DR 14 RW 54 ASC21CR0 94 RW D4
PRT5IE 15 RW 55 ASC21CR1 95 RW D5
PRT5GS 16 RW 56 ASC21CR2 96 RW I2C_CFG D6 RW
PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C_SCR D7 #
DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW
DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW
DBB00DR2 22 RW 62 A2 INT_VC E2 RC
DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W
DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC
DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC
Blank fields are Reserved and must not be accessed. # Access is bit specific.
(0,Hex)
Addr
18 58 ASD22CR0 98 RW I2C_DR D8 RW
19 59 ASD22CR1 99 RW I2C_MSCR D9 #
1A 5A ASD22CR2 9A RW INT_CLR0 DA RW
1B 5B ASD22CR3 9B RW INT_CLR1 DB RW
1C 5C ASC23CR0 9C RW DC
1D 5D ASC23CR1 9D RW INT_CLR3 DD RW
1E 5E ASC23CR2 9E RW INT_MSK3 DE RW
1F 5F ASC23CR3 9F RW DF
Access
Name
(0,Hex)
Access
Addr
Name
(0,Hex)
Access
Addr
Name
(0,Hex)
Addr
Access
Document Number: 38-12012 Rev. *O Page 16 of 53
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