Cypress Semiconductor CY8C24223A, CY8C24423A User guide

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CY8C24223A, CY8C24423A

Automotive - Extended Temperature PSoC

Programmable System-on-Chip

Features

Logic Block Diagram

DIGITAL SYSTEM

SRAM

256 Bytes

Interrupt

Controller

Sleep and Watchdog

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

Global Digital Interconnect

Global Analog Interconnect

PSoC CORE

CPU Core (M8C)

SROM Flash 4K

Digital

Block Array

Multiply Accum.

Internal Voltage

Ref.

Digital Clocks

POR and LVD

System Resets

Decimator

SYSTEM RESOURCES

ANALOG SYSTEM

Analog

Ref

Analog

Input

Muxing

I2C

(1 Row,

4 Blocks)

System Bus

Analog

Block Array

(2 Columns,

6 Blocks)

Port 2 Port 1

Analog

Drivers

Port 0

Note

1. There are eight standard analog inputs on the GPIO. The other four analog inputs connect from the GPIO directly to specific switched-capacitor block inputs. See the PSoC Technical Reference Manual for more details

■ AEC Qualified

■ Powerful Harvard Architecture Processor ❐ M8C Processor Speeds up to 12 MHz

❐ 8x8 Multiply, 32-Bit Accumulate ❐ Low Power at High Speed ❐ 4.75V to 5.25V Operating Voltage ❐ Automotive Temperature Range: -40°C to +125°C

■ Advanced Peripherals (PSoC ❐ Six Rail-to-Rail Analog PSoC Blocks Provide:

• Up to 14-Bit ADCs

• Up to 9-Bit DACs

• Programmable Gain Amplifiers

• Programmable Filters and Comparators

❐ Four Digital PSoC Blocks Provide:

• 8- to 32-Bit Timers, Counters, and PWMs

• CRC and PRS Modules

• Full- or Half-Duplex UART

• SPI Master or Slave

• Connectable to all GPIO Pins

❐ Complex Peripherals by Combining Blocks

■ Precision, Programmable Clocking ❐ Internal ±4% 24 MHz Oscillator

❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL ❐ Optional External Oscillator, up to 24 MHz ❐ Internal Low Speed, Low Power Oscillator for Watchdog and

Sleep Functionality

■ Flexible On-Chip Memory ❐ 4K Bytes Flash Program Storage, 100 Erase/Write Cycles

❐ 256 Bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash

■ Programmable Pin Configurations ❐ 25 mA Sink, 10 mA Drive on All GPIO

❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive

❐ Up to 12 Analog Inputs on GPIO ❐ Two 30 mA Analog Outputs on GPIO ❐ Configurable Interrupt on All GPIO

Modes on All GPIO

Blocks)

[1]

■ Additional System Resources

❐ I

C™ Slave, Master, or Multi-Master operation up to 400 kHz

❐ Watchdog and Sleep Timers ❐ User-Configurable Low Voltage Detection ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Reference

■ Complete Development Tools ❐ Free Development Software (PSoC Designer™)

❐ Full Featured, In-Circuit Emulator and Programmer ❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128K Bytes Trace Memory

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-12029 Rev. *H Revised December 07, 2009

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Features ................................................................................ 1

Logic Block Diagram ........................................................... 1

Contents ............................................................................... 2

PSoC Functional Overview ................................................. 3

PSoC Core ..................................................................... 3

Digital System ................................................................ 3

Analog System ............................................................... 4

Additional System Resources ........................................ 5

PSoC Device Characteristics ......................................... 5

Getting Started .....................................................................5

Application Notes ........................................................... 5

Development Kits ........................................................... 5

Training .......................................................................... 5

CYPros Consultants ....................................................... 5

Solutions Library............................................................. 5

Technical Support .......................................................... 5

Development Tools .............................................................6

PSoC Designer Software Subsystems........................... 6

System-Level View................................................... 6

Chip-Level View ...................................................... 6

Hybrid Designs........................................................ 6

Code Generation Tools ........................................... 6

Debugger ................................................................ 6

Online Help System ................................................ 6

In-Circuit Emulator.......................................................... 6

Designing with PSoC Designer ..........................................7

Select Components ........................................................ 7

Configure Components .................................................. 7

Organize and Connect ...................................................7

Generate, Verify, and Debug.......................................... 7

Document Conventions ...................................................... 8

Acronyms Used .............................................................. 8

Units of Measure ............................................................ 8

Numeric Naming............................................................. 8

Pinouts ................................................................................. 9

20-Pin Part Pinout .......................................................... 9

28-Pin Part Pinout ........................................................ 10

Registers ............................................................................ 11

Electrical Specifications ................................................... 14

Absolute Maximum Ratings.......................................... 15

Operating Temperature ................................................ 15

DC Electrical Characteristics........................................ 16

DC Chip-Level Specifications................................ 16

DC General Purpose I/O Specifications................ 16

DC Operational Amplifier Specifications ............... 17

DC Low Power Comparator Specifications ........... 18

DC Analog Output Buffer Specifications ............... 18

DC Analog Reference Specifications.................... 19

DC Analog PSoC Block Specifications ................. 20

DC POR and LVD Specifications .......................... 20

DC Programming Specifications ........................... 20

AC Electrical Characteristics ........................................ 21

AC Chip-Level Specifications................................ 21

AC General Purpose I/O Specifications................ 23

AC Operational Amplifier Specifications ............... 23

AC Low Power Comparator Specifications ........... 24

AC Digital Block Specifications ............................. 25

AC Analog Output Buffer Specifications ............... 26

AC External Clock Specifications.......................... 26

AC Programming Specifications ........................... 26

AC I2C Specifications ........................................... 27

Packaging Information ...................................................... 28

Thermal Impedances.................................................... 29

Capacitance on Crystal Pins ........................................ 29

Solder Reflow Peak Temperature................................ 29

Development Tool Selection ............................................30

Software ....................................................................... 30

PSoC Designer ......................................................30

PSoC Programmer................................................ 30

Development Kits ......................................................... 30

CY3215-DK Basic Development Kit....................... 30

Evaluation Tools........................................................... 30

CY3210-PSoCEval1............................................... 30

CY3210-24X23 Evaluation Pod (EvalPod)............ 30

Device Programmers.................................................... 31

CY3210-MiniProg1................................................ 31

CY3207ISSP In-System Serial

Programmer (ISSP)............................................... 31

Accessories (Emulation and Programming) ................. 31

Third Party Tools.......................................................... 31

Build a PSoC Emulator into Your Board....................... 31

Ordering Information .........................................................32

Ordering Code Definitions............................................ 32

Document History Page .................................................... 33

Sales, Solutions, and Legal Information ......................... 34

Worldwide Sales and Design Support.......................... 34

Products ....................................................................... 34

Document Number: 38-12029 Rev. *H Page 2 of 34

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PSoC Functional Overview

DIGITAL SYSTEM

To System Bus

Digital PSoC Block Array

To Analog

System

Row Input

Configuration

Row Output

Configuration

Row 0

DBB00 DBB01 DCB02 DCB03

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]

Global Digital

Interconnect

Port 2

Port 1

Port 0

The PSoC family consists of many programmable system-on-chips with on-chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and

Digital System

The Digital System is composed of four digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user modules.

Figure 1. Digital System Block Diagram

digital logic, and programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages.

The PSoC architecture, as shown in the Logic Block Diagram on page 1, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global buses allow all the device resources to be combined into a complete custom system. Each CY8C24x23A PSoC device includes four digital blocks and six analog blocks. Depending on the PSoC package, up to 24 general purpose I/O (GPIO) are also included. The GPIO provide access to the global digital and analog interconnects.

PSoC Core

The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose I/O).

The M8C CPU core is a powerful processor with speeds up to 12 MHz, providing a two MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with multiple vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep Timer and Watchdog Timer (WDT).

Memory includes 4 KB of Flash for program storage and 256 bytes of SRAM for data storage. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection.

The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to ±4% over temperature and voltage. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep Timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device.

PSoC GPIOs provide connection to the CPU, digital, and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt.

Digital peripheral configurations include:

■ PWMs (8 to 32 bit)

■ PWMs with Dead Band (8 to 24 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ Full or Half-Duplex 8-bit UART with selectable parity

■ SPI master and slave

■ I

C master, slave, or multi-master

■ Cyclical Redundancy Checker/Generator (16 bit)

■ IrDA

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family resources are shown in Ta b l e 1 on page 5.

Document Number: 38-12029 Rev. *H Page 3 of 34

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Analog System

ACB01

Block Array

Array Input Configuration

ACI1[1:0]

ASD20

ACI0[1:0]

P0[4]

RefInAGNDIn

Reference

Generators

AGNDIn

ASD11

Interface to

Digital System

M8C Interface (Address Bus, Data Bus, Etc.)

Analog Reference

P0[6]

P0[2]

P0[0]

P2[6]

P2[4]

P2[2]

P2[0]

ASD11

ASC22

ACB00

ASC10

P0[7]

P0[5]

P0[3]

P0[1]

P2[3]

P2[1]

RefIn BandGap

RefHi

RefLo

AGND

The Analog System is composed of six configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the common PSoC analog functions for this device (most available as user modules) are:

■ Analog-to-digital converters (up to two, with 6 to 14-bit

resolution, selectable as Incremental, Delta-Sigma, and SAR)

■ Filters (two and four pole band-pass, low-pass, and notch)

■ Amplifiers (up to two, with selectable gain up to 48x)

■ Instrumentation amplifiers (one with selectable gain up to 93x)

■ Comparators (up to two, with 16 selectable thresholds)

■ DACs (up to two, with 6 to 9-bit resolution)

■ Multiplying DACs (up to two, with 6 to 9-bit resolution)

■ High current output drivers (two with 30 mA drive)

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

■ Modulators

■ Correlators

■ Peak Detectors

■ Many other topologies possible

Analog blocks are arranged in a column of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in Figure 2.

Figure 2. Analog System Block Diagram

Document Number: 38-12029 Rev. *H Page 4 of 34

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Additional System Resources

Notes

2. Automotive qualified devices available in this group.

3. Limited analog functionality.

4. Two analog blocks and one CapSense™ block.

System Resources, some of which have been previously listed, provide additional capability useful for complete systems. Additional resources include a multiplier, decimator, low voltage detection, and power on reset. Brief statements describing the merits of each system resource follow:

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers.

■ A multiply accumulate (MAC) provides a fast 8-bit multiplier

with 32-bit accumulate, to assist in both general math as well as digital filters.

■ The decimator provides a custom hardware filter for digital

signal processing applications including the creation of Delta Sigma ADCs.

■ The I

C module provides 0 to 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported.

■ Low Voltage Detection (LVD) interrupts can signal the

application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3V voltage reference provides an absolute

reference for the analog system, including ADCs and DACs.

PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and analog systems can have a varying number of digital and analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted in Ta b le 1 .

Table 1. PSoC Device Characteristics

Getting Started

The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications.

For in depth information, along with detailed programming details, see the PSoC® Programmable System-on-Chip Technical Reference Manual for CY8C24x23A PSoC devices.

For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at www.cypress.com/psoc.

Application Notes

Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here:

www.cypress.com/psoc. Select Application Notes under the

Documentation tab.

Development Kits

PSoC Development Kits are available online from Cypress at

www.cypress.com/shop and through a growing number of

regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark.

Training

Free PSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The

training covers a wide variety of topics and skill levels to assist you in your designs.

CYPros Consultants

Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros.

PSoC Part

Number

CY8C29x66

CY8C27x43 up to 442 8 12 4 4 12 256

CY8C24x94 64 1 4 48 2 2 6 1K 16K

CY8C24x23A

CY8C23x33 up to 1 4 12 2 2 4 256

CY8C21x34

CY8C21x23

CY8C20x34

[2]

I/O

Digital

up to 644 16 12 4 4 12 2K 32K

[2]

up to 241 4 12 2 2 6 256

up to 281428024

16 1 4 8 0 2 4

up to 280 0 28 0 0 3

Rows

Digital

Blocks

Document Number: 38-12029 Rev. *H Page 5 of 34

Analog

Solutions Library

Size

Inputs

Analog

Outputs

Columns

Analog

[3]

[3, 4]

Blocks

Bytes

512 Bytes

256 Bytes

512 Bytes

SRAM

16K

Flash

Visit our growing library of solution focused designs at

www.cypress.com/solutions. Here you can find various appli-

cation designs that include firmware and hardware design files that enable you to complete your designs quickly.

Technical Support

For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736.

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Development Tools

PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista.

This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers.

PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family.

PSoC Designer Software Subsystems

System-Level View

A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC On-Chip Controllers that match your system requirements.

PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device.

Chip-Level View

The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.4. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application.

The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.

Hybrid Designs

You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools.

Code Generation Tools

PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours.

Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing.

C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices.

The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

Debugger

The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices.

The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.

Document Number: 38-12029 Rev. *H Page 6 of 34

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Designing with PSoC Designer

The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions.

The PSoC development process can be summarized in the following four steps:

1. Select components

2. Configure components

3. Organize and Connect

4. Generate, Verify, and Debug

Select Components

Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called “drivers” and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces

C-bus, for example), and the logic to control how they interact

with one another (called valuators).

In the chip-level view, the components are called “user modules”. User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties.

Configure Components

Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus.

Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in the PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design.

Organize and Connect

You can build signal chains at the chip level by interconnecting user modules to each other and the I/O pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions.

In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer’s output to a digital signal, and a PWM to control the fan.

In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources.

Generate, Verify, and Debug

When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system.

Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code.

A complete code development environment allows you to develop and customize your applications in C, assembly language, or both.

The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.

Document Number: 38-12029 Rev. *H Page 7 of 34

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Document Conventions

Acronyms Used

The following table lists the acronyms that are used in this document.

Table 2. Acronyms

Acronym Description

AC alternating current

ADC analog-to-digital converter

API application programming interface

CPU central processing unit

CT continuous time

DAC digital-to-analog converter

DC direct current

ECO external crystal oscillator

EEPROM electrically erasable programmable read-only

FSR full scale range

GPIO general purpose I/O

GUI graphical user interface

HBM human body model

ICE in-circuit emulator

ILO internal low speed oscillator

IMO internal main oscillator

I/O input/output

IPOR imprecise power on reset

LSb least-significant bit

LVD low voltage detect

MSb most-significant bit

PC program counter

PLL phase-locked loop

POR power on reset

PPOR precision power on reset

PSoC

PWM pulse width modulator

SC switched capacitor

SRAM static random access memory

memory

Programmable System-on-Chip

Units of Measure

A units of measure table is located in the Electrical Specifications section. Table 8 on page 14 lists all the abbreviations used to measure the PSoC devices.

Numeric Naming

Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are decimal.

Document Number: 38-12029 Rev. *H Page 8 of 34

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Pinouts

SSOP

3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA

AI, P0[7] AIO, P0[5] AIO, P0[3]

AI, P0[1]

Vss I2C SCL, P1[7] I2C SDA, P1[5]

P1[3]

I2C SCL, XTALin, P1[1]

Vss

Note

5. These are the ISSP pins, which are not High Z when coming out of POR (Power On Reset). See the PSoC Technical Reference Manual for details.

The automotive CY8C24x23A PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.

20-Pin Part Pinout

Table 3. 20-Pin Part Pinout (SSOP)

Pin No.

Typ e

Digital Analog

Name

Description

1 I/O I P0[7] Analog column mux input 2 I/O I/O P0[5] Analog column mux input and column

output

3 I/O I/O P0[3] Analog column mux input and column

output 4 I/O I P0[1] Analog column mux input 5 Power Vss Ground connection 6 I/O P1[7] I2C Serial Clock (SCL) 7 I/O P1[5] I2C Serial Data (SDA) 8 I/O P1[3] 9 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock

(SCL), ISSP-SCLK

[5]

10 Power Vss Ground connection 11 I/O P1[0] Crystal Output (XTALout), I2C Serial Data

(SDA), ISSP-SDATA

[5]

12 I/O P1[2] 13 I/O P1[4] Optional External Clock Input (EXTCLK) 14 I/O P1[6] 15 Input XRES Active high external reset with internal pull

down

16 I/O I P0[0] Analog column mux input 17 I/O I P0[2] Analog column mux input 18 I/O I P0[4] Analog column mux input 19 I/O I P0[6] Analog column mux input 20 Power Vdd Supply voltage

Figure 3. CY8C24223A 20-Pin PSoC Device

LEGEND: A = Analog, I = Input, and O = Output.

Document Number: 38-12029 Rev. *H Page 9 of 34

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28-Pin Part Pinout

SSOP

28 27 26 25 24 23 22 21 20 19 18 17 16 15

1 2 3 4 5 6 7 8

9 10 11 12 13 14

AI, P0[7] AIO, P0[5] AIO, P0[3]

AI, P0[1]

P2[7]

P2[5] AI, P2[3] AI, P2[1]

Vss

I2C SCL, P1[7]

I2C SDA, P1[5]

P1[3]

I2C SCL, XTALin, P1[1]

Vss

Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA

Table 4. 28-Pin Part Pinout (SSOP)

No.

1 I/O I P0[7] Analog column mux input 2 I/O I/O P0[5] Analog column mux input and column

3 I/O I/O P0[3] Analog column mux input and column

4 I/O I P0[1] Analog column mux input 5 I/O P2[7] 6 I/O P2[5] 7 I/O I P2[3] Direct switched capacitor block input 8 I/O I P2[1] Direct switched capacitor block input 9 Power Vss Ground connection

10 I/O P1[7] I2C Serial Clock (SCL)

11 I/O P1[5] I2C Serial Data (SDA) 12 I/O P1[3] 13 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock

14 Power Vss Ground connection 15 I/O P1[0] Crystal Output (XTALout), I2C Serial Data

16 I/O P1[2] 17 I/O P1[4] Optional External Clock Input (EXTCLK) 18 I/O P1[6] 19 Input XRES Active high external reset with internal

20 I/O I P2[0] Direct switched capacitor block input 21 I/O I P2[2] Direct switched capacitor block input 22 I/O P2[4] External Analog Ground (AGND) 23 I/O P2[6] External Voltage Reference (VRef) 24 I/O I P0[0] Analog column mux input 25 I/O I P0[2] Analog column mux input 26 I/O I P0[4] Analog column mux input 27 I/O I P0[6] Analog column mux input 28 Power Vdd Supply voltage

Typ e

Digital Analog

Name

Description

output

(SCL), ISSP-SCLK

(SDA), ISSP-SDATA

pull down

[5]

Figure 4. CY8C24423A 28-Pin PSoC Device

LEGEND: A = Analog, I = Input, and O = Output.

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Registers

Register Conventions

This section lists the registers of the automotive CY8C24x23A PSoC device. For detailed register information, reference the PSoC Technical Reference Manual.

The register conventions specific to this section are listed in the following table.

Table 5. Abbreviations

Convention Description

R Read register or bit(s)

W Write register or bit(s)

L Logical register or bit(s)

C Clearable register or bit(s)

# Access is bit specific

Register Mapping Tables

The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XIO bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XIO bit is set the user is in Bank 1.

Note In the following register mapping tables, blank fields are Reserved and must not be accessed.

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Table 6. Register Map Bank 0 Table: User Space

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access

PRT0DR 00 RW 40 ASC10CR0 80 RW C0 PRT0IE 01 RW 41 ASC10CR1 81 RW C1 PRT0GS 02 RW 42 ASC10CR2 82 RW C2 PRT0DM2 03 RW 43 ASC10CR3 83 RW C3 PRT1DR 04 RW 44 ASD11CR0 84 RW C4 PRT1IE 05 RW 45 ASD11CR1 85 RW C5 PRT1GS 06 RW 46 ASD11CR2 86 RW C6 PRT1DM2 07 RW 47 ASD11CR3 87 RW C7 PRT2DR 08 RW 48 88 C8 PRT2IE 09 RW 49 89 C9 PRT2GS 0A RW 4A 8A CA PRT2DM2 0B RW 4B 8B CB

DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW DBB00DR2 22 RW 62 A2 INT_VC E2 RC DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW DCB02DR0 28 # 68 A8 MUL_X E8 W DCB02DR1 29 W 69 A9 MUL_Y E9 W DCB02DR2 2A RW 6A AA MUL_DH EA R DCB02CR0 2B # 6B AB MUL_DL EB R DCB03DR0 2C # 6C AC ACC_DR1 EC RW DCB03DR1 2D W 6D AD ACC_DR0 ED RW DCB03DR2 2E RW 6E AE ACC_DR3 EE RW DCB03CR0 2F # 6F AF ACC_DR2 EF RW

Blank fields are Reserved and must not be accessed. # Access is bit specific.

0C 4C 8C CC 0D 4D 8D CD 0E 4E 8E CE 0F 4F 8F CF 10 50 ASD20CR0 90 RW D0

11 51 ASD20CR1 91 RW D1 12 52 ASD20CR2 92 RW D2 13 53 ASD20CR3 93 RW D3 14 54 ASC21CR0 94 RW D4 15 55 ASC21CR1 95 RW D5 16 56 ASC21CR2 96 RW I2C_CFG D6 RW 17 57 ASC21CR3 97 RW I2C_SCR D7 # 18 58 98 I2C_DR D8 RW 19 59 99 I2C_MSCR D9 # 1A 5A 9A INT_CLR0 DA RW 1B 5B 9B INT_CLR1 DB RW 1C 5C 9C DC 1D 5D 9D INT_CLR3 DD RW 1E 5E 9E INT_MSK3 DE RW 1F 5F 9F DF

30 ACB00CR3 70 RW RDI0RI B0 RW F0 31 ACB00CR0 71 RW RDI0SYN B1 RW F1 32 ACB00CR1 72 RW RDI0IS B2 RW F2 33 ACB00CR2 73 RW RDI0LT0 B3 RW F3 34 ACB01CR3 74 RW RDI0LT1 B4 RW F4 35 ACB01CR0 75 RW RDI0RO0 B5 RW F5 36 ACB01CR1 76 RW RDI0RO1 B6 RW F6 37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF #

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Table 7. Register Map Bank 1 Table: Configuration Space

Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access

PRT0DM0 00 RW 40 ASC10CR0 80 RW C0 PRT0DM1 01 RW 41 ASC10CR1 81 RW C1 PRT0IC0 02 RW 42 ASC10CR2 82 RW C2 PRT0IC1 03 RW 43 ASC10CR3 83 RW C3 PRT1DM0 04 RW 44 ASD11CR0 84 RW C4 PRT1DM1 05 RW 45 ASD11CR1 85 RW C5 PRT1IC0 06 RW 46 ASD11CR2 86 RW C6 PRT1IC1 07 RW 47 ASD11CR3 87 RW C7 PRT2DM0 08 RW 48 88 C8 PRT2DM1 09 RW 49 89 C9 PRT2IC0 0A RW 4A 8A CA PRT2IC1 0B RW 4B 8B CB

DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW

DBB01FN 24 RW 64 A4 VLT_CMP E4 R DBB01IN 25 RW 65 A5 E5 DBB01OU 26 RW AMD_CR1 66 RW A6 E6

DCB02FN 28 RW 68 A8 IMO_TR E8 W DCB02IN 29 RW 69 A9 ILO_TR E9 W DCB02OU 2A RW 6A AA BDG_TR EA RW

DCB03FN 2C RW 6C AC EC DCB03IN 2D RW 6D AD ED DCB03OU 2E RW 6E AE EE

Blank fields are Reserved and must not be accessed. # Access is bit specific.

0C 4C 8C CC 0D 4D 8D CD 0E 4E 8E CE 0F 4F 8F CF 10 50 ASD20CR0 90 RW GDI_O_IN D0 RW

11 51 ASD20CR1 91 RW GDI_E_IN D1 RW 12 52 ASD20CR2 92 RW GDI_O_OU D2 RW 13 53 ASD20CR3 93 RW GDI_E_OU D3 RW 14 54 ASC21CR0 94 RW D4 15 55 ASC21CR1 95 RW D5 16 56 ASC21CR2 96 RW D6 17 57 ASC21CR3 97 RW D7 18 58 98 D8 19 59 99 D9 1A 5A 9A DA 1B 5B 9B DB 1C 5C 9C DC 1D 5D 9D OSC_GO_EN DD RW 1E 5E 9E OSC_CR4 DE RW 1F 5F 9F OSC_CR3 DF RW

23 AMD_CR0 63 RW A3 VLT_CR E3 RW

27 ALT_CR0 67 RW A7 E7

2B 6B AB ECO_TR EB W

2F 6F AF EF 30 ACB00CR3 70 RW RDI0RI B0 RW F0 31 ACB00CR0 71 RW RDI0SYN B1 RW F1 32 ACB00CR1 72 RW RDI0IS B2 RW F2 33 ACB00CR2 73 RW RDI0LT0 B3 RW F3 34 ACB01CR3 74 RW RDI0LT1 B4 RW F4 35 ACB01CR0 75 RW RDI0RO0 B5 RW F5 36 ACB01CR1 76 RW RDI0RO1 B6 RW F6 37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF #

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Electrical Specifications

5.25

4.75

93 kHz 24 MHz

CPU Frequency

(nominal setting)

Vdd Voltage (V)

12 MHz

This section presents the DC and AC electrical specifications of the automotive CY8C24x23A PSoC device. For the latest electrical specifications, visit http://www.cypress.com/psoc.

Specifications are valid for -40

C ≤ TA ≤ 125oC and TJ ≤ 135oC, except where noted.

Figure 5. Voltage versus CPU Frequency

The following table lists the units of measure that are used in this section.

Table 8. Units of Measure

Symbol Unit of Measure Symbol Unit of Measure

C degree Celsius μVrms microvolts root-mean-square

dB decibels μW microwatts

fF femto farad mA milli-ampere

Hz hertz ms milli-second

KB 1024 bytes mV milli-volts Kbit 1024 bits nA nanoampere kHz kilohertz ns nanosecond

kΩ kilohm nV nanovolts

Mbaud megabaud Ω ohm

Mbps megabits per second pA picoampere

MHz megahertz pF picofarad

MΩ megaohm pp peak-to-peak

μA microampere ppm parts per million

μF microfarad ps picosecond

μH microhenry sps samples per second

μs microsecond σ sigma: one standard deviation

μV microvolts V volts

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Absolute Maximum Ratings

Table 9. Absolute Maximum Ratings

Symbol Description Min Typ Max Units Notes

STG

Storage Temperature -55 +25 +125

C Higher storage temperatures

reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Storage temperatures above 65 degrades reliability. Maximum combined storage and operational time at +125°C is 7000 hours.

Ambient Temperature with Power Applied -40 – +125

C Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 V V V I

MIO

IOZ

DC Input Voltage Vss - 0.5 – Vdd + 0.5 V DC Voltage Applied to Tri-state Vss - 0.5 – Vdd + 0.5 V

Maximum Current into any Port Pin -25 – +25 mA ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD. LU Latch-up Current – – 200 mA

Operating Temperature

Table 10. Operating Temperature

Symbol Description Min Typ Max Units Notes

Ambient Temperature -40 – +125

Junction Temperature -40 – +135

C The temperature rise from ambient

to junction is package specific. See

Thermal Impedances on page 29.

The user must limit the power consumption to comply with this requirement.

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DC Electrical Characteristics

Note

6. Standby current includes all functions (POR, LVD, WDT, Sleep Timer) needed for reliable system operation. This must be compared with devices that have similar functions enabled.

DC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

Table 11. DC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

Vdd Supply Voltage 4.75 – 5.25 V See table titled DC POR and LVD

SBH

SBXTL

SBXTLH

REF

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Specifications on page 20

Supply Current – 5 8 mA Conditions are Vdd = 5.25V, -40 oC ≤

TA ≤ 125 oC, CPU = 3 MHz, 48 MHz disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, Analog power = off.

Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.

[6]

– 4 13 μA Conditions are with internal low speed

oscillator active, Vdd = 5.25V, -40 oC ≤ TA ≤ 55 oC. Analog power = off.

Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.

[6]

– 4 100 μA Conditions are with internal slow

speed oscillator active, Vdd = 5.25V, 55 oC < TA ≤ 125 oC. Analog power = off.

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal.

[6]

– 6 15 μA Conditions are with properly loaded, 1

μW max, 32.768 kHz crystal. Vdd = 5.25V, -40 oC ≤ TA ≤ 55 oC. Analog power = off.

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature.

[6]

– 6 100 μA Conditions are with properly loaded,

1μW max, 32.768 kHz crystal. Vdd = 5.25V, 55 oC < TA ≤ 125oC. Analog power = off.

Reference Voltage (Bandgap) 1.25 1.3 1.35 V Trimmed for appropriate Vdd.

DC General Purpose I/O Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance.

Table 12. DC GPIO Specifications

Symbol Description Min Ty p Max Units Notes

Pull up Resistor 4 5.6 8 kΩ

Pull down Resistor 4 5.6 8 kΩ

High Output Level 3.5 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V

(maximum 40 mA on even port pins (for example, P0[2], P1[4]), maximum 40 mA on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget.

Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V

(maximum 100 mA on even port pins (for example, P0[2], P1[4]), maximum 100 mA on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget.

High Level Source Current 10 – – mA VOH ≥ Vdd-1.0V, see the limitations of

the total current in the note for V

OH.

IOL Low Level Sink Current 25 – – mA VOL ≤ 0.75V, see the limitations of the

total current in the note for V

OL.

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Table 12. DC GPIO Specifications (continued)

Symbol Description Min Ty p Max Units Notes

OUT

Input Low Level – – 0.8 V

Input High Level 2.1 – V

Input Hysterisis – 60 – mV

Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA

Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent.

Tem p = 2 5oC

Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dependent.

Tem p = 2 5oC

DC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

The Operational Amplifier is a component of both the Analog Continuous Time (CT) PSoC blocks and the Analog Switched Capacitor (SC) PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time (CT) PSoC blocks.

Table 13. DC Operational Amplifier Specifications

Symbol Description Min Ty p Max Units Notes

OSOA

TCV I

EBOA

INOA

CMOA

Input Offset Voltage (absolute value) Low Power Input Offset Voltage (absolute value) Mid Power Input Offset Voltage (absolute value) High Power

Input Offset Voltage Drift – 7.0 35.0 μV/oC

OSOA

Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin

Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias)

– – –

1.6

1.3

1.2

9 9

0.0 – Vdd

0.5 –

Vdd - 0.5V–

mV mV mV

dependent. Temp = 25 The common-mode input

voltage range is measured through an

analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer.

OLOA

Open Loop Gain Power = Low Power = Medium Power = High

– – –

80 80 80

– – –

Specification is applicable

at high power. For all other

bias modes (except high

power, high opamp bias), minimum is 60 dB.

OHIGHOA

OLOWOA

High Output Voltage Swing (worst case internal load) Power = Low Power = Medium Power = High

Low Output Voltage Swing (worst case internal load) Power = Low Power = Medium Power = High

Vdd - 0.2 Vdd - 0.2 Vdd - 0.5

– – –

0.2

0.5

V V V

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Table 13. DC Operational Amplifier Specifications (continued)

Symbol Description Min Ty p Max Units Notes

SOA

PSRR

Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High

Supply Voltage Rejection Ratio – 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or

– – – – – –

150 300

600 1200 2400 4600

200 400

800 1600 3200 6400

μA μA μA μA μA μA

(Vdd - 1.25V) ≤ VIN ≤ Vdd

DC Low Power Comparator Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 14. DC Low Power Comparator Specifications

Symbol Description Min Ty p Max Units Notes

REFLPC

SLPC

OSLPC

Low power comparator (LPC) reference voltage range 0.2 – Vdd - 1 V LPC supply current – 10 40 μA LPC voltage offset – 2.5 30 mV

DC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 15. DC Analog Output Buffer Specifications

Symbol Description Min Ty p Max Units Notes

OSOB

TCV V

CMOB

OUTOB

OHIGHOB

OLOWOB

SOB

PSRR

Input Offset Voltage (Absolute Value) – 3 18 mV Input Offset Voltage Drift – +6 – μV/°C

OSOB

Common-Mode Input Voltage Range 0.5 – Vdd - 1.0 V Output Resistance – 1 – Ω High Output Voltage Swing (Load = 32Ω to Vdd/2) 0.5 x Vdd

+ 1.1

– – V

Low Output Voltage Swing (Load = 32Ω to Vdd/2) – – 0.5 x Vdd

Supply Current Including Bias Cell (No Load) Power = Low Power = High

Supply Voltage Rejection Ratio – 64 – dB

– –

1.1

2.6

- 1.3

5.1

8.8

mA mA

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DC Analog Reference Specifications

Notes

7. This specification is only valid when CT Block Power = High. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.05V.

8. This specification is only valid when Ref Control Power = High.

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.

Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the AGND.

Table 16. DC Analog Reference Specifications

Symbol Description Min Ty p Max Units

BG Bandgap Voltage Reference 1.25 1.30 1.35 V – AGND = Vdd/2 – AGND = 2 x BandGap – AGND = P2[4] (P2[4] = Vdd/2) – AGND = BandGap – AGND = 1.6 x BandGap – AGND Column to Column Variation (AGND =

Vdd/2)

[7]

– RefHi = Vdd/2 + BandGap – RefHi = 3 x BandGap – RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) – RefHi = P2[4] + BandGap (P2[4] = Vdd/2) – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] =

1.3V)

[8]

– RefHi = 3.2 x BandGap – RefLo = Vdd/2 – BandGap – RefLo = BandGap – RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) – RefLo = P2[4] – BandGap (P2[4] = Vdd/2) – RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)

[7]

Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V

2.4 2.6 2.8 V

P2[4] - 0.02 P2[4] P2[4] + 0.02 V

1.23 1.30 1.37 V

1.98 2.08 2.14 V

-0.035 0.000 0.035 V

[8]

Vdd/2 + 1.15 Vdd/2 +1.30 Vdd/2 +1.45 V

3.65 3.9 4.15 V

P2[6] + 2.4 P2[6] + 2.6 P2[6] + 2.8 V

P2[4] + 1.24 P2[4] +1.30 P2[4] + 1.36 V

P2[4] + P2[6] - 0.1 P2[4] + P2[6] P2[4] + P2[6] + 0.1 V

[8]

3.9 4.16 4.42 V

Vdd/2 - 1.45 Vdd/2 - 1.3 1.15 V

1.15 1.3 1.45 V

2.4 - P2[6] 2.6 - P2[6] 2.8 - P2[6] V

P2[4] - 1.45 1.3 P2[4] - 1.15 V

P2[4] - P2[6] - 0.1 P2[4] - P2[6] P2[4] - P2[6] + 0.1 V

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DC Analog PSoC Block Specifications

Notes

9. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

10. The maximum total number of allowed erase/write cycles is the minimum Flash

ENPB

value multiplied by the number of flash blocks in the device.

11. Flash data retention based on the use condition of ≤ 7000 hours at T

≤ 125°C and the remaining time at TA ≤ 65°C.

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 17. DC Analog PSoC Block Specifications

Symbol Description Min Typ Max Units Notes

Resistor Unit Value (Continuous Time) – 12.24 – kΩ

Capacitor Unit Value (Switch Cap) – 80 – fF

DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Technical Reference Manual for more information on the VLT_CR register.

Table 18. DC POR and LVD Specifications

Symbol Description Min Ty p Max Units Notes

PPOR2

Vdd Value for PPOR Trip PORLEV[1:0] = 10b – 4.55 4.70 V

Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from watchdog.

Vdd Value for LVD Trip V V

LVD 6 LVD 7

VM[2:0] = 110b

VM[2:0] = 111b

4.62

4.710

4.73

4.814

4.83

4.950

V V

DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 19. DC Programming Specifications

Symbol Description Min Ty p Max Units Notes

Vdd

DDP

ILP

IHP

ILP

IHP

OLV

OHV

Flash

IWRITE

Supply Voltage for Flash Write Operations 4.75 – – V

Supply Current During Programming or Verify – 10 25 mA

Input Low Voltage During Programming or Verify – – 0.8 V

Input High Voltage During Programming or Verify 2.1 – – V

Input Current when Applying V

Programming or Verify

Input Current when Applying V

Programming or Verify

to P1[0] or P1[1] During

ILP

to P1[0] or P1[1] During

IHP

– – 0.2 mA Driving internal pull

– – 1.5 mA Driving internal pull

Output Low Voltage During Programming or Verify – – 0.75 V

Output High Voltage During Programming or Verify 3.5 – Vdd V

[11]

[9, 10]

[9]

100 – – – Erase/write cycles per

6,400 – – – Erase/write cycles.

15 – – Year s

Flash Endurance (per block)

ENPB

Flash Endurance (total)

ENT

Flash Data Retention

down resistor.

block.

Document Number: 38-12029 Rev. *H Page 20 of 34

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AC Electrical Characteristics

Notes

12. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.

13. See the individual user module data sheets for information on maximum frequencies for user modules.

AC Chip-Level Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

Table 20. AC Chip-Level Specifications

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Symbol Description Min Typ Max Units Notes

IMO24

CPU1

24M

32K1

Internal Low Speed Oscillator (ILO)

32KU

Internal Main Oscillator Frequency for 24 MHz

CPU Frequency (5V Vdd Nominal) 0.09 Digital PSoC Block Frequency 0 24 24.96 Internal Low Speed Oscillator

Frequency

Untrimmed Frequency

[12]

23.04

[12]

24 24.96

12 12.48

15 32 64 kHz This specification applies when

5 – – kHz After a reset and before the

[12]

[12, 13]

MHz Trimmed using factory trim

values. MHz MHz

the ILO has been trimmed.

M8C processor starts to

execute, the ILO is not trimmed.

32K2

External Crystal Oscillator – 32.768 – kHz Accuracy is capacitor and

crystal dependent. 50% duty

cycle.

PLL

PLL Frequency – 23.986 – MHz A multiple (x732) of crystal

frequency.

Jitter24M2 24 MHz Period Jitter (PLL) – – 800 ps Refer to Figure 9 on page 22. T

PLLSLEW

PLLSLEWSLOW

OSACC

PLL Lock Time 0.5 – 10 ms Refer to Figure 6 on page 22. PLL Lock Time for Low Gain Setting 0.5 – 50 ms Refer to Figure 7 on page 22. External Crystal Oscillator Startup to

– 1700 2620 ms Refer to Figure 8 on page 22.

1% External Crystal Oscillator Startup to

– 2800 3800 ms

100 ppm Jitter32k 32 kHz Period Jitter – 100 – ns Refer to Figure 10 on page 22. T

XRST

External Reset Pulse Width 10 – – μs DC24M 24 MHz Duty Cycle 40 50 60 % DC

ILO

Internal Low Speed Oscillator (ILO)

Duty Cycle

20 50 80 %

Step24M 24 MHz Trim Step Size – 50 – kHz Jitter24M1P 24 MHz Period Jitter (IMO)

– 600 – ps Refer to Figure 9 on page 22.

Peak-to-Peak Jitter24M1R 24 MHz Period Jitter (IMO) Root Mean

– – 600 ps

Squared F

MAX

POWERUP

Maximum frequency of signal on row

– – 12.48

input or row output.

Power Supply Slew Rate – – 250 V/ms Vdd slew rate during power up.

Time between end of POR state and

– 16 100 ms Power up from 0V.

CPU code execution

[12]

MHz

Document Number: 38-12029 Rev. *H Page 21 of 34

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Figure 6. PLL Lock Timing Diagram

24 MHz

PLL

Enable

PLLSLEW

PLL

Gai n

24 MHz

PLL

Enable

PLLSLEWLOW

PLL

Gai n

32 kHz

32K2

32K

Select

Jitter24M1P

Jitter24M2

24M

Jitter32k

32K2

Figure 7. PLL Lock for Low Gain Setting Timing Diagram

Figure 8. External Crystal Oscillator Startup Timing Diagram

Figure 9. 24 MHz Period Jitter (IMO) Timing Diagram

Figure 10. 32 kHz Period Jitter (ECO) Timing Diagram

Document Number: 38-12029 Rev. *H Page 22 of 34

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AC General Purpose I/O Specifications

TFallF TFallS

TRiseF

TRiseS

90%

10%

GPIO

Output

Voltage

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 21. AC GPIO Specifications

Symbol Description Min Typ Max Units Notes

GPIO

GPIO Operating Frequency 0 – 12.48

[12]

MHz Normal Strong Mode TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 2 – 22 ns 10% - 90% TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 22 ns 10% - 90% TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 9 27 – ns 10% - 90% TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 9 22 – ns 10% - 90%

Figure 11. GPIO Timing Diagram

AC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Note Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.

Table 22. AC Operational Amplifier Specifications

Symbol Description Min Ty p Max Units

ROA

FOA

Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High

Falling Slew Rate (80% to 20%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High

Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High

0.15

1.7

6.5

0.01

0.5

4.0

0.75

3.1

5.4

– – – – – –

–

V/μs

–

V/μs

–

V/μs

–

V/μs

–

V/μs

–

V/μs

–

V/μs

–

V/μs

–

V/μs

–

V/μs

–

V/μs

–

V/μs

–

MHz

–

MHz

–

MHz

–

MHz

–

MHz

–

MHz

Document Number: 38-12029 Rev. *H Page 23 of 34

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AC Low Power Comparator Specifications

100

1000

10000

0.001 0.01 0.1 1 10 100Freq ( kHz )

dBV/rtHz

0.01

0.1

1.0 10

100

1000

10000

0.001 0.01 0.1 1 10 100

Freq (kHz )

nV/rtHz

PH_ BH PH_ BL PM_ BL PL _B L

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 23. AC Low Power Comparator Specifications

Symbol Description Min Typ Max Units Notes

RLPC

LPC response time – – 50 μs ≥ 50 mV overdrive comparator

reference set within V

REFLPC

When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.

Figure 12. Typical AGND Noise with P2[4] Bypass

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level.

Figure 13. Typical Opamp Noise

Document Number: 38-12029 Rev. *H Page 24 of 34

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AC Digital Block Specifications

Note

14. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 24. AC Digital Block Specifications

Function Description Min Typ Max Units Notes

All Functions Maximum Block Clocking Frequency – – 24.96

Timer Capture Pulse Width 50

[14]

– – ns

Maximum Frequency, No Capture – – 24.96

Maximum Frequency, With Capture – – 24.96

Counter Enable Pulse Width 50

[14]

– – ns

Maximum Frequency, No Enable Input – – 24.96

Maximum Frequency, Enable Input – – 24.96

[12]

MHz

Dead Band Kill Pulse Width:

Asynchronous Restart Mode 20 – – ns

[14]

– – ns

[12]

MHz

[12]

MHz

CRCPRS

Synchronous Restart Mode 50

Disable Mode 50

Maximum Frequency – – 24.96

Maximum Input Clock Frequency – – 24.96

(PRS Mode)

CRCPRS

Maximum Input Clock Frequency – – 24.96

[12]

MHz

(CRC Mode)

SPIM Maximum Input Clock Frequency – – 4.16

[12]

MHz Maximum data rate is 2.08

Mbps due to 2 x over clocking.

SPIS Maximum Input Clock Frequency – – 2.08

Width of SS_ Negated Between

[14]

– – ns

[12]

MHz

Transmissions

Transmitter Maximum Input Clock Frequency – – 8.32

[12]

MHz Maximum baud rate is 1.04

Mbaud due to 8 x over clocking.

Receiver Maximum Input Clock Frequency – – 24.96

[12]

MHz Maximum baud rate is 3.12

Mbaud due to 8 x over clocking.

Document Number: 38-12029 Rev. *H Page 25 of 34

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AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 25. AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units

ROB

SOB

ROB

FOB

Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High

Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High

Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High

Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load

Power = Low Power = High

Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load

Power = Low Power = High

– –

0.6

0.8

300 300

– –

3 3

– –

μs μs

V/μs V/μs

MHz MHz

kHz kHz

AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 26. AC External Clock Specifications

Symbol Description Min Typ Max Units Notes

OSCEXT

Frequency 0.093 –24.24MHz

– High Period 20.6 – –ns

– Low Period 20.6

– Power Up IMO to Switch 150

– –ns

– – μs

AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 27. AC Programming Specifications

Symbol Description Min Typ Max Units Notes

RSCLK

FSCLK

SSCLK

HSCLK

SCLK

ERASEB

WRITE

DSCLK

PRGH

PRGC

Rise Time of SCLK 1 – 20 ns Fall Time of SCLK 1 – 20 ns Data Set up Time to Falling Edge of SCLK 40 – – ns Data Hold Time from Falling Edge of SCLK 40 – – ns Frequency of SCLK 0 – 8 MHz Flash Erase Time (Block) – 20 80 Flash Block Write Time – 80 320

[9]

ms Data Out Delay from Falling Edge of SCLK – – 50 ns Total Flash Block Program Time (T

WRITE

), Hot

+ T Total Flash Block Program Time (T

+ T

WRITE

), Cold

ERASEB

– – 200

– – 400

[9]

ms TJ ≥ 0°C

ms TJ < 0°C

Document Number: 38-12029 Rev. *H Page 26 of 34

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Notes

15. F

SCLI2C

is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the F

SCLI2C

specification adjusts accordingly.

16. A Fast-Mode I

C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement T

SUDATI2C

≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t

rmax

+ T

SUDATI2C

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

SDA

SCL

S Sr SP

BUFI2C

SPI2C

HDSTAI2C

SUSTOI2C

SUSTAI2C

LOWI2C

HIGHI2C

HDDATI2C

HDSTAI2C

SUDATI2C

C Specifications

AC I

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T

Table 28. AC Characteristics of the I

Symbol Description

SCLI2C

HDSTAI2C

LOWI2C

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

SPI2C

≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.

C SDA and SCL Pins

Standard Mode Fast Mode

Min Max Min Max

SCL Clock Frequency 0 100 Hold Time (repeated) START Condition. After this period, the first

4.0 –0.6– μs

[15]

0400

[15]

Units

kHz

clock pulse is generated. LOW Period of the SCL Clock 4.7 –1.3– μs HIGH Period of the SCL Clock 4.0 –0.6– μs Setup Time for a Repeated START Condition 4.7 –0.6– μs Data Hold Time 0 –0– μs Data Setup Time 250 –100

[16]

–ns Setup Time for STOP Condition 4.0 –0.6– μs Bus Free Time Between a STOP and START Condition 4.7 –1.3– μs Pulse Width of spikes are suppressed by the input filter. – – 0 50 ns

Figure 14. Definition for Timing for Fast/Standard Mode on the I

C Bus

Document Number: 38-12029 Rev. *H Page 27 of 34

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Packaging Information

51-85077 *C

This section illustrates the packaging specifications for the automotive CY8C24x23A PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the drawings at http://www.cypress.com/design/MR10161.

Figure 15. 20-Pin (210-Mil) SSOP

Document Number: 38-12029 Rev. *H Page 28 of 34

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Figure 16. 28-Pin (210-Mil) SSOP

51-85079 *C

Notes

17. T

= TA + POWER x θ

18. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.

Thermal Impedances Capacitance on Crystal Pins

Package Typ ical θ

20 SSOP 117 oC/W

28 SSOP 101 oC/W

[17]

Package Package Capacitance

20 SSOP 2.6 pF

28 SSOP 2.8 pF

Solder Reflow Peak Temperature

The following table lists the minimum solder reflow peak temperature to achieve good solderability.

Package Minimum Peak Temperature

20 SSOP 240oC 260oC

28 SSOP 240oC 260oC

[18]

Maximum Peak Temperature

Document Number: 38-12029 Rev. *H Page 29 of 34

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Development Tool Selection

This section presents the development tools available for the CY8C24x23A family.

Software

PSoC Designer

At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for years. PSoC Designer is available free of charge at http://www.cypress.com. PSoC Designer comes with a free C compiler.

PSoC Programmer

Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at

http://www.cypress.com/psocprogrammer.

Development Kits

All development kits can be purchased from the Cypress Online Store. The online store (www.cypress.com/shop) also has the most up to date information on kit contents, descriptions, and availability.

CY3215-DK Basic Development Kit

The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the contents of specific memory locations. Advanced emulation features are also supported through PSoC Designer. The kit includes:

■ ICE-Cube Unit

■ 28-Pin PDIP Emulation Pod for CY8C29466-24PXI

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Samples (two)

■ PSoC Designer Software CD

■ ISSP Cable

■ MiniEval Socket Programming and Evaluation board

■ Backward Compatibility Cable (for connecting to legacy Pods)

■ Universal 110/220 Power Supply (12V)

■ European Plug Adapter

■ USB 2.0 Cable

■ Getting Started Guide

■ Development Kit Registration form

Evaluation Tools

All evaluation tools can be purchased from the Cypress Online Store. The online store (www.cypress.com/shop) also has the most up to date information on kit contents, descriptions, and availability.

CY3210-PSoCEval1

The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, an RS-232 port, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

■ Evaluation Board with LCD Module

■ MiniProg Programming Unit

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

CY3210-24X23 Evaluation Pod (EvalPod)

PSoC EvalPods are pods that connect to the ICE In-Circuit Emulator (CY3215-DK kit) to allow debugging capability. They can also function as a standalone device without debugging capability. The EvalPod has a 28-pin DIP footprint on the bottom for easy connection to development kits or other hardware. The top of the EvalPod has prototyping headers for easy connection to the device's pins. CY3210-24X23 provides evaluation of the CY8C24x23A PSoC device family.

Document Number: 38-12029 Rev. *H Page 30 of 34

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Device Programmers

Notes

19. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.

20. Foot kit includes surface mount feet that can be soldered to the target PCB.

21. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at

http://www.emulation.com.

All device programmers can be purchased from the Cypress Online Store.

CY3207ISSP In-System Serial Programmer (ISSP)

The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment.

CY3210-MiniProg1

The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:

■ MiniProg Programming Unit

■ MiniEval Socket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. This software is free and can be downloaded from http://www.cypress.com. The kit includes:

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

Accessories (Emulation and Programming)

Table 29. Emulation and Programming Accessories

Part Number Pin Package Pod Kit

[19]

Foot Kit

CY8C24223A-12PVXE 20 SSOP CY3250-24X23A CY3250-20SSOP-FK

CY8C24423A-12PVXE 28 SSOP CY3250-24X23A CY3250-28SSOP-FK

[20]

Adapter

[21]

Adapters can be found at

http://www.emulation.com.

Third Party Tools

Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under Design Resources > Evaluation Boards.

Build a PSoC Emulator into Your Board

For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note “Debugging - Build a PSoC Emulator into Your Board - AN2323” at http://www.cypress.com.

Document Number: 38-12029 Rev. *H Page 31 of 34

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Ordering Information

CY 8 C 24 xxx-12xx

Package Type: Thermal Rating:

PX = PDIP Pb-Free A = Automotive -40°C to +85°C SX = SOIC Pb-Free C = Commercial PVX = SSOP Pb-Free I = Industrial LFX/LKX = QFN Pb-Free E = Automotive Extended -40°C to +125°C AX = TQFP Pb-Free

CPU Speed: 12 MHz

Part Number

Family Code

Technology Code: C = CMOS

Marketing Code: 8 = PSoC

Company ID: CY = Cypress

The following table lists the automotive CY8C24x23A PSoC device group’s key package features and ordering codes.

Package

Ordering

Code

Flash

(Bytes)

RAM

(Bytes)

Switch Mode

Pump

Range

Tem per atur e

Digital Blocks

Analog Blocks

Digital I/O Pins

Analog Inputs

Analog Outputs

20 Pin (210 Mil) SSOP CY8C24223A-12PVXE 4K 256 No -40°C to +125°C 4 6 16 8 2 Yes 20 Pin (210 Mil) SSOP

CY8C24223A-12PVXET 4K 256 No -40°C to +125°C 4 6 16 8 2 Yes

(Tape and Reel) 28 Pin (210 Mil) SSOP CY8C24423A-12PVXE 4K 256 No -40°C to +125°C 4 6 24 12 28 Pin (210 Mil) SSOP

CY8C24423A-12PVXET 4K 256 No -40°C to +125°C 4 6 24 12

[1]

2 Ye s 2 Ye s

(Tape and Reel)

Ordering Code Definitions

XRES Pin

Document Number: 38-12029 Rev. *H Page 32 of 34

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Document History Page

Document Title: CY8C24223A, CY8C24423A Automotive - Extended Temperature PSoC® Programmable System-on-Chip Document Number: 38-12029

Rev. ECN

238268 SFV See ECN First release of CY8C24x23A Automotive Preliminary Data Sheet.

271471 HMT See ECN Update per SFV memo. Input MWR changes, including removing SMP. Change

286089 HMT See ECN Update characterization data. Fine tune pinouts. Add Reflow Peak Temp. table. 512475 HMT See ECN Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add ISSP note

Orig. of Change

*D 2101387 AESA See ECN Post to www.cypress.com *E 2619935 OGNE/AESA 12/11/2008 Changed title to “CY8C24223A, CY8C24423A PSoC® Programmable

*F 2659314 PRKA/PYRS 02/13/09 Changed title to “Automotive - Extended Temperature CY8C24223A,

*G 2719510 BTK 06/16/09 Changed title. Updated Features section. Updated text of PSoC Functional

*H 2822792 BTK/AESA 12/07/2009 Added T

Submission

Date

Description of Change

to Final.

to pinout tables. Update typical and recommended Storage Temperature per extended temp. specs. Update CY branding and QFN convention. Update copyright and trademarks.

System-on-Chip™” Added note on digital signaling in DC Analog Reference Specifications on page

19. Added Die Sales information note to Ordering Information on page 32. Updated data sheet template.

CY8C24423A PSoC® Programmable System-on-Chip™” Updated Development Tools and Designing with PSoC Designer sections on pages 5 and 6.

Overview section. Updated Getting Started section. Made corrections and minor text edits to Pinouts section. Changed the name of the Register Reference section to "Registers". Improved formatting of the register tables. Added clarifying comments to some electrical specifications. Changed T MASJ input. Changed number of analog inputs for 28-pin package to 12 from 10.

specification per

RAMP

Fixed all AC specifications to conform to a ±4% IMO accuracy. Made other miscellaneous minor text edits. Deleted some non-applicable or redundant information. Added a footnote to clarify that 8 of the 12 analog inputs are regular and the other 4 are direct SC block connections. Added Development Tool Selection section.

specifications. Updated the text of footnote 10. Added maximum values and

PRGH, TPRGC, IOL

updated typical values for T Replaced T Added “Contents” on page 2. This revision fixes CDT 63984.

electrical specification with SR

RAMP

, IOH, F

ERASEB

32KU

and T

, DC

, and T

ILO

WRITE

POWERUP

electrical specifications.

POWERUP

electrical specification.

electrical

Document Number: 38-12029 Rev. *H Page 33 of 34

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Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at www.cypress.com/sales.

Products

PSoC psoc.cypress.com

Clocks & Buffers clocks.cypress.com

Wireless wireless.cypress.com

Memories memory.cypress.com

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© Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Sou rce Code and derivative works for the sole purpose of cr eating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-12029 Rev. *H Revised December 07, 2009 Page 34 of 34

PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corp. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.

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Cypress Semiconductor CY8C24223A, CY8C24423A User guide

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Logic Block Diagram

Contents

PSoC Functional Overview

DIGITAL SYSTEM

PSoC Core

Analog System

Additional System Resources

PSoC Device Characteristics

Getting Started

Application Notes

Development Kits

Training

CYPros Consultants

Solutions Library

Technical Support

Development Tools

PSoC Designer Software Subsystems

System-Level View

Chip-Level View

Hybrid Designs

Code Generation Tools

Debugger

Online Help System

In-Circuit Emulator

Designing with PSoC Designer

Select Components

Configure Components

Organize and Connect

Generate, Verify, and Debug

Document Conventions

Acronyms Used

Units of Measure

Numeric Naming

Pinouts

20-Pin Part Pinout

28-Pin Part Pinout

Registers

Register Conventions

Register Mapping Tables

Electrical Specifications

Absolute Maximum Ratings

Operating Temperature

DC Electrical Characteristics

DC Chip-Level Specifications

DC General Purpose I/O Specifications

DC Operational Amplifier Specifications

DC Low Power Comparator Specifications

DC Analog Output Buffer Specifications

DC Analog Reference Specifications

DC Analog PSoC Block Specifications

DC POR and LVD Specifications

DC Programming Specifications

AC Electrical Characteristics

AC Chip-Level Specifications

AC General Purpose I/O Specifications

AC Operational Amplifier Specifications

AC Low Power Comparator Specifications

AC Digital Block Specifications

AC Analog Output Buffer Specifications

AC External Clock Specifications

AC Programming Specifications

Packaging Information

Thermal Impedances Capacitance on Crystal Pins

Solder Reflow Peak Temperature

Development Tool Selection

Software

PSoC Designer

PSoC Programmer

Development Kits

CY3215-DK Basic Development Kit

Evaluation Tools

CY3210-PSoCEval1

CY3210-24X23 Evaluation Pod (EvalPod)

Device Programmers

CY3207ISSP In-System Serial Programmer (ISSP)