Cypress Semiconductor CY8C24223A, CY8C24423A User guide
CY8C24223A, CY8C24423A
Automotive - Extended Temperature PSoC
®
Programmable System-on-Chip
Features
Logic Block Diagram
DIGITAL SYSTEM
SRAM
256 Bytes
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
CPU Core (M8C)
SROM Flash 4K
Digital
Block
Array
Multiply
Accum.
Internal
Voltage
Ref.
Digital
Clocks
POR and LVD
System Resets
Decimator
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref
Analog
Input
Muxing
I2C
(1 Row,
4 Blocks)
System Bus
Analog
Block
Array
(2 Columns,
6 Blocks)
Port 2 Port 1
Analog
Drivers
Port 0
Note
1. There are eight standard analog inputs on the GPIO. The other four analog inputs connect from the GPIO directly to specific switched-capacitor block inputs. See
the PSoC Technical Reference Manual for more details
■ AEC Qualified
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds up to 12 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 4.75V to 5.25V Operating Voltage
❐ Automotive Temperature Range: -40°C to +125°C
■ Advanced Peripherals (PSoC
❐ Six Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Four Digital PSoC Blocks Provide:
• 8- to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full- or Half-Duplex UART
• SPI Master or Slave
• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Precision, Programmable Clocking
❐ Internal ±4% 24 MHz Oscillator
❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Low Speed, Low Power Oscillator for Watchdog and
Sleep Functionality
■ Flexible On-Chip Memory
❐ 4K Bytes Flash Program Storage, 100 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Drive on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
❐ Up to 12 Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on All GPIO
Modes on All GPIO
®
Blocks)
[1]
■ Additional System Resources
2
❐ I
C™ Slave, Master, or Multi-Master operation up to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-12029 Rev. *H Revised December 07, 2009
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Contents
Features ................................................................................ 1
Logic Block Diagram ........................................................... 1
Contents ............................................................................... 2
PSoC Functional Overview ................................................. 3
PSoC Core ..................................................................... 3
Digital System ................................................................ 3
Analog System ............................................................... 4
Additional System Resources ........................................ 5
PSoC Device Characteristics ......................................... 5
Getting Started .....................................................................5
Application Notes ........................................................... 5
Development Kits ........................................................... 5
Training .......................................................................... 5
CYPros Consultants ....................................................... 5
Solutions Library............................................................. 5
Technical Support .......................................................... 5
Development Tools .............................................................6
PSoC Designer Software Subsystems........................... 6
System-Level View................................................... 6
Chip-Level View ...................................................... 6
Hybrid Designs........................................................ 6
Code Generation Tools ........................................... 6
Debugger ................................................................ 6
Online Help System ................................................ 6
In-Circuit Emulator.......................................................... 6
Designing with PSoC Designer ..........................................7
Select Components ........................................................ 7
Configure Components .................................................. 7
Organize and Connect ...................................................7
Generate, Verify, and Debug.......................................... 7
Document Conventions ...................................................... 8
Acronyms Used .............................................................. 8
Units of Measure ............................................................ 8
Numeric Naming............................................................. 8
Pinouts ................................................................................. 9
20-Pin Part Pinout .......................................................... 9
28-Pin Part Pinout ........................................................ 10
Registers ............................................................................ 11
Register Conventions ................................................... 11
Register Mapping Tables ............................................. 11
Electrical Specifications ................................................... 14
Absolute Maximum Ratings.......................................... 15
Operating Temperature ................................................ 15
DC Electrical Characteristics........................................ 16
DC Chip-Level Specifications................................ 16
DC General Purpose I/O Specifications................ 16
DC Operational Amplifier Specifications ............... 17
DC Low Power Comparator Specifications ........... 18
DC Analog Output Buffer Specifications ............... 18
DC Analog Reference Specifications.................... 19
DC Analog PSoC Block Specifications ................. 20
DC POR and LVD Specifications .......................... 20
DC Programming Specifications ........................... 20
AC Electrical Characteristics ........................................ 21
AC Chip-Level Specifications................................ 21
AC General Purpose I/O Specifications................ 23
AC Operational Amplifier Specifications ............... 23
AC Low Power Comparator Specifications ........... 24
AC Digital Block Specifications ............................. 25
AC Analog Output Buffer Specifications ............... 26
AC External Clock Specifications.......................... 26
AC Programming Specifications ........................... 26
AC I2C Specifications ........................................... 27
Packaging Information ...................................................... 28
Thermal Impedances.................................................... 29
Capacitance on Crystal Pins ........................................ 29
Solder Reflow Peak Temperature................................ 29
Development Tool Selection ............................................30
Software ....................................................................... 30
PSoC Designer ......................................................30
PSoC Programmer................................................ 30
Development Kits ......................................................... 30
CY3215-DK Basic Development Kit....................... 30
Evaluation Tools........................................................... 30
CY3210-PSoCEval1............................................... 30
CY3210-24X23 Evaluation Pod (EvalPod)............ 30
Device Programmers.................................................... 31
CY3210-MiniProg1................................................ 31
CY3207ISSP In-System Serial
Programmer (ISSP)............................................... 31
Accessories (Emulation and Programming) ................. 31
Third Party Tools.......................................................... 31
Build a PSoC Emulator into Your Board....................... 31
Ordering Information .........................................................32
Ordering Code Definitions............................................ 32
Document History Page .................................................... 33
Sales, Solutions, and Legal Information ......................... 34
Worldwide Sales and Design Support.......................... 34
Products ....................................................................... 34
Document Number: 38-12029 Rev. *H Page 2 of 34
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PSoC Functional Overview
DIGITAL SYSTEM
To System Bus
D
i
g
i
t
a
l
C
l
o
c
k
s
F
r
o
m
C
o
r
e
Digital PSoC Block Array
To Analog
System
8
Row Input
Configuration
Row Output
Configuration
88
8
Row 0
DBB00 DBB01 DCB02 DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 2
Port 1
Port 0
The PSoC family consists of many programmable
system-on-chips with on-chip Controller devices. These devices
are designed to replace multiple traditional MCU-based system
components with one, low cost single-chip programmable
device. PSoC devices include configurable blocks of analog and
Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit
peripherals, which are called user modules.
Figure 1. Digital System Block Diagram
digital logic, and programmable interconnects. This architecture
enables the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts and packages.
The PSoC architecture, as shown in the Logic Block Diagram on
page 1, is comprised of four main areas: PSoC Core, Digital
System, Analog System, and System Resources. Configurable
global buses allow all the device resources to be combined into
a complete custom system. Each CY8C24x23A PSoC device
includes four digital blocks and six analog blocks. Depending on
the PSoC package, up to 24 general purpose I/O (GPIO) are also
included. The GPIO provide access to the global digital and
analog interconnects.
PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose I/O).
The M8C CPU core is a powerful processor with speeds up to
12 MHz, providing a two MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with
multiple vectors, to simplify programming of real time embedded
events. Program execution is timed and protected using the
included Sleep Timer and Watchdog Timer (WDT).
Memory includes 4 KB of Flash for program storage and 256
bytes of SRAM for data storage. Program Flash uses four
protection levels on blocks of 64 bytes, allowing customized
software IP protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to
±4% over temperature and voltage. A low power 32 kHz ILO
(internal low speed oscillator) is provided for the Sleep Timer and
WDT. If crystal accuracy is desired, the ECO (32.768 kHz
external crystal oscillator) is available for use as a Real Time
Clock (RTC) and can optionally generate a crystal-accurate 24
MHz system clock using a PLL. The clocks, together with
programmable clock dividers (as a System Resource), provide
the flexibility to integrate almost any timing requirement into the
PSoC device.
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system
interrupt.
Digital peripheral configurations include:
■ PWMs (8 to 32 bit)
■ PWMs with Dead Band (8 to 24 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ Full or Half-Duplex 8-bit UART with selectable parity
■ SPI master and slave
2
■ I
C master, slave, or multi-master
■ Cyclical Redundancy Checker/Generator (16 bit)
■ IrDA
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Ta b l e 1 on page 5.
Document Number: 38-12029 Rev. *H Page 3 of 34
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Analog System
ACB01
Block Array
Array Input Configuration
ACI1[1:0]
ASD20
ACI0[1:0]
P0[4]
RefInAGNDIn
Reference
Generators
AGNDIn
ASD11
Interface to
Digital System
M8C Interface (Address Bus, Data Bus, Etc.)
Analog Reference
P0[6]
P0[2]
P0[0]
P2[6]
P2[4]
P2[2]
P2[0]
ASD11
ASC22
ACB00
ASC10
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
RefIn
BandGap
RefHi
RefLo
AGND
The Analog System is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the common PSoC analog functions for this device
(most available as user modules) are:
■ Analog-to-digital converters (up to two, with 6 to 14-bit
resolution, selectable as Incremental, Delta-Sigma, and SAR)
■ Filters (two and four pole band-pass, low-pass, and notch)
■ Amplifiers (up to two, with selectable gain up to 48x)
■ Instrumentation amplifiers (one with selectable gain up to 93x)
■ Comparators (up to two, with 16 selectable thresholds)
■ DACs (up to two, with 6 to 9-bit resolution)
■ Multiplying DACs (up to two, with 6 to 9-bit resolution)
■ High current output drivers (two with 30 mA drive)
■ 1.3V reference (as a System Resource)
■ DTMF Dialer
■ Modulators
■ Correlators
■ Peak Detectors
■ Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in Figure 2.
Figure 2. Analog System Block Diagram
Document Number: 38-12029 Rev. *H Page 4 of 34
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Additional System Resources
Notes
2. Automotive qualified devices available in this group.
3. Limited analog functionality.
4. Two analog blocks and one CapSense™ block.
System Resources, some of which have been previously listed,
provide additional capability useful for complete systems.
Additional resources include a multiplier, decimator, low voltage
detection, and power on reset. Brief statements describing the
merits of each system resource follow:
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■ A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math as well
as digital filters.
■ The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
2
■ The I
C module provides 0 to 400 kHz communication over two
wires. Slave, master, and multi-master modes are all
supported.
■ Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■ An internal 1.3V voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have a varying number of digital and analog
blocks. The following table lists the resources available for
specific PSoC device groups. The PSoC device covered by this
data sheet is highlighted in Ta b le 1 .
Table 1. PSoC Device Characteristics
Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming
details, see the PSoC® Programmable System-on-Chip
Technical Reference Manual for CY8C24x23A PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
PSoC Part
Number
CY8C29x66
CY8C27x43 up to 442 8 12 4 4 12 256
CY8C24x94 64 1 4 48 2 2 6 1K 16K
CY8C24x23A
CY8C23x33 up to 1 4 12 2 2 4 256
CY8C21x34
CY8C21x23
CY8C20x34
[2]
[2]
I/O
Digital
up to 644 16 12 4 4 12 2K 32K
[2]
up to 241 4 12 2 2 6 256
up to 281428024
16 1 4 8 0 2 4
up to 280 0 28 0 0 3
Rows
Digital
Digital
Blocks
Document Number: 38-12029 Rev. *H Page 5 of 34
Analog
Solutions Library
Size
Size
Inputs
Analog
Analog
Outputs
Columns
Analog
[3]
[3]
[3, 4]
Blocks
Bytes
Bytes
Bytes
512
Bytes
256
Bytes
512
Bytes
SRAM
16K
4K
8K
8K
4K
8K
Flash
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various appli-
cation designs that include firmware and hardware design files
that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
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Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
A drag-and-drop visual embedded system design environment
based on PSoC Express. In the system level view you create a
model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
On-Chip Controllers that match your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Code Generation Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Document Number: 38-12029 Rev. *H Page 6 of 34
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select components
2. Configure components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
Both the system-level and chip-level views provide a library of
prebuilt, pretested hardware peripheral components. In the
system-level view, these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces
2
(I
C-bus, for example), and the logic to control how they interact
with one another (called valuators).
In the chip-level view, the components are called “user modules”.
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and mixed signal
varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in the PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Organize and Connect
You can build signal chains at the chip level by interconnecting
user modules to each other and the I/O pins, or connect system
level inputs, outputs, and communication interfaces to each
other with valuator functions.
In the system-level view, selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog to
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
In the chip-level view, perform the selection, configuration, and
routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Application” step. This causes PSoC Designer to generate
source code that automatically configures the device to your
specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high level functions to
control and respond to hardware events at run-time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
Document Number: 38-12029 Rev. *H Page 7 of 34
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Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Table 2. Acronyms
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only
FSR full scale range
GPIO general purpose I/O
GUI graphical user interface
HBM human body model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
I/O input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision power on reset
PSoC
PWM pulse width modulator
SC switched capacitor
SRAM static random access memory
memory
®
Programmable System-on-Chip
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 8 on page 14 lists all the abbreviations used to
measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, ‘01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are
decimal.
Document Number: 38-12029 Rev. *H Page 8 of 34
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Pinouts
SSOP
2
1
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
Vss
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
Note
5. These are the ISSP pins, which are not High Z when coming out of POR (Power On Reset). See the PSoC Technical Reference Manual for details.
The automotive CY8C24x23A PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.
20-Pin Part Pinout
Table 3. 20-Pin Part Pinout (SSOP)
Pin
No.
Typ e
Digital Analog
Pin
Name
Description
1 I/O I P0[7] Analog column mux input
2 I/O I/O P0[5] Analog column mux input and column
output
3 I/O I/O P0[3] Analog column mux input and column
output
4 I/O I P0[1] Analog column mux input
5 Power Vss Ground connection
6 I/O P1[7] I2C Serial Clock (SCL)
7 I/O P1[5] I2C Serial Data (SDA)
8 I/O P1[3]
9 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK
[5]
10 Power Vss Ground connection
11 I/O P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA
[5]
12 I/O P1[2]
13 I/O P1[4] Optional External Clock Input (EXTCLK)
14 I/O P1[6]
15 Input XRES Active high external reset with internal pull
down
16 I/O I P0[0] Analog column mux input
17 I/O I P0[2] Analog column mux input
18 I/O I P0[4] Analog column mux input
19 I/O I P0[6] Analog column mux input
20 Power Vdd Supply voltage
Figure 3. CY8C24223A 20-Pin PSoC Device
LEGEND: A = Analog, I = Input, and O = Output.
Document Number: 38-12029 Rev. *H Page 9 of 34
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CY8C24223A, CY8C24423A
28-Pin Part Pinout
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
P2[5]
AI, P2[3]
AI, P2[1]
Vss
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Table 4. 28-Pin Part Pinout (SSOP)
Pin
No.
1 I/O I P0[7] Analog column mux input
2 I/O I/O P0[5] Analog column mux input and column
3 I/O I/O P0[3] Analog column mux input and column
4 I/O I P0[1] Analog column mux input
5 I/O P2[7]
6 I/O P2[5]
7 I/O I P2[3] Direct switched capacitor block input
8 I/O I P2[1] Direct switched capacitor block input
9 Power Vss Ground connection
10 I/O P1[7] I2C Serial Clock (SCL)
11 I/O P1[5] I2C Serial Data (SDA)
12 I/O P1[3]
13 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock
14 Power Vss Ground connection
15 I/O P1[0] Crystal Output (XTALout), I2C Serial Data
16 I/O P1[2]
17 I/O P1[4] Optional External Clock Input (EXTCLK)
18 I/O P1[6]
19 Input XRES Active high external reset with internal
20 I/O I P2[0] Direct switched capacitor block input
21 I/O I P2[2] Direct switched capacitor block input
22 I/O P2[4] External Analog Ground (AGND)
23 I/O P2[6] External Voltage Reference (VRef)
24 I/O I P0[0] Analog column mux input
25 I/O I P0[2] Analog column mux input
26 I/O I P0[4] Analog column mux input
27 I/O I P0[6] Analog column mux input
28 Power Vdd Supply voltage
Typ e
Digital Analog
Pin
Name
Description
output
output
(SCL), ISSP-SCLK
(SDA), ISSP-SDATA
pull down
[5]
[5]
Figure 4. CY8C24423A 28-Pin PSoC Device
LEGEND: A = Analog, I = Input, and O = Output.
Document Number: 38-12029 Rev. *H Page 10 of 34
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CY8C24223A, CY8C24423A
Registers
Register Conventions
This section lists the registers of the automotive CY8C24x23A
PSoC device. For detailed register information, reference the
PSoC Technical Reference Manual.
The register conventions specific to this section are listed in the
following table.
Table 5. Abbreviations
Convention Description
R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific
Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks. The XIO bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XIO bit
is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Document Number: 38-12029 Rev. *H Page 11 of 34
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