Cypress Semiconductor CY8C24123A, CY8C24223A, CY8C24423A Specification Sheet

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CY8C24123A

CY8C24223A, CY8C24423A

PSoC® Programmable System-on-Chip™

Features

DIGITAL SYSTEM

SRAM

256 Bytes

Interrupt

Controller

Sleep and Watchdog

Multiple Clock Sources

(Includes IMO, ILO, PLL, and ECO)

Global Digital Interconnect

Global Analog Interconnect

PSoC CORE

CPU Core (M8C)

SROM Flash 4K

Digital

Block Array

Multiply

Accum.

Switch

Mode Pump

Internal Voltage

Ref.

Digital Clocks

POR and LVD

System Resets

Decimator

SYSTEM RESOURCES

ANALOG SYSTEM

Analog

Ref

Analog

Input

Muxing

I2C

Port 2 Port 1 Port 0

Analog Drivers

System Bus

Analog

Block

Array

Logic Block Diagram

■ Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 24 MHz ❐ 8x8 Multiply, 32-Bit Accumulate

❐ Low Power at High Speed ❐ 2.4 to 5.25V Operating Voltage ❐ Operating Voltages Down to 1.0V Using On-Chip Switch

Mode Pump (SMP)

❐ Industrial Temperature Range: -40°C to +85°C

■ Advanced Peripherals (PSoC Blocks) ❐ Six Rail-to-Rail Analog PSoC Blocks Provide:

• Up to 14-Bit ADCs

• Up to 9-Bit DACs

• Programmable Gain Amplifiers

• Programmable Filters and Comparators

❐ Four Digital PSoC Blocks Provide:

• 8 to 32-Bit Timers, Counters, and PWMs

• CRC and PRS Modules

• Full-Duplex UART

• Multiple SPI™ Masters or Slaves

• Connectable to All GPIO Pins

❐ Complex Peripherals by Combining Blocks

■ Precision, Programmable Clocking ❐ Internal ±2.5% 24/48 MHz Oscillato r

❐ High accuracy 24 MHz with optional 32 kHz Crystal and PLL ❐ Optional External Oscillator, up to 24 MHz ❐ Internal Oscillator for Watchdog and Sleep

■ Flexible On-Chip Memory ❐ 4K Flash Program Storage 50,000 Erase/Write Cycles

❐ 256 Bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash

■ Programmable Pin Configurations ❐ 25 mA Sink on all GPIO ❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive

❐ Up to Ten Analog Inputs on GPIO ❐ Two 30 mA Analog Outputs on GPIO ❐ Configurable Interrupt on All GPIO

Modes on All GPIO

■ New CY8C24x23A PSoC Device ❐ Derived From the CY8C24x23 Device ❐ Low Power and Low Voltage (2.4V)

■ Additional System Resources

❐ I

C™ Slave, Master, and MultiMaster to 400 kHz

❐ Watchdog and Sleep Timers ❐ User-Configurable Low Voltage Detection ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Reference

■ Complete Development Tools ❐ Free Development Software (PSoC Designer™)

❐ Full-Featured, In-Circuit Emulator, and Programmer ❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128K Trace Memory

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-12028 Rev. *I Revised December 11, 2008

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PSoC® Functional Overview

DIGITAL SYSTEM

To System Bus

Digital PSoC Block Array

To Analog

System

Row Input

Configuration

Row Output

Configuration

Row 0

DBB00 DBB01 DCB02 DCB03

GIE[7:0] GIO[7:0]

GOE[7:0]

GOO[7:0]

Global Digital

Interconnect

Port 2

Port 1

Port 0

The PSoC family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with a low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and

Digital System

The Digital System consists of 4 digital PSoC blocks. Each block is an 8-bit resource that may be used alone or comb ined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references.

Figure 1. Digital System Block Diagram

programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages.

The PSoC architecture, shown in Figure 1, consists of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows combining all the device resources into a complete custom system. The PSoC CY8C24x23A family can have up to three IO ports that connect to the global digital and analog interconnects, providing access to 4 digital blocks and 6 analog blocks.

PSoC Core

The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory , clocks, and configurable GPIO (General Purpose IO).

The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 11 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watchdog Timers (WDT).

Memory encompasses 4 KB of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection.

The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to

2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is required, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device.

PSoC GPIOs provide connection to the CPU, digital, and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin can generate a system interrupt on high level, low level, and change from last read.

Digital peripheral configurations are:

■ PWMs (8 to 32 bit)

■ PWMs with Dead band (8 to 24 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity

■ SPI master and slave

■ I2C slave and multi-master (one is available as a System

Resource)

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks may be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This gives a choice of system resources for your application. Family resources are shown in Table 1 on page 4.

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Analog System

ACB00 ACB01

Block Array

Array Input Configuration

ACI1[1:0]

ASD20

ACI0[1:0]

P0[6]

P0[4]

P0[2] P0[0]

P2[2] P2[0]

P2[6]

P2[4]

RefIn

AGNDIn

P0[7]

P0[5]

P0[3] P0[1]

P2[3]

P2[1]

Reference

Generators

AGNDIn RefIn Bandgap

RefHi RefLo

AGND

ASD11

ASC21

ASC10

Interface to

Digital System

M8C Interface (Address Bus, Data Bus, Etc.)

Analog Reference

The Analog System consists of six configurable blocks, each consisting of an opamp circuit that allows the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are:

■ Analog-to-digital converters (up to two, with 6 to 14-bit

resolution, selectable as Incremental, Delta Sigma, and SAR)

■ Filters (two and four pole band-pass, low-pass, and notch)

■ Amplifiers (up to two, with selectable gain to 48x)

■ Instrumentation amplifiers (one with selectable gain to 93x)

■ Comparators (up to two, with 16 selectable thresholds)

■ DACs (up to two, with 6 to 9-bit resolution)

■ Multiplying DACs (up to two, with 6 to 9-bit resolution)

■ High current output drivers (two with 30 mA drive as a PSoC

Core resource)

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

■ Modulators

■ Correlators

■ Peak Detectors

■ Many other topologies possible

Analog blocks are arranged in a column of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in Figure 2.

Figure 2. Analog System Block Diagram

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Additional System Resources

System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Statements describing the merits of each system resource follow:

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks may be generated using digital PSoC blocks as clock dividers.

■ A multiply accumulate (MAC) provides a fast 8-bit multiplier

with 32-bit accumulate, to assist in both general math and digital filters.

■ The decimator provides a custom hardware filter for digital

signal processing applications including the creation of Delta Sigma ADCs.

■ The I2C module provides 100 and 400 kHz communication over

two wires. Slave, master, and multi-master are supported.

■ Low Voltage Detection (LVD) interrupts can signal the appli-

cation of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3V reference provides an absolute reference for

the analog system, including ADCs and DACs.

■ An integrated switch mode pump (SMP) generates normal

operating voltages from a single 1.2V battery cell, providing a low cost boost converter.

Getting Started

The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, refer the PSoC Programmable Sytem-on-Chip Technical Reference Manual.

For up-to-date Ordering, Packaging, and Electrical Specification information, refer the latest PSoC device data sheets on the web at http://www.cypress.com/psoc.

Development Kits

Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at

http://www.cypress.com, click the Online Store shopping cart

icon at the bottom of the web page, and click PSoC (Program- mable System-on-Chip) to view a current list of available items.

Technical Training

Free PSoC technical training is available for beginners and is taught by a marketing or application engineer over the phone. PSoC training classes cover designing, debugging, advanced analog, and application-specific classes covering topics, such as PSoC and the LIN bus. Go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select Technical Training for more details.

PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or 4 analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted in this table.

Table 1. PSoC Device Characteristics

PSoC Part

Number

CY8C29x66 up to 644 16 12 4 4 12 2K 32K

CY8C27x43

CY8C24x94 49 1 4 48 2 2 6 1K 16K CY8C24x23

CY8C24x23A up to 241 4 12 2 2 6 256

CY8C21x34 up to 281428024

CY8C21x23

CY8C20x34

a. Limited analog functionality. b. Two analog blocks and one CapSense.

Digital IODigital

up to 442 8 12 4 4 12 256

up to 241 4 12 2 2 6 256

16 1 4 8 0 2 4a256

up to 280 0 28 0 0 3

Rows

Digital

Blocks

Analog

Inputs

Analog

Outputs

Analog

Columns

Blocks

Bytes

512 Bytes

Bytes 512

Bytes

Size

SRAM

16K

Flash

Consultants

Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants.

Technical Support

PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support.

Size

Application Notes

A long list of application notes can assist you in every aspect of your design effort. To view the PSoC application notes, go to the

http://www.cypress.com web site and select Application Notes

under the Design Resources list located in the center of the web page. Application notes are listed by date as default.

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Development Tools

Commands

Results

PSoC

Designer

Core

Engine

PSoC

Configuration

Sheet

Manufacturing

Information

File

Device

Database

Importable

Design

Database

Device

Programmer

Graphical Designer

Interface

Context

Sensitive

Help

Emulation

Pod

In-Circuit

Emulator

Project

Database

Application

Database

User

Modules

Library

PSoC

Designer

PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP (refer Figure 3).

PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs.

PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family.

Figure 3. PSoC Designer Subsystems

PSoC Designer Software Subsystems

Device Editor

The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters.

The device editor also supports the easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows changing configurations at run time.

PSoC Designer sets up power on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming, in conjunction with the device data sheet. After the framework is generated, the user can add application-specific code to flesh out the framework. It is also possible to change the selected components and regenerate the framework.

Design Browser

The Design Browser allows users to select and import preconfigured designs into the user’s project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader.

Application Editor

In the Application Editor you can edit C language and Assembly language source code. You can also assemble, compile, link, and build.

Assembler. The macro assembler allows the seamless merging of the assembly code with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing.

C Language Compiler. A C language compiler is available that supports PSoC family devices. Even if you have never worked in the C language before, the product helps you to quickly create complete C programs for the PSoC family devices.

The embedded, optimizing C compiler provides all th e features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

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Debugger

Interface

to ICE

Application Editor

Device Editor

Project

Manager

Source

Code

Editor

Storage

Inspector

User

Module

Selection

Placement

and

Parameter-

ization

Generate Application

Build All

Event &

Breakpoint

Manager

Build

Manager

Source

Code

Generator

The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices.

The emulator consists of a base unit that connects to the PC through the parallel or USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.

establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides high-level functions to control and respond to hardware events at run-time. The API also provides optional interrupt service routines that you can adapt as needed.

The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module.

The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. Pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you can also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides high-level user module API functions.

Figure 4. User Module and Source Code Development Flow s

Designing with User Modules

The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, can implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware and the software. This substantially lowers the risk of having to select a different part to meet the final design requirements.

To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called “User Modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other uncommon peripherals, such as DTMF Generators and Bi-Quad analog filter sections.

Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to

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The next step is to write your main program, and any sub-routine using PSoC Designer’s Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive “grep-style” patterns. A single mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming.

The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.

Document Conventions

Acronyms Used

The following table lists the acronyms that are used in this document.

Table 2. Acronyms Used

Acronym Description

AC alternating current ADC analog-to-digital converter API application programming interface CPU central processing unit CT continuous time DAC digital-to-analog converter DC direct current ECO external crystal oscillator EEPROM electrically erasable programmable read-only

memory FSR full scale range GPIO general purpose IO GUI graphical user interface HBM human body model ICE in-circuit emulator ILO internal low speed oscillator IMO internal main oscillator IO input/output IPOR imprecise power on reset

Table 2. Acronyms Used (continued)

Acronym Description

LSb least-significant bit LVD low voltage detect MSb most-significant bit PC program counter PLL phase-locked loop POR power on reset PPOR precision power on reset PSoC® Programmable System-on-Chip™ PWM pulse width modulator SC switched capacitor SLIMO slow IMO SMP switch mode pump SRAM static random access memory

Units of Measure

A unit of measure table is located in the section

Electrical Specifications on page 18. Table 8 on page 14 lists all

the abbreviations used to measure the PSoC devices.

Numeric Naming

Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.

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Pinouts

PDIP SOIC

1 2 3 4

8 7 6 5

Vdd P0[4], A, I P0[2], A, I P1[0], XTALout, I2C SDA

A, IO, P0[5]

A, IO, P0[3]

I2C SCL, XTALin, P1[1]

Vss

This section describes, lists, and illustrates the CY8C24x23A PSoC device pins and pinout configurations. Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.

8-Pin Part Pinoutt

Table 3. Pin Definitions - 8-Pin PDIP and SOIC

Pin No.

Type

Digital Analog

Name

Description

1 IO IO P0[5] Analog Column Mux Input and

Column Output

2 IO IO P0[3] Analog Column Mux Input and

Column Output

3 IO P1[1] Crystal Input (XTALin), I2C Serial

Clock (SCL), ISSP-SCLK* 4 Power Vss Ground Connection 5 IO P1[0] Crystal Output (XTALout), I2C Serial

Data (SDA), ISSP-SDAT A* 6 IO I P0[2] Analog Column Mux Input 7 IO I P0[4] Analog Column Mux Input 8 Power Vdd Supply Voltage

LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details.

Figure 5. CY8C24123A 8-Pin PSoC Device

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20-Pin Part Pinout

A, I, P 0[7] A, IO, P 0[5] A, IO, P 0[3]

A, I, P 0[1]

SMP I2C SCL, P1[7] I2C SDA, P1[5]

P1[3]

I2C SCL, XTALin, P1[1]

Vss

PDIP

SSOP

SOIC

20 19 18 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9

Vdd P0[6], A, I P0[4], A, I

P0[2], A, I P0[0], A, I XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA

Table 4. Pin Definitions - 20-Pin PDIP, SSOP, and SOIC

Pin No.

1 IO I P0[7] Analog Column Mux Input 2 IO IO P0[5] Analog Column Mux Input and Column

3 IO IO P0[3] Analog Column Mux Input and Column

4 IO I P0[1] Analog Column Mux Input 5 Power SMP Switch Mode Pump (SMP) Connection to

6 IO P1[7] I2C Serial Clo ck (SCL) 7 IO P1[5] I2C Serial Data (SDA) 8 IO P1[3] 9 IO P1[1] Crystal Input (XTALin), I2C Serial Clock

10 Power Vss Ground Connection. 11 IO P1[0] Crystal Output (XTALout), I2C Serial Data

12 IO P1[2] 13 IO P1[4] Optional External Clock Input (EXTCLK) 14 IO P1[6] 15 Input XRES Active High External Reset with Internal

16 IO I P0[0] Analog Column Mux Input 17 IO I P0[2] Analog Column Mux Input 18 IO I P0[4] Analog Column Mux Input 19 IO I P0[6] Analog Column Mux Input 20 Power Vdd Supply Voltage

Type

Digital Analog

Name

Description

Output

External Components required

(SCL), ISSP-SCLK*

(SDA), ISSP-SDATA*

Pull Down

Figure 6. CY8C24223A 20-Pin PSoC Device

LEGEND: A = Analog, I = Input, and O = Output.

* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details.

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28-Pin Part Pinout

A, I, P0[7] A, IO, P 0[5] A, IO, P 0[3]

A, I, P 0[1]

P2[7] P2[5]

A, I, P 2[3]

A, I, P2[1]

SMP

I2C SCL, P1[7]

I2C SDA, P1[5]

P1[3]

I2C SCL, XTALin, P1[1]

Vss

Vdd P0[6], A, I P0[4], A, I P0[2], A, I P0[0], A, I P2[6], Ex ternal VRef P2[4], Ex ternal AGND P2[2], A, I P2[0], A, I XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA

PDIP

SSOP

SOIC

1 2 3 4 5 6 7 8

9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

Table 5. Pin Definitions - 28-Pin PDIP, SSOP, and SOIC

Pin No.

1 IO I P0[7] Analog Column Mux Input 2 IO IO P0[5] Analog Column Mux Input and column

3 IO IO P0[3] Analog Column Mux Input and Column

4 IO I P0[1] Analog Column Mux Input 5 IO P2[7] 6 IO P2[5] 7 IO I P2[3] Direct Switched Capacitor Block Input 8 IO I P2[1] Direct Switched Capacitor Block Input 9 Power SMP Switch Mode Pump (SMP) Connection to

10 IO P1[7] I2C Serial Clock (SCL) 11 IO P1[5] I2C Serial Data (SDA) 12 IO P1[3] 13 IO P1[1] Crystal Input (XTALin), I2C Serial Clock

14 Power Vss Ground connection. 15 IO P1[0] Crystal Output (XTALout), I2C Serial Data

16 IO P1[2] 17 IO P1[4] Optional External Clock Input (EXTCLK) 18 IO P1[6] 19 Input XRES Active High External Reset with Internal

20 IO I P2[0] Direct Switched Capacitor Block Input 21 IO I P2[2] Direct Switched Capacitor Block Input 22 IO P2[4] External Analog Ground (AGND) 23 IO P2[6] External Voltage Reference (VRef) 24 IO I P0[0] Analog Column Mux Input 25 IO I P0[2] Analog Column Mux Input 26 IO I P0[4] Analog Column Mux Input 27 IO I P0[6] Analog Column Mux Input 28 Power Vdd Supply Voltage

Type

Digital Analog

Name

Description

output

Output

External Components required

(SCL), ISSP-SCLK*

(SDA), ISSP-SDATA*

Pull Down

Figure 7. CY8C24423A 28-Pin PSoC Device

LEGEND: A = Analog, I = Input, and O = Output.

* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details.

Document Number: 38-12028 Rev. *I Page 10 of 56

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32-Pin Part Pinout

P2[7]

P2[5] A, I, P2[3] A, I, P2[1]

Vss

SMP

QFN

(Top View )

101112

131415

1 2

4 5 6

7 8

24 23 22 21 20 19 18 17

32313029282726

P0[1], A, I

P0[3], A, IO

P0[5], A, IO

P0[7], A, I

Vdd

P0[6], A, I

P0[4], A, I

I2C SCL, P1[7]

I2C SDA, P1[5]

P0[2], A, I P0[0], A, I

XRES P1[6]

P1[3]

I2C SCL, XTALin, P1[1]

Vss

I2C SDA, XTALout, P1[0]

P1[2]

EXTCLK, P1[4]

P2[6], External VRef P2[4], External AGND P2[2], A, I P2[0], A, I

P2[7]

P2[5] A, I, P2[3] A, I, P2[1]

Vss

SMP

QFN

(Top View)

101112

131415

1 2 3 4 5 6 7 8

24 23 22 21 20 19 18 17

32313029282726

P0[1], A, I

P0[3], A, IO

P0[7], A, I

Vdd

P0[6], A, I

P0[4], A, I

12 CS CL, P1[7] 12 CS DA, P1[5]

P0[2], A, I P0[0], A, I

XRES P1[6]

P1[3]

12 CS CL, XTALin, P1[1]

Vss

12 CS DA, XTALout, P1[0]

P1[2]

EXTCLK, P1[4]

P2[6], ExternalVRef P2[4], ExternalA GND P2[2], A, I P2[0], A, I

P0[5], A, IO

Figure 9. CY8C24423A 32-Pin Sawn PSoC Device

Table 6. Pin Definitions - 32-Pin QFN**

Pin No.

1 IO P2[7] 2 IO P2[5] 3 IO I P2[3] Direct Switched Capacitor Block Input 4 IO I P2[1] Direct Switched Capacitor Block Input 5 Power Vss Ground Connection 6 Power SMP Switch Mode Pump (SMP) Connection

7 IO P1[7] I2C Serial Clock (SCL). 8 IO P1[5] I2C Serial Data (SDA). 9 NC No Connection 10 IO P1[3] 11 IO P1[1] Crystal Input (XTALin), I2C Serial Clock

12 Power Vss Ground Connection 13 IO P1[0] Crystal Output (XTALout), I2C Serial

14 IO P1[2] 15 IO P1[4] Optional External Clock Input

16 NC No Connection 17 IO P1[6] 18 Input XRES Active High External Reset with Internal

19 IO I P2[0] Direct Switched Capacitor Block Input 20 IO I P2[2] Direct Switched Capacitor Block Input 21 IO P2[4] External Analog Ground (AGND) 22 IO P2[6] External Voltage Reference (VRef) 23 IO I P0[0] Analog Column Mux Input 24 IO I P0[2] Analog Column Mux Input 25 NC No Connection 26 IO I P0[4] Analog Column Mux Input 27 IO I P0[6] Analog Column Mux Input 28 Power Vdd Supply Voltage 29 IO I P0[7] Analog Column Mux Input 30 IO IO P0[5] Analog Column Mux Input and Column

31 IO IO P0[3] Analog Column Mux Input and Column

32 IO I P0[1] Analog Column Mux Input

LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details. ** The center pad on the QFN package must be connected to ground (Vss) for best mechanical, the rmal, and electrical perfo rmance. If not connected to gr ound, it must

be electrically floated and not connected to any other signal.

Document Number: 38-12028 Rev. *I Page 11 of 56

Type

Digital Analog

Name

to External Components required

(SCL), ISSP-SCLK*

Data (SDA), ISSP-SDAT A*

(EXTCLK)

Pull Down

Output

Description

Figure 8. CY8C24423A 32-Pin PSoC Device

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56-Pin Part Pinout

SSOP

56 255 354 453 5

52 6

51 750

849 948

11 46 12 45 13

14 43 15

18 39 19 38 20

21 36 22

23 34 24 33

25 32 26 31 27

Vdd P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI P4[6] P4[4] P4[2] P4[0] CCLK HCLK XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0]

P1[6] P1[4], EXTCLK P1[2]

P1[0], XTALOut, I2C SDA, SDAT A NC NC

AI, P0[7] AIO, P0[5] AIO, P0[3]

AI, P0[1]

P2[7]

P2[5] AI, P2[3] AI, P2[1]

P4[7] P4[5] P4[3] P4[1]

OCDE OCDO

SMP P3[7] P3[5] P3[3] P3[1] P5[3]

P5[1] I2C SCL, P1[7] I2C SDA, P1[5]

P1[3]

SCLK, I2C SCL, XTALIn, P1[1]

Vss

Not for Production

The 56-pin SSOP part is for the CY8C24000A On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production. Table 7. Pin Definitions - 56-Pin SSOP

Pin No.

1 NC No Connection Figure 10. CY8C24000A 56-Pin PSoC Device 2 IO I P0[7] Analog Column Mux Input 3 IO I P0[5] Analog Column Mux Input and

4 IO I P0[3] Analog Column Mux Input and

5 IO I P0[1] Analog Column Mux Input 6 IO P2[7] 7 IO P2[5] 8 IO I P2[3] Direct Switched Capacitor Block

9 IO I P2[1] Dire ct sWitched Capacitor Block

10 IO P4[7] 11 IO P4[5] 12 IO I P4[3] 13 IO I P4[1] 14 OCD OCDEOCD Even Data IO.

Type

Digital Analog

Name

Description

Column Output

Input

15 OCD OCDOOCD Odd Data Output

16 Power SMP Switch Mode Pump (SMP)

Connection to required External

Components 17 IO P3[7] 18 IO P3[5] 19 IO P3[3] 20 IO P3[1] 21 IO P5[3] 22 IO P5[1] 23 IO P1[7] I2C Serial Clock (SCL) 24 IO P1[5] I2C Serial Data (SDA) 25 NC No Connection 26 IO P1[3] 27 IO P1[1] Crystal Input (XTALin), I2C Serial

28 Power Vdd Supply Voltage 29 NC No Connection 30 NC No Connection 31 IO P1[0] Crystal Output (XTALout), I2C

32 IO P1[2] 33 IO P1[4] Optional External Clock Input

Document Number: 38-12028 Rev. *I Page 12 of 56

Clock (SCL), ISSP-SCLK*

Serial Data (SDA), ISSP-SDAT A*

(EXTCLK)

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Table 7. Pin Definitions - 56-Pin SSOP (continued)

Pin No.

34 IO P1[6] 35 IO P5[0] 36 IO P5[2] 37 IO P3[0] 38 IO P3[2] 39 IO P3[4] 40 IO P3[6] 41 Input XRES Active high external reset with

42 OCD HCLK OCD high-speed clock output. 43 OCD CCLK OCD CPU clock output. 44 IO P4[0] 45 IO P4[2] 46 IO P4[4] 47 IO P4[6] 48 IO I P2[0] Direct switched capacitor block

49 IO I P2[2] Direct switched capacitor block

50 IO P2[4] External Analog Ground (AGND). 51 IO P2[6] E xternal Voltage Reference

52 IO I P0[0] Analog column mux input. 53 IO I P0[2] Analog column mux input and

54 IO I P0[4] Analog column mux input and

55 IO I P0[6] Analog column mux input. 56 Power Vdd Supply voltage.

Type

Digital Analog

Name

Description

internal pull down.

input.

(VRef).

column output.

LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details.

Document Number: 38-12028 Rev. *I Page 13 of 56

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This section lists the registers of the CY8C24x23A PSoC device. For detailed register information, refer the PSoC Programmable Sytem-on-Chip Reference Manual.

Abbreviations Used

The register conventions specific to this section are listed in the following table.

Table 8. Abbreviations

Convention Description

R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific

The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1.

Note In the following register mapping tables, blank fields are reserved and must not be accessed.

Document Number: 38-12028 Rev. *I Page 14 of 56

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Table 9. Register Map Bank 0 Table: User Space

Name

PRT0DR 00 RW 40 ASC10CR0 80 RW C0 PRT0IE 01 RW 41 ASC10CR1 81 RW C1 PRT0GS 02 RW 42 ASC10CR2 82 RW C2 PRT0DM2 03 RW 43 ASC10CR3 83 RW C3 PRT1DR 04 RW 44 ASD11CR0 84 RW C4 PRT1IE 05 RW 45 ASD11CR1 85 RW C5 PRT1GS 06 RW 46 ASD11CR2 86 RW C6 PRT1DM2 07 RW 47 ASD11CR3 87 RW C7 PRT2DR 08 RW 48 88 C8 PRT2IE 09 RW 49 89 C9 PRT2GS 0A RW 4A 8A CA PRT2DM2 0B RW 4B 8B CB

DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW DBB00DR1 21 W 61 A1 INT_MSK1 E1 RW DBB00DR2 22 RW 62 A2 INT_VC E2 RC DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW DCB02DR0 28 # 68 A8 MUL_X E8 W DCB02DR1 29 W 69 A9 MUL_Y E9 W DCB02DR2 2A RW 6A AA MUL_DH EA R DCB02CR0 2B # 6B AB MUL_DL EB R DCB03DR0 2C # 6C AC ACC_DR1 EC RW DCB03DR1 2D W 6D AD ACC_DR0 ED RW DCB03DR2 2E RW 6E AE ACC_DR3 EE RW DCB03CR0 2F # 6F AF ACC_DR2 EF RW

Blank fields are Reserved and must not be accessed. # Access is bit specific.

Addr (0,Hex)

0C 4C 8C CC 0D 4D 8D CD 0E 4E 8E CE 0F 4F 8F CF 10 50 ASD20CR0 90 RW D0 11 51 ASD20CR1 91 RW D1 12 52 ASD20CR2 92 RW D2 13 53 ASD20CR3 93 RW D3 14 54 ASC21CR0 94 RW D4 15 55 ASC21CR1 95 RW D5 16 56 ASC21CR2 96 RW I2C_CFG D6 RW 17 57 ASC21CR3 97 RW I2C_SCR D7 # 18 58 98 I2C_DR D8 RW 19 59 99 I2C_MSCR D9 # 1A 5A 9A INT_CLR0 DA RW 1B 5B 9B INT_CLR1 DB RW 1C 5C 9C DC 1D 5D 9D INT_CLR3 DD RW 1E 5E 9E INT_MSK3 DE RW 1F 5F 9F DF

30 ACB00CR3 70 RW RDI0RI B0 RW F0 31 ACB00CR0 71 RW RDI0SYN B1 RW F1 32 ACB00CR1 72 RW RDI0IS B2 RW F2 33 ACB00CR2 73 RW RDI0LT0 B3 RW F3 34 ACB01CR3 74 RW RDI0LT1 B4 RW F4 35 ACB01CR0 75 RW RDI0RO0 B5 RW F5 36 ACB01CR1 76 RW RDI0RO1 B6 RW F6 37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD

Access Name

Addr (0,Hex)

Access Name

Addr (0,Hex)

Access Name

Addr (0,Hex)

Access

Document Number: 38-12028 Rev. *I Page 15 of 56

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Table 9. Register Map Bank 0 Table: User Space (continued)

Name

Blank fields are Reserved and must not be accessed. # Access is bit specific.

Addr (0,Hex)

3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF #

Access Name

Addr (0,Hex)

Access Name

Addr (0,Hex)

Access Name

Addr (0,Hex)

Table 10. Register Map Bank 1 Table: Configuration Space

Name

PRT0DM0 00 RW 40 ASC10CR0 80 RW C0 PRT0DM1 01 RW 41 ASC10CR1 81 RW C1 PRT0IC0 02 RW 42 ASC10CR2 82 RW C2 PRT0IC1 03 RW 43 ASC10CR3 83 RW C3 PRT1DM0 04 RW 44 ASD11CR0 84 RW C4 PRT1DM1 05 RW 45 ASD11CR1 85 RW C5 PRT1IC0 06 RW 46 ASD11CR2 86 RW C6 PRT1IC1 07 RW 47 ASD11CR3 87 RW C7 PRT2DM0 08 RW 48 88 C8 PRT2DM1 09 RW 49 89 C9 PRT2IC0 0A RW 4A 8A CA PRT2IC1 0B RW 4B 8B CB

DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW

DBB01FN 24 RW 64 A4 VLT_CMP E4 R DBB01IN 25 RW 65 A5 E5 DBB01OU 26 RW AMD_CR1 66 RW A6 E6

DCB02FN 28 RW 68 A8 IMO_TR E8 W DCB02IN 29 RW 69 A9 ILO_TR E9 W DCB02OU 2A RW 6A AA BDG_TR EA RW

DCB03FN 2C RW 6C AC EC DCB03IN 2D RW 6D AD ED DCB03OU 2E RW 6E AE EE

Blank fields are Reserved and must not be accessed. # Access is bit specific.

Addr (1,Hex)

0C 4C 8C CC 0D 4D 8D CD 0E 4E 8E CE 0F 4F 8F CF 10 50 ASD20CR0 90 RW GDI_O_IN D0 RW 11 51 ASD20CR1 91 RW GDI_E_IN D1 RW 12 52 ASD20CR2 92 RW GDI_O_OU D2 RW 13 53 ASD20CR3 93 RW GDI_E_OU D3 RW 14 54 ASC21CR0 94 RW D4 15 55 ASC21CR1 95 RW D5 16 56 ASC21CR2 96 RW D6 17 57 ASC21CR3 97 RW D7 18 58 98 D8 19 59 99 D9 1A 5A 9A DA 1B 5B 9B DB 1C 5C 9C DC 1D 5D 9D OSC_GO_EN DD RW 1E 5E 9E OSC_CR4 DE RW 1F 5F 9F OSC_CR3 DF RW

23 AMD_CR0 63 RW A3 VLT_CR E3 RW

27 ALT_CR0 67 RW A7 E7

2B 6B AB ECO_TR EB W

2F 6F AF EF 30 ACB00CR3 70 RW RDI0RI B0 RW F0 31 ACB00CR0 71 RW RDI0SYN B1 RW F1 32 ACB00CR1 72 RW RDI0IS B2 RW F2 33 ACB00CR2 73 RW RDI0LT0 B3 RW F3 34 ACB01CR3 74 RW RDI0LT1 B4 RW F4 35 ACB01CR0 75 RW RDI0RO0 B5 RW F5 36 ACB01CR1 76 RW RDI0RO1 B6 RW F6

Access Name

Addr (1,Hex)

Access Name

Addr (1,Hex)

Access Name

Addr (1,Hex)

Access

Document Number: 38-12028 Rev. *I Page 16 of 56

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Table 10. Register Map Bank 1 Table: Configuration Space (continued)

Name

Blank fields are Reserved and must not be accessed. # Access is bit specific.

Addr (1,Hex)

37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E 7E BE CPU_SCR1 FE # 3F 7F BF CPU_SCR0 FF #

Access Name

Addr (1,Hex)

Access Name

Addr (1,Hex)

Access Name

Addr (1,Hex)

Access

Document Number: 38-12028 Rev. *I Page 17 of 56

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Electrical Specifications

5.25

4.75

3.00

93 kHz 12 MHz 24 MHz

CPU Fre que ncy

Vdd Voltage

5.25

4.75

3.00

93 kHz 12 MHz 24 MHz

IM O Frequency

Vdd Voltage

3.60

6 MHz

SLIMO Mode = 0

SLIMO

Mode=0

2.40

SLIMO

Mode=1

SLIMO

Mode=1

SLIMO

Mode=1

2.40

3 MHz

SLIMO

Mode=1

SLIMO

Mode=0

Figure 11. Volt age versus CPU Frequency Figure 12. IMO Frequency T rim Options

This section presents the DC and AC electrical specifications of the CY8C24x23A PSoC device. For the latest electrical specifications, check if you have the most recent data sheet by visiting the web at http://www.cypress.com/psoc.

Specifications are valid for -40°C ≤ T Refer to Table 31 on page 32 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.

≤ 85°C and TJ ≤ 100°C, except where noted.

The following table lists the units of measure that are used in this section.

Ta ble 11. Units of Measure

Symbol Unit of Measure Symbol Unit of Measure

°C degree Celsius μW microwatts dB decibels mA milli-ampere fF femto farad ms milli-second Hz hertz mV milli-volts KB 1024 bytes nA nanoampere Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts kΩ kilohm W ohm MHz megahertz pA picoampere MΩ megaohm pF picofarad

μA microampere pp peak-to-peak μF microfarad ppm parts per million μH microhenry ps picosecond μs microsecond sps samples per second μV microvolts s sigma: one standard deviation μVrms microvolts root-mean-square V volts

Document Number: 38-12028 Rev. *I Page 18 of 56

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Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Table 12. Absolute Maximum Ratings

Symbol Description Min Typ Max Units Notes

STG

Storage Temperature -55 25 +100 °C Higher storage temperatures

reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 65°C degrades reliability.

Ambient Temperature with Power Applied -40 – +85 °C Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 V V

MIO

IOZ

DC Input Voltage Vss - 0.5 – Vdd +

0.5

DC Voltage Applied to Tri-state Vss - 0.5 – Vdd +

0.5

Maximum Current into any Port Pin -25 – +50 mA ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD. LU Latch-up Current – – 200 mA

Operating Temperature

Table 13. Operating Temperature

Symbol Description Min Typ Max Units Notes

Ambient Temperature -40 – +85 °C

Junction Temperature -40 – +100 °C The temperature rise from ambient

to junction is package specific. See

T able 50 on page 51. The user must

limit the power consumption to comply with this requirement.

Document Number: 38-12028 Rev. *I Page 19 of 56

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DC Electrical Characteristics

DC Chip-Level Specifications

Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to

≤ T

5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 14. DC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

Vdd Supply Voltage 2.4 – 5.25 V See DC POR and LVD specifications,

Table 29 on page 30.

DD3

DD27

SBH

SBXTL

SBXTLH

REF

REF27

Supply Current – 5 8 mA Conditions are Vdd = 5.0V , TA = 25°C,

CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. SLIMO mode = 0. IMO = 24 MHz.

Supply Current – 3.3 6.0 mA Conditions are Vdd = 3.3V , TA= 25 °C,

CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. SLIMO mode = 0. IMO = 24 MHz.

Supply Current – 2 4 mA Conditions are Vdd = 2.7V , TA = 25°C,

CPU = 0.75 MHz, SYSCLK doubler disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz, analog power = off. SLIMO mode = 1. IMO = 6 MHz.

Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.

Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal.

Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature.

– 3 6.5 μA Conditions are with internal slow

speed oscillator, Vdd = 3.3V, -40°C ≤ T

≤ 55°C, analog power = off.

– 4 25 μA Conditions are with internal slow

speed oscillator, Vdd = 3.3V , 55°C < T ≤ 85°C, analog power = off.

– 4 7.5 μA Conditions are with properly loaded,

1 μW max, 32.768 kHz crystal. Vdd = 3.3V , -40°C ≤ T power = off.

≤ 55°C, analog

– 5 26 μA Conditions are with properly loaded,

1μW max, 32.768 kHz crystal. Vdd = 3.3 V , 55°C < T power = off.

≤ 85°C, analog

Reference Voltage (Bandgap) 1.28 1.30 1.33 V Trimmed for appropriate Vdd.

Vdd > 3.0V

Reference Voltage (Bandgap) 1.16 1.30 1.33 V Trimmed for appropriate Vdd.

Vdd = 2.4V to 3.0V

a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar

functions enabled.

Document Number: 38-12028 Rev. *I Page 20 of 56

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DC General Purpose IO Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

Table 15. 5V and 3.3V DC GPIO Specificati on s

Symbol Description Min Typ Max Units Notes

Pull up Resistor 4 5.6 8 kΩ Pull down Resistor 4 5.6 8 kΩ High Output Level Vdd - 1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V

(maximum 40 mA on even port pins (for example, P0[2], P1[4]), maximum 40 mA on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget.

Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V

(maximum 100 mA on even port pins (for example, P0[2], P1[4]), maximum 100 mA on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL

budget. V V V I C

IL IH H

OUT

Input Low Level – – 0.8 V Vdd = 3.0 to 5.25 Input High Level 2.1 – V Vdd = 3.0 to 5.25 Input Hysterisis – 60 – mV Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent.

Temp = 25°C

Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dependent.

Temp = 25°C

Table 16. 2.7V DC GPIO Specifications

Symbol Description Min Typ Max Units Notes

Pull up Resistor 4 5.6 8 kΩ Pull down Resistor 4 5.6 8 kΩ High Output Level Vdd - 0.4 – – V IOH = 2 mA (6.25 Typ), Vdd = 2.4

to 3.0V (16 mA maximum, 50 mA

Typ combined IOH budget). V

Low Output Level – – 0.75 V IOL = 11.25 mA, Vdd = 2.4 to 3.0V

(90 mA maximum combined IOL

budget). V V V I C

IL IH H

OUT

Input Low Level – – 0.75 V Vdd = 2.4 to 3.0 Input High Level 2.0 – – V Vdd = 2.4 to 3.0 Input Hysteresis – 90 – mV Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent.

Temp = 25

Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dep endent.

Temp = 25

Document Number: 38-12028 Rev. *I Page 21 of 56

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DC Operational Amplifier Specifications

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switch ed Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25°C and are for design guidance only.

Table 17. 5V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

OSOA

TCV I

EBOA

INOA

CMOA

Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

Average Input Offset Voltage Drift – 7.0 35.0 μV/°C

OSOA

–1.6 – –

1.3

1.2

7.5

mV mV mV

Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 μA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent.

Temp = 25°C

Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias)

0.0 – Vdd

0.5 –

Vdd - 0.5

V The common-mode input voltage

range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer.

OLOA

OHIGHOA

OLOWOA

SOA

PSRR

Open Loop Gain Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

60 60 80

– – dB Specification is applicable at high

power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB.

High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

Vdd - 0.2 Vdd - 0.2 Vdd - 0.5

– – –

V V V

Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

– – –

0.2

0.5

V V V

Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = High Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Power = High, Opamp Bias = High

Supply Voltage Rejection Ratio 64 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or

– – – – – –

150 300

600 1200 2400 4600

200 400

800 1600 3200 6400

μA μA μA μA μA μA

(Vdd - 1.25V) ≤ VIN ≤ Vdd

Document Number: 38-12028 Rev. *I Page 22 of 56

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Table 18. 3.3V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

OSOA

Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High

–

1.65

–

1.32

mV mV

High Power is 5 Volts Only TCV I

EBOA

INOA

CMOA

Average Input Offset Voltage Drift – 7.0 35.0 μV/°C

OSOA

Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 μA

Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent.

Temp = 25°C

Common Mode Voltage Range 0.2 – Vdd - 0.2 V The common-mode input voltage

range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer.

OLOA

OHIGHOA

OLOWOA

SOA

PSRR

Open Loop Gain

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = Low

Power = High, Opamp Bias = Low

60 60 80

High Output Voltage Swing (internal signals)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = Low

Power = High is 5V only

Vdd - 0.2 Vdd - 0.2 Vdd - 0.2

Low Output Voltage Swing (internal signals)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = Low

Power = High, Opamp Bias = Low

– – –

Supply Current (including associated AGND

buffer)

Power = Low, Opamp Bias = Low

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = Low

Power = High, Opamp Bias = High

Supply Voltage Rejection Ratio 64 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or

– – – – – –

– – dB Specification is applicable at high

power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB.

– – –

150 300

600 1200 2400 4600

– – –

0.2

200 400

800 1600 3200 6400

V V V

μA μA μA μA μA μA

(Vdd - 1.25V) ≤ VIN ≤ Vdd

Document Number: 38-12028 Rev. *I Page 23 of 56

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Table 19. 2.7V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

OSOA

Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High

–

1.65

–

1.32

mV mV

High Power is 5 Volts Only TCV I

EBOA

INOA

CMOA

Average Input Offset Voltage Drift – 7.0 35.0 μV/°C

OSOA

Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 μA

Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent.

Temp = 25°C

Common Mode Voltage Range 0.2 – Vdd - 0.2 V The common-mode input voltage

range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer.

OLOA

OHIGHOA

OLOWOA

SOA

PSRR

Open Loop Gain

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = Low

Power = High

60 60 80

High Output Voltage Swing (internal signals)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = Low

Power = High is 5V only

Vdd - 0.2 Vdd - 0.2 Vdd - 0.2

Low Output Voltage Swing (internal signals)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = Low

Power = High, Opamp Bias = Low

– – –

Supply Current (including associated AGND

buffer)

Power = Low, Opamp Bias = Low

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = Low

Power = High, Opamp Bias = High

Supply Voltage Rejection Ratio 6 4 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or

– – – – – –

– – dB Specification is applicable at high

power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB.

– – –

150 300

600 1200 2400 4600

– – –

0.2

200 400

800 1600 3200 6400

V V V

μA μA μA μA μA μA

(Vdd - 1.25V) ≤ VIN ≤ Vdd

DC Low Power Comparator Specifications

Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to

5V at 25°C and are for design guidance only.

Table 20. DC Low Power Comparator Specifications

Symbol Description Min Typ Max Units

REFLPC

SLPC

OSLPC

Low power comparator (LPC) reference voltage range

LPC supply current – 10 40 μA LPC voltage offset – 2.5 30 mV

Document Number: 38-12028 Rev. *I Page 24 of 56

0.2 – Vdd - 1 V

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DC Analog Output Buffer Specifications

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

Table 21. 5V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

OSOB

TCV V

CMOB

OUTOB

OHIGHOB

OLOWOB

SOB

PSRR

Input Offset Voltage (Absolute Value) – 3 12 mV Average Input Offset Voltage Drift – +6 – μV/°C

OSOB

Common-Mode Input Voltage Range 0.5 – Vdd - 1.0 V Output Resistance

Power = Low Power = High

– –

1 1

– –

High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High

0.5 x Vdd + 1.1

0.5 x Vdd

+ 1.1

– –

Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High

– –

––.5 x Vdd - 1.3

0.5 x Vdd

Supply Current Including Bias Cell (No Lo ad) Power = Low Power = High

Supply Voltage Rejection Ratio 52 64 – dB V

– –

1.1

2.6

5.1

8.8

- 1.3

W W

V V

mA mA

> (Vdd - 1.25).

OUT

Table 22. 3.3V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

OSOB

TCV V

CMOB

OUTOB

OHIGHOB

OLOWOB

SOB

PSRR

Input Offset Voltage (Absolute Value) – 3 12 mV Average Input Offset Voltage Drift – +6 – μV/°C

OSOB

Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 V Output Resistance

Power = Low Power = High

– –

1 1

– –

High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High

0.5 x Vdd + 1.0

0.5 x Vdd

+ 1.0

– –

Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High

– –

––0.5 x Vdd - 1.0

0.5 x Vdd

Supply Current Including Bias Cell (No Lo ad) Power = Low Power = High

Supply Voltage Rejection Ratio 52 64 – dB V

–

0.8

2.0

4.3

- 1.0

W W

V V

mA mA

> (Vdd - 1.25)

OUT

Document Number: 38-12028 Rev. *I Page 25 of 56

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Table 23. 2.7V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

OSOB

TCV V

CMOB

OUTOB

OHIGHOB

OLOWOB

SOB

PSRR

Input Offset Voltage (Absolute Value) – 3 12 mV Average Input Offset Voltage Drift – +6 – μV/°C

OSOB

Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 V Output Resistance

Power = Low Power = High

– –

1 1

– –

High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High

0.5 x Vdd + 0.2

0.5 x Vdd

+ 0.2

– –

Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High

– –

––0.5 x Vdd - 0.7

0.5 x Vdd

Supply Current Including Bias Cell (No Lo ad) Power = Low Power = High

Supply Voltage Rejection Ratio 52 64 – dB V

–

0.8

2.0

4.3

- 0.7

W W

V V

mA mA

> (Vdd - 1.25).

OUT

DC Switch Mode Pump Specifications

Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 24. DC Switch Mode Pump (SMP) Specifications

Symbol Description Min Typ Max Units Notes

5V 5V Output Voltage from Pump 4.75 5.0 5.25 V Configuration listed in footnote.a

PUMP

Average, neglecting ripple. SMP trip voltage is set to 5.0V.

3V 3.3V Output Voltage from Pump 3.00 3.25 3.60 V Configuration listed in footnote.a

PUMP

Average, neglecting ripple. SMP trip voltage is set to 3.25V.

2V 2.6V Output Voltage from Pump 2.45 2.55 2.80 V Configuration listed in footnote.a

PUMP

Average, neglecting ripple. SMP trip voltage is set to 2.55V.

PUMP

5V Input Voltage Range from Battery 1.8 – 5.0 V Configuration listed in footnote.a

BAT

3V Input Voltage Range from Battery 1.0 – 3.3 V Configuration listed in footnote.a

BAT

2V Input Voltage Range from Battery 1.0 – 3.0 V Configuration listed in footnote.a

BAT

BATSTART

Available Output Current V

BAT

= 1.8V, V = 1.5V, V = 1.3V, V

PUMP PUMP PUMP

= 5.0V = 3.25V = 2.55V

Minimum Input Voltage from Battery to Start Pump

Configuration listed in footnote. 5 8 8

– – –

SMP trip voltage is set to 5.0V.

SMP trip voltage is set to 3.25V.

SMP trip voltage is set to 2.55V.

SMP trip voltage is set to 5.0V.

SMP trip voltage is set to 3.25V.

SMP trip voltage is set to 2.55V.

1.2 – – V Configuration listed in footnote.a = -40°C

≤ 100. 1.25V at

0°C ≤ T T

Document Number: 38-12028 Rev. *I Page 26 of 56

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Table 24. DC Switch Mode Pump (SMP) Specifications (continued)

Battery

PSoC

Vdd

Vss

SMP

BAT

PUMP

Symbol Description Min Typ Max Units Notes

ΔV

PUMP_Line

Line Regulation (over V

range) – 5 – %VO Configuration listed in footnote.a

BAT

is the “Vdd Value for PUMP

Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 29 on page 30.

ΔV

PUMP_Load

Load Regulation – 5 – %VO Configuration listed in footnote.a

is the “Vdd Value for PUMP

Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, T able 29 on page 30.

ΔV

PUMP_Ripple

Output Voltage Ripple (depends on capacitor/load)

– 100 – mVpp Configuration listed in footnote.a

Load is 5 mA.

Efficiency 35 50 – % Configuration listed in footnote.a

Load is 5 mA. SMP trip voltage is set to 3.25V.

PUMP

a. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 13.

Efficiency Switching Frequency – 1.3 – MHz Switching Duty Cycle – 50 – %

Figure 13. Basic Switch Mode Pump Circuit

Document Number: 38-12028 Rev. *I Page 27 of 56

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DC Analog Reference Specifications

The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high.

Note Avoid using P2[4] for digital signaling when using an analog re source that depen ds on the Analog Refere nce. Some coupling of the digital signal may appear on the AGND.

Table 25. 5V DC Analog Reference Specifications

Symbol Description Min Typ Max Units

BG Bandgap Voltage Reference 1.28 1.30 1.33 V – AGND = Vdd/2 Vd d/2 - 0.04 Vdd/2 - 0.01 Vdd/2 + 0.007 V – AGND = 2 x BandGap 2 x BG - 0.048 2 x BG - 0.030 2 x BG + 0.024 V – AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.011 P2[4] P2[4] + 0.011 V – AGND = BandGap BG - 0.009 BG + 0.008 BG + 0.016 V – AGND = 1.6 x BandGap 1.6 x BG - 0.022 1.6 x BG - 0.010 1.6 x BG + 0.018 V – AGND Block to Block Variation

– RefHi = Vdd/2 + BandGap Vdd/2 + BG - 0.10 Vdd/2 + BG Vdd/2 + BG + 0.10 V – RefHi = 3 x BandGap 3 x BG - 0.06 3 x BG 3 x BG + 0.06 V – RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077 V – RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098 V – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2

– RefHi = 3.2 x BandGap 3.2 x BG - 0.112 3.2 x BG 3.2 x BG + 0.076 V – RefLo = Vdd/2 – BandGap Vdd/2 - BG - 0.04 Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.04 V – RefLo = BandGap BG - 0.06 BG BG + 0.06 V – RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134 V – RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 V – RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

(AGND = Vdd/2)

P2[6] = 1.3V)

-0.034 0.000 0.034 V

P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6]+ 0.100 V

P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110 V

Table 26. 3.3V DC Analog Reference Specifications

Symbol Description Min Typ Max Units

BG Bandgap Voltage Reference 1.28 1.30 1.33 V – AGND = Vdd/2 Vd d/2 - 0.03 Vdd/2 - 0.01 Vdd/2 + 0.005 V – AGND = 2 x BandGap Not Allowed – AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.008 P2[4] + 0.001 P2[4] + 0.009 V – AGND = BandGap BG - 0.009 BG + 0.005 BG + 0.015 V – AGND = 1.6 x BandGap 1.6 x BG - 0.027 1.6 x BG - 0.010 1.6 x BG + 0.018 V – AGND Column to Column Variation

(AGND = Vdd/2) – RefHi = Vdd/2 + BandGap Not Allowed – RefHi = 3 x BandGap Not Allowed – RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed – RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed

Document Number: 38-12028 Rev. *I Page 28 of 56

-0.034 0.000 0.034 mV

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Table 26. 3.3V DC Analog Reference Specifications (continued)

Symbol Description Min Typ Max Units

– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,

P2[6] = 0.5V) – RefHi = 3.2 x BandGap Not Allowed – RefLo = Vdd/2 - BandGap Not Allowed – RefLo = BandGap Not Allowed – RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed – RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed – RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,

P2[6] = 0.5V)

Table 27. 2.7V DC Analog Reference Specifications

Symbol Description Min Typ Max Units

BG Bandgap Voltage Reference 1.16 1.30 1.33 V – AGND = Vdd/2 Vd d/2 - 0.03 Vdd/2 - 0.01 Vdd/2 + 0.01 V – AGND = 2 x BandGap Not Allowed – AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.01 P2[4] P2[4] + 0.01 V – AGND = BandGap BG - 0.01 BG BG + 0.015 V – AGND = 1.6 x BandGap Not Allowed – AGND Column to Column Variation

P2[6] = 0.5V)

P2[4] + P2[6] - 0.075 P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057 V

P2[4] - P2[6] - 0.048 P2[4]- P2[ 6] + 0.022 P2[4] - P2[6] + 0.092 V

-0.034 0.000 0.034 mV

P2[4] + P2[6] - 0.08 P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.06 V

P2[4] - P2[6] - 0.05 P2[4]- P2[6] + 0.01 P2[4] - P2[6] + 0.09 V

Document Number: 38-12028 Rev. *I Page 29 of 56

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DC Analog PSoC Block Specifications

Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to

5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 28. DC Analog PSoC Block Specifications

Symbol Description Min Typ Max Units Notes

Resistor Unit Value (Continuous Time) – 12.2 – kΩ Capacitor Unit V alue (Switched Capacitor) – 80 – fF

DC POR, SMP, and LVD Specifications

Table 30 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to

5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for more information on the VLT_CR register.

Table 29. DC POR and LVD Specifications

Symbol Description Min Typ Max Units Notes

Vdd Value for PPOR Trip

PPOR0

PPOR1

PPOR2

LVD0

LVD1

LVD2

LVD3

LVD4

LVD5

LVD6

LVD7

PUMP0

PUMP1

PUMP2

PUMP3

PUMP4

PUMP5

PUMP6

PUMP7

a. Always greater than 50 mV above V b. Always greater than 50 mV above V c. Always greater than 50 mV above V d. Always greater than 50 mV above

PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b

Vdd Value for SMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b

(PORLEV=00) for falling supply.

PPOR

(PORLEV=01) for falling supply.

PPOR

LVD0

LVD3

–

2.40

2.85

2.95

3.06

4.37

4.50

4.62

4.71

2.50

2.96

3.03

3.18

4.54

4.62

4.71

4.89

2.36

2.82

4.55

2.45

2.92

3.02

3.13

4.48

4.64

4.73

4.81

2.55

3.02

3.10

3.25

4.64

4.73

4.82

5.00

2.40

2.95

4.70

0 0

2.51

2.99

a b

3.09

3.20

4.55

4.75

4.83

4.95

2.62

3.09

3.16

3.32

4.74

4.83

4.92

5.12

Vdd must be greater than

or equal to 2.5V during

startup, reset from the

XRES pin, or reset from Watchdog.

V V V

Document Number: 38-12028 Rev. *I Page 30 of 56

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DC Programming Specifications

Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to

5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 30. DC Programming Specifications

Symbol Description Min Typ Max Units Notes

Vdd

DDP

ILP

IHP

ILP

IHP

OLV

OHV

Flash

Flash Flash

a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum

Supply Voltage for Flash Write Operations 2.70 – – V

IWRIT

Supply Current During Programming or Verify – 5 25 mA Input Low Voltage During Programming or Verify – – 0.8 V Input High Voltage During Programming or Verify 2.1 – – V Input Current when Applying Vilp to P1[0] or P1[1]

During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1]

During Programming or Verify

– – 0.2 mA Driving internal pull down

resistor.

– – 1.5 mA Driving internal pull down

resistor. Output Low Voltage During Programming or Verify – – Vss + 0.75 V Output High Voltage During Programming or

Vdd - 1.0 – Vdd V

Verify Flash Endurance (per block) 50,000 – – – Erase/write cycles per

ENP

Flash Endurance (total)

ENT

Flash Data Retention 10 – – Years

cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles).

For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

1,800,000 – – – Erase/write cycles

block

Document Number: 38-12028 Rev. *I Page 31 of 56

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AC Electrical Characteristics

AC Chip-Level Specifications

Table 31. 5V and 3.3V AC Chip-Level Spec ifications

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

Symbol Description Min Typ Max Units Notes

IMO24

Internal Main Oscillator Frequency for 24 MHz

23.4 24 24.6

a,b,c

MHz Trimmed for 5V or 3.3V operation

using factory trim values. See Figure

12 on page 18. SLIMO mode = 0.

IMO6

Internal Main Oscillator Frequency for 6 MHz

5.75 6 6.35

a,b,c

MHz Trimmed for 5V or 3.3V operation

using factory trim values. See Figure

12 on page 18. SLIMO mode = 1.

F F F

F F

CPU1 CPU2 48M

24M 32K1

32K2

PLL

CPU Frequency (5V Nominal) 0.93 24 24.6 CPU Frequency (3.3V Nominal) 0.93 12 12.3 Digital PSoC Block Frequency 0 48 49.2

Digital PSoC Block Frequency 0 24 24.6 Internal Low Speed Oscillator

15 32 64 kHz

Frequency External Crystal Oscillator – 32.768 – kHz Accuracy is capacitor and crystal

PLL Frequency – 23.986 – MHz Is a multiple (x732) of crystal

a,b

MHz

b,c

MHz

a,b,d

MHz Refer to the AC Digital Block

Specifications.

b, d

MHz

dependent. 50% duty cycle.

frequency. Jitter24M2 24 MHz Period Jitter (PLL) – – 600 ps T

PLLSLEW

PLLSLEWSLOW

OSACC

PLL Lock Time 0.5 – 10 ms PLL Lock Time for Low Gain Setting 0.5 – 50 ms External Crystal Oscillator Startup to 1% – 1700 2620 ms External Crystal Oscillator Startup to

– 2800 3800 ms The crystal oscillator frequency is

100 ppm

within 100 ppm of its final value by the

end of the T

operation assumes a properly loaded

period. Correct

osacc

1 uW maximum drive level 32.768

kHz crystal. 3.0V ≤ Vdd ≤ 5.5V , -40

≤ T

≤ 85 oC.

Jitter32k 32 kHz Period Jitter – 100 ns T

XRST

External Reset Pulse Width 10 – – μs DC24M 24 MHz Duty Cycle 40 50 60 % Step24M 24 MHz Trim Step Size – 50 – kHz Fout48M 48 MHz Output Frequency 46.8 48.0 49.2 Jitter24M1P 24 MHz Period Jitter (IMO)

– 300 ps

a,c

MHz Trimmed. Using factory trim values.

Peak-to-Peak Jitter24M1R 24 MHz Period Jitter (IMO) Root Mean

– – 600 ps

Squared F

MAX

RAMP

a. 4.75V < Vdd < 5.25V . b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual V oltage-Range Operation” for information on trimming for

operation at 3.3V.

d. See the individual user module data sheets for information on maximum frequencies for user modules.

Maximum frequency of signal on row

– – 12.3 MHz

input or row output.

Supply Ramp Time 0 – – μs

Document Number: 38-12028 Rev. *I Page 32 of 56

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Table 32. 2.7V AC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

IMO12

Internal Main Oscillator Frequency for

12 MHz

11.5 12 12.7

a,b,c

MHz Trimmed for 2.7V operation using

factory trim values. See Figure 12 on page 18. SLIMO mode = 1.

IMO6

Internal Main Oscillator Frequency for 6

MHz

5.75 6 6.35

a,b,c

MHz Trimmed for 2.7V operation using

factory trim values. See Figure 12 on page 18. SLIMO mode = 1.

CPU1

BLK27

32K1

CPU Frequency (2.7V Nominal)

Digital PSoC Block Frequency (2.7V

Nominal)

Internal Low Speed Oscillator

Frequency

0.93

0 12 12.7

3.15

a,b

a,b,c

8 32 96 kHz

MHz MHz0Refer to the AC Digital Block

Specifications.

Jitter32k 32 kHz Period Jitter – 150 ns T

XRST

External Reset Pulse Width 10 – – μs DC12M 12 MHz Duty Cycle 40 50 60 % Jitter12M1P 12 MHz Period Jitter (IMO)

– 340 ps

Peak-to-Peak Jitter12M1R 12 MHz Period Jitter (IMO) Root Mean

– – 600 ps

Squared F

MAX

RAMP

a. 2.4V < Vdd < 3.0V. b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. c. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Volt a ge-Ran ge Operat ion” fo r info rmation on maximum fre quen cy for User Modules.

Maximum frequency of signal on row

– – 12.7 MHz

input or row output.

Supply Ramp Time 0 – – μs

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Figure 14. PLL Lock Timing Diagram

24 MHz

PLL

Enable

PLLSLEW

PLL

Gain

24 MHz

PLL

Enable

PLLSLEWLOW

PLL

Gain

32 kHz

32K2

32K

Select

Jitter24M1

24M

Jitter32k

32K2

Figure 15. PLL Lock for Low Gain Setting Timing Diagram

Figure 16. External Crystal Oscillator Startup Timing Diagram

Figure 17. 24 MHz Period Jitter (IMO) Timing Diagram

Figure 18. 32 kHz Period Jitter (ECO) Timing Diagram

Document Number: 38-12028 Rev. *I Page 34 of 56

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AC General Purpose IO Specifications

TFallF TFallS

TRiseF

TRiseS

90%

10%

GPI O

Output

Voltage

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

Table 33. 5V and 3.3V AC GPIO Specificati on s

Symbol Description Min Typ Max Units Notes

GPIO

GPIO Operating Frequency 0 – 12 MHz Normal Strong Mode TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90% TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90% TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10% - 90% TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10% - 90%

Table 34. 2.7V AC GPIO Specifications

Symbol Description Min Typ Max Units Notes

GPIO

TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF TFallF Fall Time, Normal Strong Mode, Cload = 50 pF

GPIO Operating Frequency 0 – 3 MHz Normal Strong Mode

6 – 50 ns Vdd = 2.4 to 3.0V, 10% - 90%

6 – 50 ns Vdd = 2.4 to 3.0V, 10% - 90% TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 18 40 120 ns Vdd = 2.4 to 3.0V, 10% - 90% TFallS Fall Time, Slow Strong Mode, Cload = 50 pF

18 40 120 ns Vdd = 2.4 to 3.0V, 10% - 90%

Figure 19. GPIO Timing Diagram

Document Number: 38-12028 Rev. *I Page 35 of 56

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AC Operational Amplifier Specifications

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V and 2.7V.

Table 35. 5V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units

ROA

SOA

ROA

FOA

NOA

Table 36. 3.3V AC Operational Amplifier Specifications

Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

– – –

–

– –

3.9

0.72

0.62

μs μs μs

Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

– – –

5.9

0.92

0.72

μs μs μs

Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

0.15

1.7

6.5

– – –

V/μs V/μs V/μs

Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

0.01

0.5

4.0

– – –

V/μs V/μs V/μs

Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

0.75

3.1

5.4

– – –

MHz MHz MHz

Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

Symbol Description Min Typ Max Units

ROA

SOA

NOA

ROA

FOA

Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High

– –

3.92

0.72

μs μs

Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High

– –

5.41

0.72

μs μs

Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High

0.31

2.7

– –

V/μs V/μs

Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High

0.24

1.8

– –

V/μs V/μs

Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High

0.67

2.8

– –

MHz MHz

Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

Document Number: 38-12028 Rev. *I Page 36 of 56

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Table 37. 2.7V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units

ROA

SOA

NOA

ROA

FOA

Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High

– –

3.92

0.72

Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High

– –

5.41

0.72

Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High

0.31

2.7

– –

Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High

0.24

1.8

– –

Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High

0.67

2.8

– –

Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

μs μs

V/μs V/μs

MHz MHz

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When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up

100

1000

10000

0.001 0.01 0.1 1 10 100Freq (kHz)

dBV/rtHz

0.01

0.1

1.0 10

100

1000

10000

0.001 0.01 0.1 1 10 100

Freq (kHz)

nV/rtHz

PH_BH PH_BL PM_BL PL_BL

to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.

Figure 20. Typical AGND Noise with P2[4] Bypass

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level.

Figure 21. Typical Opamp Noise

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AC Low Power Comparator Specifications

Table 38 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to

5V at 25°C and are for design guidance only.

Table 38. AC Low Power Comparator Specifications

Symbol Description Min Typ Max Units Notes

RLPC

LPC response time – – 50 μs ≥ 50 mV overdrive comparator

reference set within V

REFLPC

AC Digital Block Specifications

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

Table 39. 5V and 3.3V AC Digital Block Specifications

Function Description Min Typ Max Units Notes

Timer Capture Pulse Width 50

– – ns Maximum Frequency, No Capture – – 49.2 MHz 4.75V < Vdd < 5.25V Maximum Frequency, With Capture – – 24.6 MHz

Counter Enable Pulse Width 50

– – ns Maximum Frequency, No Enable Input – – 49.2 MHz 4.75V < Vdd < 5.25V Maximum Frequency, Enable Input – – 24.6 MHz

Dead Band Kill Pulse Width:

Asynchronous Restart Mode 20 – – ns Synchronous Restart Mode 50 Disable Mode 50

a a

– – ns

– – ns Maximum Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V

CRCPRS

Maximum Input Clock Frequency – – 49.2 MHz 4.75V < Vdd < 5.25V

(PRS Mode) CRCPRS

Maximum Input Clock Frequency – – 24.6 MHz

(CRC Mode) SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz

due to 2 x over clocking.

SPIS Maximu m Input Clock Frequency – – 4.1 ns

Width of SS_ Negated Between Transmissions 50

– – ns

Transmitter Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08

MHz due to 8 x over clocking.

Maximum Input Clock Frequency with Vdd ≥

4.75V, 2 Stop Bits

– – 49.2 MHz Maximum data rate at 6.15

MHz due to 8 x over clocking.

Receiver Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08

MHz due to 8 x over clocking.

Maximum Input Clock Frequency with Vdd ≥

4.75V, 2 Stop Bits

a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

– – 49.2 MHz Maximum data rate at 6.15

MHz due to 8 x over clocking.

Document Number: 38-12028 Rev. *I Page 39 of 56

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Table 40. 2.7V AC Digital Block Specifications

Function Description Min Typ Max Units Notes

All

Maximum Block Clocking Frequency 12.7 MHz 2.4V < Vdd < 3.0V

Functions Timer Capture Pulse Width 100

–

Maximum Frequency, With or Without Capture – – 12.7 MHz

Counter Enable Pulse Width 100

–

ns Maximum Frequency, No Enable Input – – 12.7 MHz Maximum Frequency, Enable Input – – 12.7 MHz

Dead Band

Kill Pulse Width:

Asynchronous Restart Mode 20 – – ns Synchronous Restart Mode 100 Disable Mode

100

a a

–

ns Maximum Frequency – – 12.7 MHz

CRCPRS

Maximum Input Clock Frequency – – 12.7 MHz

(PRS Mode)

CRCPRS

Maximum Input Clock Frequency – – 12.7 MHz

(CRC Mode)

SPIM Maximum Input Clock Frequency – – 6.35 MHz Maximum data rate at 3.17 MHz

due to 2 x over clocking.

SPIS Maximum Input Clock Frequency – – 4.23 ns

Transmitter

Width of SS_ Negated Between Transmissions 100

Maximum Input Clock Frequency – – 12.7 MHz Max imum data rate at 1.59 MHz

–

due to 8 x over clocking.

Receiver Maximum Input Clock Frequency – – 12.7 MHz Maximum data rate at 1.59 MH z

due to 8 x over clocking.

a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).

Document Number: 38-12028 Rev. *I Page 40 of 56

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AC Analog Output Buffer Specifications

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

Table 41. 5V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units

ROB

SOB

ROB

FOB

Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High

Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High

Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High

Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load

Power = Low Power = High

Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load

Power = Low Power = High

– –

0.65

0.8

300 300

– –

2.5

2.2

– –

μs μs

V/μs V/μs

MHz MHz

kHz kHz

Table 42. 3.3V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units

ROB

SOB

ROB

FOB

Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High

Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High

Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High

Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load

Power = Low Power = High

Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load

Power = Low Power = High

– –

0.5

0.7

200 200

– –

3.8

2.6

– –

V/μs V/μs

MHz MHz

kHz kHz

μs μs

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Table 43. 2.7V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units

ROB

SOB

ROB

FOB

Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High

Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High

Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High

Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load

Power = Low Power = High

Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load

Power = Low Power = High

– –

0.4

0.6

180 180

– –

4 4

3 3

– –

μs μs

V/μs V/μs

MHz MHz

kHz kHz

AC External Clock Specifications

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

Table 44. 5V AC External Clock Specifications

Symbol Description Min Typ Max Units

OSCEXT

– High Period 20.6 – Low Period 20.6

Frequency 0.093 – 24.6 MHz

– 5300 ns – –ns

– Power Up IMO to Switch 150 – – μs

Table 45. 3.3V AC External Clock Specifications

Symbol Description Min Typ Max Units

OSCEXT

Frequency with CPU Clock divide by 1

Frequency with CPU Clock divide by 2 or greater – High Period with CPU Clock divide by 1 41.7 – Low Period with CPU Clock divide by 1 41.7 – Power Up IMO to Switch 150

a. Maximum CPU frequency is 12 MHz at 3.3V. With th e CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle

requirements.

b. If the frequency of the external clock is greater t han 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the

fifty percent duty cycle requirement is met.

0.093 –12.3MHz

0.186 –24.6MHz – 5300 ns – –ns – – μs

Document Number: 38-12028 Rev. *I Page 42 of 56

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Table 46. 2.7V AC External Clock Specifications

Symbol Description Min Typ Max Units

OSCEXT

Frequency with CPU Clock divide by 1 Frequency with CPU Clock divide by 2 or greater

0.093 –12.3MHz

0.186 –12.3MHz

– High Period with CPU Clock divide by 1 41.7 – 5300 ns – Low Period with CPU Clock divide by 1 41.7 – Power Up IMO to Switch 150

a. Maximum CPU frequency is 12 MHz at 3.3V. With th e CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle

requirements.

b. If the frequency of the external clock is greater t han 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the

fifty percent duty cycle requirement is met.

– –ns – – μs

AC Programming Specifications

Table 47 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to

5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 47. AC Programming Specifications

Symbol Description Min Typ Max Units Notes

RSCLK

FSCLK

SSCLK

HSCLK

SCLK

ERASEB

WRITE

DSCLK

DSCLK3

DSCLK2

Rise Time of SCLK 1 – 20 ns Fall Time of SCLK 1 – 20 ns Data Setup Time to Falling Edge of SCLK 40 – – ns Data Hold Time from Falling Edge of SCLK 40 – – ns Frequency of SCLK 0 – 8 MHz Flash Erase Time (Block) – 20 – ms Flash Block Write Time – 20 – ms Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6 Data Out Delay from Falling Edge of SCLK – – 70 ns 2.4 ≤ Vdd ≤ 3.0

AC I2C Specifications

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

Table 48. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V

Symbol Description

SCLI2C

HDSTAI2C

LOWI2C

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SCL Clock Frequency 0 100 0 400 kHz Hold Time (repeated) START Condition. After

this period, the first clock pulse is generated. LOW Period of the SCL Clock 4.7 –1.3– μs HIGH Period of the SCL Clock 4.0 –0.6– μs Setup Time for a Repeated START Condition 4.7 –0.6– μs Data Hold Time 0 –0– μs Data Setup Time 250 –100a–ns

Document Number: 38-12028 Rev. *I Page 43 of 56

Standard Mode Fast Mode Min Max Min Max

Units

4.0 –0.6– μs

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Table 48. AC Characteristics of the I

SDA

SCL

Sr SP

BUFI2C

SPI2C

HDSTAI2C

SUSTOI2C

SUSTAI2C

LOWI2C

HIGHI2C

HDDATI2C

HDSTAI2C

SUDATI2C

Symbol Description

SUSTOI2C

BUFI2C

SPI2C

a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t

Setup Time for STOP Condition 4.0 –0.6– μs Bus Free Time Between a STOP and START

Condition Pulse Width of spikes are suppressed by the

input filter.

automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretc h the LOW period of the SCL signal, it must output the next d at a bit to t he S DA li ne t

tion) before the SCL line is released.

C SDA and SCL Pins for Vdd > 3.0V (continued)

Standard Mode Fast Mode Min Max Min Max

4.7 –1.3– μs

– –050ns

SU;DAT

+ t

rmax

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specifica-

SU;DAT

Š 250 ns must then be met. This is

Table 49. AC Characteristics of the I2C SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported)

Units

Symbol Description

SCLI2C

HDSTAI2C

LOWI2C

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

SPI2C

SCL Clock Frequency 0 100 – –kHz Hold Time (repeated) START Condition. After

this period, the first clock pulse is generated. LOW Period of the SCL Clock 4.7 – – – μs HIGH Period of the SCL Clock 4.0 – – – μs Setup Time for a Repeated START Condition 4.7 – – – μs Data Hold Time 0 – – – μs Data Setup Time 250 – – –ns Setup Time for STOP Condition 4.0 – – – μs Bus Free Time Between a STOP and START

Condition Pulse Width of spikes are suppressed by the

input filter

Figure 22. Definition for Timing for Fast/Standard Mode on the I2C Bus

Standard Mode Fast Mode Min Max Min Max

Units

4.0 – – – μs

4.7 – – – μs

– – – –ns

Document Number: 38-12028 Rev. *I Page 44 of 56

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Packaging Information

0.115

0.100 BSC.

0.125

0.055

0.014

0.015 MIN.

0.145

0.070

0.022

0.140

SEATING

PLANE

0.380

0.240

0.180 MAX.

0.300

0.430 MAX.

0.325

0.008 0°-10°

0.015

0.390

0.260

DIMENSIONS IN INCHES MIN.

MAX.

PIN 1 ID

51-85075 *A

This section illustrates the packaging specifications for the CY8C24x23A PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a de tailed descripti on of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/design/MR10161.

Packaging Dimensions

Figure 23. 8-Pin (300-Mil) PDIP

Document Number: 38-12028 Rev. *I Page 45 of 56

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Figure 24. 8-Pin (150-Mil) SOIC

0.0075[0.190]

0.0098[0.249]

1. DIMENSIONS IN INCHES[MM] MIN.

RECTANGULAR ON MATRIX LEADFRAME

SEATING PLANE

PIN 1 ID

0.230[5.842]

0.244[6.197]

0.157[3.987]

0.150[3.810]

0.189[4.800]

0.196[4.978]

0.050[1.270] BSC

0.061[1.549]

0.068[1.727]

0.004[0.102]

0.0098[0.249]

0.0138[0.350]

0.0192[0.487]

0.016[0.406]

0.035[0.889]

MAX.

0°~8°

0.016[0.406]

0.010[0.254] X 45°

2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME

0.004[0.102]

3. REFERENCE JEDEC MS-012

PART #

S08.15 STANDARD PKG.

SZ08.15 LEAD FREE PKG.

4. PACKAGE WEIGHT 0.07gms

51-85066 *C

51-85011-A

20-Lead (300-Mil) Molded DIP P5

51-85011 *A

Figure 25. 20-Pin (300-Mil) Molded DIP

Document Number: 38-12028 Rev. *I Page 46 of 56

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Figure 26. 20-Pin (210-Mil) SSOP

51-85077 *C

51-85024 *C

Figure 27. 20-Pin (300-Mil) Molded SOIC

Document Number: 38-12028 Rev. *I Page 47 of 56

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Figure 28. 28-Pin (300-Mil) Molded DIP

51-85014 *D

51-85079 *C

Figure 29. 28-Pin (210-Mil) SSOP

Document Number: 38-12028 Rev. *I Page 48 of 56

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Figure 30. 28-Pin (300-Mil) Molded SOIC

51-85026 *D

X = 138 MIL Y = 138 MIL

TOP VIEW

BOTTOM VIEW

SEATING PLANE

0°-12°

PIN1 ID

SIDE VIEW

0.20 R.

3.50

0.45

3.503.50

-0.20

3.50

0.50

0.42±0.18

[4X]

1. HATCH AREA IS SOLDERABLE EXPOSED PAD.

2. REFERENCE JEDEC#: MO-220

4. ALL DIMENSIONS ARE IN MM [MIN/MAX]

NOTES

32LD QFN 5 X 5mm PACKAGE OUTLINE

01/29/07

PART #

PB-FREE

STANDARD

LY32

5. PACKAGE CODE

51-85188SEE NOTES

CMG

UNLESS OTHERWISE SPECIFIED

ALL DIMENSIONS ARE IN INCHES [MILLIMETERS]

MATERIAL

STANDARD TOLERANCES ON: DECIMALS

.XXX .XXXX

.XX

+ +

COMPANY CONFIDENTIAL

APPROVED BY

DRAWN

ANGLES

CHK BY

DATE

CYPRESS

TITLE

SIZE

PART NO. DWG NO REV

11/01/06

DESCRIPTION

3. PACKAGE WEIGHT: 0.054g

JSO

LF32

PAD

EXPOSED

SOLDERABLE

(SUBCON PUNCH TYPE PKG with 3.50 X 3.50 EPAD)

CHANGED SPEC. TITLE, CORRECTED EPAD DIMENSION

51-85188 *B

Figure 31. 32-Pin (5x5 mm) QFN

Document Number: 38-12028 Rev. *I Page 49 of 56

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Figure 32. 32-Pin Sawn QFN Package

COMPANY CONFIDENTIAL

CYPRESS

TITLE

SOLDERA BLE

EXPOSED

PAD

4. DIMENSIONS ARE IN MILLIMETERS

2. BASED ON REF JEDEC # MO-220

NOTES:

1. HA TCH AREA IS SOLDERABLE EXPOSED PAD

3. PACKA G E WEIGHT: 0.058g

001-30999 *A

51-85062 *C

Important Note For information on the preferred dimensions for mounting QFN packages, see the following application note at

http://www.amkor.com/products/notes_papers/MLF AppNote.pdf.

Figure 33. 56-Pin (300-Mil) SSOP

Document Number: 38-12028 Rev. *I Page 50 of 56

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Thermal Impedances Capacitance on Crystal Pins

Table 50. Thermal Impedances per Package

Package Typical θ

8 PDIP 123°C/W 8 SOIC 185°C/W 20 PDIP 109°C/W 20 SSOP 117 °C/W 20 SOIC 81°C/W 28 PDIP 69 °C/W 28 SSOP 101°C/W 28 SOIC 74 °C/W 32 QFN 22°C/W

* TJ = TA + POWER x θ

Table 51. Typical Package Capacitance on Crystal Pins

Package Package Capacitance

8 PDIP 2.8 pF 8 SOIC 2.0 pF 20 PDIP 3.0 pF 20 SSOP 2.6 pF 20 SOIC 2.5 pF 28 PDIP 3.5 pF 28 SSOP 2.8 pF 28 SOIC 2.7 pF 32 QFN 2.0 pF

Solder Reflow Peak Temperature

The following table lists the minimum solder reflow peak temperatures to achieve good solderability.

Table 52. Solder Reflow Peak Tempera t ure

Package Minimum Peak T emperature* Maximum Peak Temperature

8 PDIP 240°C 260°C 8 SOIC 240°C 260°C 20 PDIP 240°C 260°C 20 SSOP 240°C 260°C 20 SOIC 220°C 260°C 28 PDIP 240°C 260°C 28 SSOP 240°C 260°C 28 SOIC 220°C 260°C 32 QFN 240°C 260°C

*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5

C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.

Document Number: 38-12028 Rev. *I Page 51 of 56

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Development Tool Selection

This section presents the development tools available for all current PSoC device families including the CY8C24x23A family.

Software

PSoC Designer

At the core of the PSoC development software suite is PSoC Designer. Used by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at

http://www.cypress.com under DESIGN RESOURCES >>

Software and Drivers.

PSoC Express

As the newest addition to the PSoC development software suite, PSoC Express is the first visual embedded system design tool that allows a user to create an entire PSoC project and generate a schematic, BOM, and data sheet without writing a single line of code. Users work directly with application objects such as LEDs, switches, sensors, and fans. PSoC Express is available free of charge at http://www.cypress.com/psocexpress.

PSoC Programmer

Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocpro-

grammer.

CY3202-C iMAGEcraft C Compiler

CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items.

Development Kits

All development kits can be purchased from the Cypress Online Store.

CY3215-DK Basic Development Kit

The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes:

■ PSoC Designer Software CD

■ ICE-Cube In-Circuit Emulator

■ ICE Flex-Pod for CY8C29x66 Family

■ Cat-5 Adapter

■ Mini-Eval Programming Board

™

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ iMAGEcraft C Compiler (Registration Required)

■ ISSP Cable

■ USB 2.0 Cable and Blue Cat-5 Cable

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

CY3210-ExpressDK PSoC Express Development Kit

The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (may be used with ICE-Cube In-Circuit Emulator). It provides access to I

C buses, voltage reference, switches, upgradeable modules and more. The kit includes:

■ PSoC Express Software CD

■ Express Development Board

■ 4 Fan Modules

■ 2 Proto Modules

■ MiniProg In-System Serial Programmer

■ MiniEval PCB Evaluation Board

■ Jumper Wire Kit

■ USB 2.0 Cable

■ Serial Cable (DB9)

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples

■ 2 CY8C27443-24PXI 28-PDIP Chip Samples

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

Evaluation Tools

All evaluation tools can be purchased from the Cypress Online Store.

CY3210-MiniProg1

The CY3210-MiniProg1 kit allows a user to program PSoC devices through the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC through a provided USB 2.0 cable. The kit includes:

■ MiniProg Programming Unit

■ MiniEval Socket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

Document Number: 38-12028 Rev. *I Page 52 of 56

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CY3210-PSoCEval1

The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

■ Evaluation Board with LCD Module

■ MiniProg Programming Unit

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

CY3214-PSoCEvalUSB

The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes:

■ PSoCEvalUSB Board

■ LCD Module

■ MIniProg Programming Unit

■ Mini USB Cable

■ PSoC Designer and Example Projects CD

■ Getting Started Guide

■ Wire Pack

Device Programmers

All device programmers can be purchased from the Cypress Online Store.

CY3216 Modular Programmer

The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:

■ Modular Programmer Base

■ 3 Programming Module Cards

■ MiniProg Programming Unit

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

CY3207ISSP In-System Serial Programmer (ISSP)

The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

Accessories (Emulation and Programming)

Table 53. Emulation and Programming Accessories

Part # Pin Package Flex-Pod Kit

Foot Kit

All non-QFN All non QFN CY3250-24X23A CY3250-8DIP-FK,

CY3250-8SOIC-FK, CY3250-20DIP-FK, CY3250-20SOIC-FK, CY3250-20SSOP-FK, CY3250-28DIP-FK, CY3250-28SOIC-FK, CY3250-28SSOP-FK

CY8C24423A-24LFXI 32 QFN CY3250-24X23AQFN CY3250-32QFN-FK

a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. b. Foot kit includes surface mount feet that can be soldered to the target PCB. c. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at

http://www.emulation.com.

Third Party Tools

Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN

Build a PSoC Emulator into Your Board

For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see application note AN2323 “Debugging - Build a PSoC Emulator into Your Board”.

RESOURCES >> Evaluation Boards.

Document Number: 38-12028 Rev. *I Page 53 of 56

Adapter

Adapters can be found at

http://www.emulation.com.

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Ordering Information

CY 8 C 24 xxx-SPxx

Package Type: Thermal Rating:

PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free

AX = TQFP Pb-Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress

The following table lists the CY8C24x23A PSoC device’s key package features and ordering codes.

Table 54. CY8C24x23A PSoC Device Key Features and Ordering Information

Package

Ordering

Code

Flash

(Bytes)

SRAM

(Bytes)

Switch Mode

Pump

Range

Temperature

Digital Blocks

Analog Blocks

Digital IO Pins

Analog Inputs

Analog Outputs

8 Pin (300 Mil) DIP CY8C24123A-24PXI 4K 256 No -40C to +85C 4 6 6 4 2 No 8 Pin (150 Mil) SOIC CY8C24123A-24SXI 4K 256 No -40C to +85C 4 6 6 4 2 No 8 Pin (150 Mil) SOIC

(Tape and Reel)

CY8C24123A-24SXIT 4K 256 No -40C to +85C 4 6 6 4 2 No

20 Pin (300 Mil) DIP CY8C24223A-24PXI 4K 256 Yes -40C to +85C 4 6 16 8 2 Yes 20 Pin (210 Mil) SSOP CY8C24223A-24PVXI 4K 256 Yes -40C to +85C 4 6 16 8 2 Yes 20 Pin (210 Mil) SSOP

(Tape and Reel)

CY8C24223A-24PVXIT 4K 256 Yes -40C to +85C 4 6 16 8 2 Yes

20 Pin (300 Mil) SOIC CY8C24223A-24SXI 4K 256 Yes -40C to +85C 4 6 16 8 2 Yes 20 Pin (300 Mil) SOIC

(Tape and Reel)

CY8C24223A-24SXIT 4K 256 Yes -40C to +85C 4 6 16 8 2 Yes

28 Pin (300 Mil) DIP CY8C24423A-24PXI 4K 256 Yes -40C to +85C 4 6 24 10 2 Yes 28 Pin (210 Mil) SSOP CY8C24423A-24PVXI 4K 256 Yes -40C to +85C 4 6 24 10 2 Yes 28 Pin (210 Mil) SSOP

(Tape and Reel)

CY8C24423A-24PVXIT 4K 256 Yes -40C to +85C 4 6 24 10 2 Yes

28 Pin (300 Mil) SOIC CY8C24423A-24SXI 4K 256 Yes -40C to +85C 4 6 24 10 2 Yes 28 Pin (300 Mil) SOIC

(Tape and Reel)

CY8C24423A-24SXIT 4K 256 Yes -40C to +85C 4 6 24 10 2 Yes

32 Pin (5x5 mm) QFN CY8C24423A-24LFXI 4K 256 Yes -40C to +85C 4 6 24 10 2 Yes 32 Pin (5x5 mm 0.93 MAX)

SAWN QFN 32 Pin (5x5 mm 0.93 MAX)

SAWN QFN (Tape and Reel) 56 Pin OCD SSOP CY8C24000A-24PVXI

a. This part may be used for in-circuit debugging. It is NOT available for production

CY8C24423A-24LTXI 4K 256

CY8C24423A-24LTXIT 4K 256

4K 256 Yes -40C to +85C 4 6 24 10 2 Yes

Yes -40C to +85C 4 6 24 10 2 Yes

Yes -40C to +85C 4 6 24 10 2

Yes

Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).

Ordering Code Definitions

XRES Pin

Document Number: 38-12028 Rev. *I Page 54 of 56

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Document History Page

Document Title: CY8C24123A, CY8C24223A, CY8C24423A PSoC® Programmable System-on-Chip™ Document Number: 38-12028

Rev. ECN

** 236409 SFV See ECN New silicon and new document – Preliminary Data Sheet. *A 247589 SFV See ECN Changed the title to read “Final” data sheet. Updated Electrical Specifications

*B 261711 HMT See ECN Input all SFV memo changes. Updated Electrical Specifications chapter. *C 279731 HMT See ECN Update Electrical Specifications chapter, including 2.7 VIL DC GPIO spec. Add

*D 352614 HMT See ECN Add new color and CY logo. Add URL to preferred dimensions for mounting MLF

*E 424036 HMT See ECN Fix SMP 8-pin SOIC error in Feature and Order table. Update 32-pin QFN E-Pad

*F 521439 HMT See ECN Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add new Dev.

*G 2256806 UVS/PYRS See ECN Added Sawn pin information. *H 2425586 DSO/AESA See ECN Corrected Ordering Information to include CY8C24423A-24LTXI and

*I 2619935 OGNE/AESA 12/11/2008 Changed title to “CY8C24123A, CY8C24223A, CY8C24423A PSoC

Orig. of Change

Submission

Date

Description of Change

chapter.

Solder Reflow Peak T emperature table. Clean up pinouts and fine tune wording and format throughout.

packages. Update Transmitter and Receiver AC Digital Block Electrical Specifications. Re-add ISSP pinout identifier. Delete Electrical Specification sentence re: devices running at greater than 12 MHz. Update Solder Reflow Peak Temperature table. Fix CY.com URLs. Update CY copyright.

dimensions and rev. *A. Add ISSP note to pinout tables. Update typical and recommended Storage T emperature per industrial specs. Add OCD non-production pinout and package diagram. Update CY branding and QFN convention. Update package diagram revisions.

Tool section. Add CY8C20x34 to PSoC Device Characteristics table.

CY8C24423A-24LTXIT

Programmable System-on-Chip™” Updated package diagram 001-30999 to *A. Added note on digital signaling in DC Analog Reference Specifications on page 28. Added Die Sales information note to Ordering Information on page 54.

Document Number: 38-12028 Rev. *I Page 55 of 56

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Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office closest to you, visit us at cypress.com/sales.

Products

PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com

PSoC Solutions

General psoc.cypress.com/solutions Low Power/Low Voltage psoc.cypress.com/low-power Precision Analog psoc.cypress.com/precision-analog LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb

© Cypress Semiconductor Corporation, 2004- 2008. The infor mation cont ain ed herein is subj ect to change wi thout notice. C ypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor inte nd ed to be us ed for medical, life support, life saving, critica l contr o l or safety applications, unless pursuant to an express wr itten agreement with Cypress. Furthermore, Cypress does not auth ori ze i t s products for use as critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the us er . The inclu sion of Cypress p roducts in life -support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby gr ant s to l icense e a pers onal, no n-exclu sive , non-tr ansfer able license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction wit h a Cypress integrated circuit as specified in the ap plicable agreem ent. Any reprod uction, modificatio n, translation, co mpilation, or repr esentation of this Source Co de except as speci fied above is pro hibited with out the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the applic ation or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot author ize its p roducts fo r use as critical compon ents in life-su pport systems whe re a malfunction or failure may reason ably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-12028 Rev. *I Revised December 11, 2008 Page 56 of 56

PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered t rade mark of Cypress S em ic on duct or C orp. A ll other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.

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Cypress Semiconductor CY8C24123A, CY8C24223A, CY8C24423A Specification Sheet

Specifications and Main Features

Frequently Asked Questions

User Manual