Cypress Semiconductor CY8C24094, CY8C24794, CY8C24894, CY8C24994 User manual

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CY8C24094, CY8C24794 CY8C24894, CY8C24994

PSoC® Programmable System-on-Chip

1. Features

DIGITAL SYSTEM

SRAM

Interrupt

Controller

Sleep and W atchdog

C lock S ources

(Includes IM O and ILO )

Global Digital Interconnect

Global Analog Interconnect

PSoC CO RE

CPU Core (M8C)

SROM Flash 16K

Digital

Block A rray

Digital

Clocks

SYSTEM RESO URCES

ANALOG SYSTEM

Analog

Ref.

Port 5 Port 4 Port 3 Port 2 Port 1 Port 0

Analog Drivers

Analog

Block Array

In te rn a l Voltage

Ref.

PO R and LV D

System Resets

MACs

Decimator

Type 2

I2 C USB

Port 7

Analog

Input

Muxing

Logic Block Diagram

■ XRES Pin to Support In-System Serial Programming (ISSP)

and External Reset Control in CY8C24894

■ Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 24 MHz

❐ Two 8x8 Multiply , 32-Bit Accumulate ❐ Low Power at High Speed ❐ 3V to 5.25V Operating Voltage ❐ Industrial Temperature Range: -40°C to +85°C ❐ USB T emperature Range: -10°C to +85°C

■ Advanced Peripherals (PSoC ❐ 6 Rail-to-Rail Analog PSoC Blocks Provide:

• Up to 14-Bit ADCs

• Up to 9-Bit DACs

• Programmable Gain Amplifiers

• Programmable Filters and Comparators

❐ Four Digital PSoC Blocks Provide:

• 8 to 32-Bit Timers, Counters, and PWMs

• CRC and PRS Modules

• Full-Duplex UART

• Multiple SPI Masters or Slaves

• Connectable to all GPI/O Pins

❐ Complex Peripherals by Combining Blocks ❐ Capacitive Sensing Application Capability

Blocks)

■ Full Speed USB (12 Mbps) ❐ Four Uni-Directional Endpoints ❐ One Bi-Directional Control Endpoint

❐ USB 2.0 Compliant ❐ Dedicated 256 Byte Buffer ❐ No External Crystal Required

■ Flexible On-Chip Memory ❐ 16K Flash Program Storage 50,000 Erase and Write Cycles

❐ 1K SRAM Data Storage ❐ In-System Serial Programming (ISSP) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash

■ Programmable Pin Configurations ❐ 25 mA Sink, 10 mA Source on all GPIO ❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive

Modes on all GPI/O

❐ Up to 48 Analog Inputs on GPI/O ❐ Two 33 mA Analog Outputs on GPI/O ❐ Configurable Interrupt on all GPI/O

■ Precision, Programmable Clocking ❐ Internal ±4% 24 and 48 MHz Oscillator

❐ Internal Oscillator for Watchdog and Sleep ❐ 0.25% Accuracy for USB with no External Components

■ Additional System Resources

❐ I

C Slave, Master, and Multi-Master to 400 kHz

❐ Watchdog and Sleep Timers ❐ User Configurable Low Voltage Detection

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-12018 Rev. *S Revised January 12, 2010

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2. Contents

PSoC Functional Overview ................................................3

The PSoC Core .............................................................3

The Digital System ........................................................3

The Analog System .......................................................4

Additional System Resources .......................................5

PSoC Device Characteristics ........................................5

Getting Started ........................................ ... .........................5

Application Notes ..........................................................5

Development Kits .................................... ......................5

Training .........................................................................5

CyPros Consultants .......................................................5

Solutions Library ............................................................5

Technical Support .........................................................5

Development Tools ............................................................6

PSoC Designer Software Subsystems ..........................6

In-Circuit Emulator .........................................................6

Designing with PSoC Designer .........................................7

Select Components .......................................................7

Configure Components .................................................7

Organize and Connect ..................................................7

Generate, Verify, and Debug .........................................7

Document Conventions ..................................... .. ..............8

Acronyms Used .............................................................8

Units of Measure ................................................ ...........8

Numeric Naming ............................................................8

Pin Information ...................................................................9

56-Pin Part Pinout ........................................................9

56-Pin Part Pinout (with XRES) ..................................10

68-Pin Part Pinout .......................................................11

68-Pin Part Pinout (On-Chip Debug) ...........................12

100-Ball VFBGA Part Pinout .......................................13

100-Ball VFBGA Part Pinout (On-Chip Debug) ...........14

100-Pin Part Pinout (On-Chip Debug) .........................16

Electrical Specifications 21

Absolute Maximum Ratings .........................................22

Operating Temperature ...............................................22

DC Electrical Characteristics .......................................23

AC Electrical Characteristics .......................................31

Packaging Dimensions ....................................................39

Thermal Impedance ....................................................43

Solder Reflow Peak Temperature ............................... 43

Development Tool Selection 44

Software ......................................................................44

Development Kits ........................................................44

Evaluation Tools ..........................................................44

Device Programmers ...................................................45

Accessories (Emulation and Programming) ................ 45

Ordering Information ........................................................46

Ordering Code Definitions ...........................................47

Document Number: 38-12018 Rev. *S Page 2 of 49

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3. PSoC Functional Overview

DIGITAL SYSTEM

To System Bus

Digital PSoC Block Array

To Analog

System

Row Input

Configuration

Row Output

Configuration

Row 0

DBB00 DBB01 DCB02 DCB03

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]

Global Digital

Interconnect

Port 1

Port 0

Port 3

Port 2

Port 5

Port 4

Port 7

The PSoC family consists of many programmable system-on-chips with On-Chip Controller devices. All PSoC family devices are designed to replace traditional MCUs, system ICs, and the numerous discrete components that surround them. The PSoC CY8C24x94 devices are unique members of the

3.2 The Digital System

The Digital System is composed of four digital PSoC blocks. Each block is an 8-bit resource used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references.

Figure 3-1. Digital System Block Diagram

PSoC family because it includes a full featured, full speed (12 Mbps) USB port. Configurable analog, digital, and interconnect circuitry enable a high level of integration in a host of indu strial, consumer, and communication applications.

This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM dat a memory, and configurable I/O are included in a range of convenient pinouts and packages.

The PSoC architecture, as illustrated on the left, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources including a full speed USB port. Configurable global busing enables all the device resources to be combined into a complete custom system. The PSoC CY8C24x94 devices can have up to seven I/O ports that connect to the global digital and analog interconnects, providing access to 4 digital blocks and 6 analog blocks.

3.1 The PSoC Core

The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory , clocks, and configurable GPI/O (General Purpose I/O).

The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with up to 20 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT).

Memory encompasses 16K of Flash for program storage, 1K of SRAM for data storage, and up to 2K of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection.

The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 8% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. In USB systems, the IMO self tunes to ± 0.25% accuracy for USB communication.

PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin is also capable of generating a system interrupt on high level, low level, and change from last read.

Digital peripheral configurations include the following:

■ Full Speed USB (12 Mbps)

■ PWMs (8 to 32 bit)

■ PWMs with Dead band (8 to 24 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ UART 8 bit with selectable parity

■ SPI master and slave

■ I2C slave and multi-master

■ Cyclical Redundancy Checker/Generator (8 to 32 bit)

■ IrDA

■ Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks are connected to any GPI/O through a series of global buses that can route any signal to any pin. The buses also enable signal multiplexing and performing logic operations. This configurability frees the designs from the constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This enables you the optimum choice of system resources for your application. Family resources are shown in Table 3-1 on page 5.

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3.3 The Analog System

ACB00 ACB01

Block Array

Array In put

C on fig u r atio n

ACI1[1:0]

ASD20

ACI0[1:0]

P0[6]

P0[4]

P0[2] P0[0]

P2[2] P2[0]

P2[6]

P2[4]

RefIn

AGNDIn

P0[7]

P0[5]

P0[3] P0[1]

P2[3]

P2[1]

Reference

Generators

AGNDIn R efIn Bandgap

RefHi RefLo

AGND

ASD11

ASC21

ASC10

Interface to

Digital System

M8C Interface (Address Bus, Data Bus, Etc.)

Analog Reference

A ll IO

(Except Port 7)

Analog

Mux Bus

The Analog System is composed of 6 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are as follows.

■ Analog-to-digital converters (up to 2, with 6 to 14-bit resolution,

selectable as Incremental, Delta Sigma, and SAR)

■ Filters (2 and 4 pole band-pass, low-pass, and notch)

■ Amplifiers (up to 2, with selectable gain to 48x)

■ Instrumentation amplifiers (1 with selectable gain to 93x)

■ Comparators (up to 2, with 16 selectable thresholds)

■ DACs (up to 2, with 6- to 9-bit resolution)

■ Multiplying DACs (up to 2, with 6- to 9-bit resolution)

■ High current output drivers (two with 30 mA drive as a PSoC

Core Resource)

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

■ Modulators

■ Correlators

■ Peak Detectors

■ Many other topologies possible

Analog blocks are arranged in a column of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in Figure 3-2.

Figure 3-2. Analog System Block Diagram

3.3.1 The Analog Multiplexer System

The Analog Mux Bus can connect to every GPI/O pin in ports 0-5. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. It is split into two sections for simultaneous dual-channel processing. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array.

Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include:

■ Track pad, finger sensing.

■ Chip-wide mux that enables analog input from up to 48 I/O pins.

■ Crosspoint connection between any I/O pin combinations.

When designing capacitive sensing applications, refer to the latest signal-to-noise signal level requirements Application Notes, which are found under http://www.cypress.com > Design Resources > Application Notes. In general, and unless otherwise noted in the relevant Application Notes, the minimum signal-to-noise ratio (SNR) for CapSense applications is 5:1.

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3.4 Additional System Resources

System Resources, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, low voltage detection, and power on reset. Brief statements describing the merits of each resource follow.

■ Full Speed USB (12 Mbps) with 5 configurable endpoints and

256 bytes of RAM. No external components required except two series resistors. Wider than comm ercial temperature USB operation (-10°C to +85°C).

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks are generated using digital PSoC blocks as clock dividers.

■ Two multiply accumulates (MACs) provide fast 8-bit multipliers

with 32-bit accumulate, to assist in both general math and digital filters.

■ Decimator provides a custom hard ware filter for digital signal

processing applications including creation of Delta Sigma ADCs.

■ The I2C module provides 100 and 400 kHz communication over

two wires. Slave, master, multi-master are supported.

■ Low Voltage Detection (LVD) interrupts signal the application

of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3V reference provides an absolute reference for

the analog system, including ADCs and DACs.

■ Versatile analog multiplexer system.

3.5 PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups. The device covered by this data sheet is shown in the highlighted row of the table

Table 3-1. PSoC Device Characteristics

PSoC Part

Number

CY8C29x66 up to 644 16 12 4 4 12 2K 32K

CY8C27x43 up to 442 8 12 4 4 12 256

CY8C24x94 56 1 4 48 2 2 6 1K 16K CY8C24x23A up to 241 4 12 2 2 6 256

CY8C21x34 up to 281 4 28 0 2 4 512

CY8C21x23

CY8C20x34

I/O

Digital

16 1 4 8 0 2 4 256

up to 280 0 28 0 0 3 512

Rows

Digital

Blocks

Analog

Inputs

Analog

Outputs

Analog

Blocks

Analog

Columns

Bytes

Size

SRAM

Flash

16K

4. Getting Started

The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications.

For in depth information, along with detailed programming information, see the PSoC® Technical Reference Manual for CY8C24x94 PSoC devices.

For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at www.cypress.com/psoc.

4.1 Application Notes

Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here:

www.cypress.com/psoc. Select Application Notes under the

Documentation tab.

4.2 Development Kits

PSoC Development Kits are available online from Cypress at

www.cypress.com/shop and through a growing number of

regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark.

4.3 Training

Free PSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs.

4.4 CyPros Consultants

Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros.

4.5 Solutions Library

Visit our growing library of solution focused designs at

www.cypress.com/solutions. Here you can find various appli-

cation designs that include firmware and hardware design files that enable you to complete your designs quickly.

Size

4.6 Technical Support

For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736.

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5. Development Tools

PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista.

This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers.

PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family.

5.1 PSoC Designer Software Subsystems

5.1.1 System-Level View

A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. Y ou define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC Mixed-Signal Controllers that match your system requirements.

PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device.

5.1.2 Chip-Level View

The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.4. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application.

The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration enables changing configurations at run time.

5.1.3 Hybrid Designs

You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder , and common debug, emulation, and programming tools.

5.1.4 Code Generation Tools

PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours.

Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute a ddr e ssing .

C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices.

The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.

5.1.5 Debugger

The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear b reakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.

5.1.6 Online Help System

The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.

5.2 In-Circuit Emulator

A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices.

The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device fami ly are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.

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6. Designing with PSoC Designer

The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions.

The PSoC development process can be summarized in the following four steps:

1. Select components

2. Configure components

3. Organize and Connect

4. Generate, Verify, and Debug

6.1 Select Components

Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called “drivers” and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces

C-bus, for example), and the logic to control how they interact

with one another (called valuators). In the chip-level view, the components are called “user modules”.

User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties.

6.2 Configure Components

Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus.

Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design.

6.3 Organize and Connect

You can build signa l chains at the chip level by interconnecting user modules to each other and the I/O pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions.

In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer’s outp ut to a digital signal, and a PWM to control the fan.

In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources.

6.4 Generate, Verify, and Debug

When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system.

Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code.

A complete code development environment allows you to develop and customize your applications in C, assembly language, or both.

The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the ICE where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.

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7. Document Conventions

7.1 Acronyms Used

The following table lists the acronyms that are used in this document.

Acronym Description

AC alternating current ADC analog-to-digital converter API application programming interface CPU central processing unit CT continuous time DAC digital-to-analog converter DC direct current ECO external crystal oscillator EEPROM electrically erasable programmable read-only

memory FSR full scale range GPI/O general purpose I/O GUI graphical user interface HBM human body model ICE in-circuit emulator ILO internal low speed oscillator IMO internal main oscillator I/O input/output IPOR imprecise power on reset LSb least-significant bit LVD low voltage detect MSb most-significant bit PC program counter PLL phase-locked loop POR power on reset PPOR precision power on reset PSoC® Programmable System-on-Chip™ PWM pulse width modulator SC switched capacitor SRAM static random access memory

7.2 Units of Measure

A units of measure table is located in the Electrical Specifications section. Table 10-1 on page 21 lists all the abbreviations used to measure the PSoC devices.

7.3 Numeric Naming

Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.

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8. Pin Information

Note

1. This part cannot be programmed with Reset mode; use Power Cycle mode when programming.

QFN

(Top View )

A, I, M, P2[3] A, I, M, P2[1]

M, P4[7] M, P4[5] M, P4[3] M, P4[1] M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[7] M, P5[5] M, P5[3] M, P5[1]

1 2 3 4 5 6 7 8 9

10 11 12 13 14

M, I2C SCL, P1[7]

M, I2C SDA, P1[5]

M, P1[3]

M, I2C SCL, P1[1]

Vss

D+

D-

Vdd

P7[7]

P7[0]

M, I2C SDA, P1[0]

M, P1[2]

M, P1[4]

M, P1[6]

15161718192021

2324252627

P2[4], M

P2[6], M

P0[0], A, I, M

P0[2], A, I, M

P0[4], A, I, M

P0[6], A, I, M

Vdd

Vss

P0[7], A, I, M

P0[5], A, IO, M

P0[3], A, IO, M

P0[1], A, I, M

P2[7], M

P2[5], M

P2[2], A, I, M P2[0], A, I, M P4[6], M P4[4], M P4[2], M P4[0], M P3[6], M P3[4], M

P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M

41 40

39 38 37 36

34 33 32 31 30 29

EXTCLK,

This section describes, lists, and illustrates the CY8C24x94 PSoC device family pins and pinout configuration. The CY8C24x94 PSoC devices are available in the following packages, all of which are shown on the following pages. Every port pin

(labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.

8.1 56-Pin Part Pinout

Table 8-1. 56-Pin Part Pinout (QFN

Pin No.

Type

Digital Analog

Name Description

[3]

) See LEGEND details and footnotes in Tab le 8-2 on page 10.

Figure 8-1. CY8C24794 56-Pin PSoC Device

1 I/O I, M P2[3] Direct switched capacitor block input. 2 I/O I, M P2[1] Direct switched capacitor block input. 3 I/O M P4[7] 4 I/O M P4[5] 5 I/O M P4[3] 6 I/O M P4[1] 7 I/O M P3[7] 8 I/O M P3[5] 9 I/O M P3[3]

10 I/O M P3[1] 11 I/O M P5[7] 12 I/O M P5[5] 13 I/O M P5[3] 14 I/O M P5[1] 15 I/O M P1[7] I2C Serial Clock (SCL). 16 I/O M P1[5] I2C Serial Data (SDA). 17 I/O M P1[3] 18 I/O M P1[1] I2C Serial Clock (SCL), ISSP SCLK

[2]

. 19 Power Vss Ground connection. 20 USB D+ 21 USB D22 Power Vdd Supply voltage. 23 I/O P7[7] 24 I/O P7[0] 25 I/O M P1[0] I2C Serial Data (SDA), ISSP SDATA

[2]

. 26 I/O M P1[2] 27 I/O M P1[4] Optional External Clock Input (EXTCLK). 28 I/O M P1[6] 29 I/O M P5[0]

30 I/O M P5[2]

Pin No.

Type

Digital Analog

Name Description

31 I/O M P5[4] 44 I/O M P2[6] External Voltage Reference (VREF) i nput. 32 I/O M P5[6] 45 I/O I, M P0[0] Analog column mux input. 33 I/O M P3[0] 46 I/O I, M P0[2] Analog column mux input. 34 I/O M P3[2] 47 I/O I, M P0[4] Analog column mux input VREF. 35 I/O M P3[4] 48 I/O I, M P0[6] Analog column mux input. 36 I/O M P3[6] 49 Power Vdd Supply voltage. 37 I/O M P4[0] 50 Power Vss Ground connection. 38 I/O M P4[2] 51 I/O I, M P0[7] Analog column mux input,. 39 I/O M P4[4] 52 I/O I/O, M P0[5] Analog column mux input and column output. 40 I/O M P4[6] 53 I/O I/O, M P0[3] Analog column mux input and column output. 41 I/O I, M P2[0] Direct switched capacitor block input. 54 I/O I, M P0[1] Analog column mux input. 42 I/O I, M P2[2] Direct switched capacitor block input. 55 I/O M P2[7] 43 I/O M P2[4] External Analog Ground (AGND) input. 56 I/O MP2[5]

[1]

Document Number: 38-12018 Rev. *S Page 9 of 49

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CY8C24094, CY8C24794 CY8C24894, CY8C24994

8.2 56-Pin Part Pinout (with XRES)

QFN

(Top View)

A, I, M, P2 [3] A, I, M, P2 [1]

M, P 4[ 7] M, P 4[ 5] M, P 4[ 3] M, P 4[ 1] M, P 3[ 7] M, P 3[ 5] M, P 3[ 3] M, P 3[ 1] M, P 5[ 7] M, P 5[ 5] M, P 5[ 3] M, P 5[ 1]

1 2

4 5 6

7 8 9 10 11 12 13 14

M, I2C SCL, P1[7]

M, I2C SDA, P1[5]

M, P1[3]

M, I2C SCL, P1[1]

Vss

D+

D-

Vdd

P7[7]

P7[0]

M, I2C SDA, P1[0 ]

M, P1[2]

M, P1[4]

M, P1[6]

15161718192021

2324252627

P2[4 ], M

P2[6], M

P0[0], A , I, M

P0[2], A , I, M

P0[4], A , I, M

P0[6], A, I, M

Vdd

Vss

P0[7], A, I, M

P0[5 ], A, IO, M

P0[3], A, IO, M

P0[1], A, I, M

P2[7], M

P2[5 ], M

P2[2 ], A, I, M P2[0 ], A, I, M P4[6], M P4[4], M P4[2], M P4[0], M XRES P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M

41 40 39 38 37 36 35 34

33 32 31 30 29

EXTCLK,

Notes

2. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details.

3. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electr ical performance. If not connected to ground, it should be electrically floated and not connected to any other si gnal.

Table 8-2. 56-Pin Part Pinout (QFN

Pin No.

Type

Digital Analog

Name Description

[3]

)

1 I/O I, M P2[3] Direct switched capacitor block input. 2 I/O I, M P2[1] Direct switched capacitor block input. 3 I/O M P4[7] 4 I/O M P4[5] 5 I/O M P4[3] 6 I/O M P4[1] 7 I/O M P3[7] 8 I/O M P3[5]

9 I/O M P3[3] 10 I/O M P3[1] 11 I/O M P5[7] 12 I/O M P5[5] 13 I/O M P5[3] 14 I/O M P5[1] 15 I/O M P1[7] I2C Serial Clock (SCL). 16 I/O M P1[5] I2C Serial Data (SDA). 17 I/O M P1[3] 18 I/O M P1[1] I2C Serial Clock (SCL), ISSP SCLK 19 Power Vss Ground connection. 20 USB D+ 21 USB D22 Power Vdd Supply voltage. 23 I/O P7[7] 24 I/O P7[0] 25 I/O M P1[0] I2C Serial Data (SDA), ISSP SDATA 26 I/O M P1[2] 27 I/O M P1[4] Optional External Clock Input (EXTCLK). 28 I/O M P1[6]

Figure 8-2. CY8C24894 56-Pin PSoC Device

[2].

[2]

29 I/O M P5[0] 30 I/O M P5[2]

Pin No.

Type

Digital Analog

Name Description

pull down.

49 Power Vdd Supply voltage.

37 I/O M P4[0] 50 Power Vss Ground connection. 38 I/O M P4[2] 51 I/O I, M P0[7] Analog column mux input,. 39 I/O M P4[4] 52 I/O I/O, M P0[5] Analog column mux input and column output. 40 I/O M P4[6] 53 I/O I/O, M P0[3] Analog column mux input and column output. 41 I/O I, M P2[0] Direct switched capacitor block input. 54 I/O I, M P0[1] Analog column mux input. 42 I/O I, M P2[2] Direct switched capacitor block input. 55 I/O M P2[7] 43 I/O M P2[4] External Analog Ground (AGND) input. 56 I/O MP2[5]

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

Document Number: 38-12018 Rev. *S Page 10 of 49

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CY8C24094, CY8C24794 CY8C24894, CY8C24994

8.3 68-Pin Part Pinout

P2[6], M, Ext. VREF

P2[4], M, Ext. AGND

M, P4[7] M, P4[5] M, P4[3] M, P4[1]

NC NC

Vss M, P3[7] M, P3[5]

M, P3[3] M, P3[1] M, P5[7]

M, P5[5] M, P5[3] M, P5[1]

I2C SCL, M, P1[7]

I2C SDA, M, P1[5]

M, P1[3]

P7[5]

I2C SDA, M, P1[0]

I2C SCL, M, P1[1]

Vss

D +

D -

Vdd

P7[6]

P7[4]

P7[3]

P7[2]

P7[1]

P7[0]

M, P1[2]

P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M

XRES

NC NC

P3[6], M P3[4], M P3[2], M P3[0], M

P5[6], M P5[4], M P5[2], M

P5[0], M P1[6], M

P2[1], M, AI

P2[3], M, AI

P2[5], M

P2[7], M

P0[1], M, AI

P0[3], M, AIO

P0[5], M, AIO

P0[7], M, AI

Vss

Vdd

P0[6], M, AI

P0[4], M, AI

P0[2], M, AI

P0[0], M, AI

P2[2], M, AI

51 50

49 48 47 46 45 44 43 42 41 40 39

38 37 36 35

6867666564636261605958575655545352

10 11 12

13 14 15 16 17

1 2 3 4 5 6 7 8 9

1819202122232425262728293031323334

QFN

(Top View)

M, P1[4]

EXTCLK,

P7[7]

The following 68-pin QFN part table and drawing is for the CY8C24994 PSoC device.

Table 8-3. 68-Pin Part Pinout (QFN

[3]

)

Pin No.

Digital Analog

Type

Name Description

Figure 8-3. CY8C24994 68-Pin PSoC Device

1 I/O M P4[7] 2 I/O M P4[5] 3 I/O MP4[3] 4 I/O MP4[1] 5 NC No connection. 6 NC No connection. 7 Power Vss Ground connection. 8 I/O M P3[7] 9 I/O M P3[5] 10 I/O MP3[3] 11 I/O MP3[1] 12 I/O M P5[7] 13 I/O M P5[5] 14 I/O MP5[3] 15 I/O MP5[1] 16 I/O M P1[7] I2C Serial Cl ock (SCL ). 17 I/O M P1[5] I2C Serial Data (SDA). 18 I/O M P1[3] 19 I/O M P1[1] I2C Serial Clock (SCL) ISSP SCLK

[2]

. 20 Power Vss Ground connection. 21 USB D+ 22 USB D23 Power Vdd Supply voltage. 24 I/O P7[7] 25 I/O P7[6] 26 I/O P7[5] 27 I/O P7[4] 28 I/O P7[3] 29 I/O P7[2] 30 I/O P7[1] Digital Analog 31 I/O P7[0] 50 I/O M P4[6] 32 I/O M P1[0] I2C Seri al Da ta (SDA), ISSP SDATA

Pin No.

[2]

.51I/O I,M P2[0] Direct switched capacitor block input.

Type

Name Description

33 I/O M P1[2] 52 I/O I,M P2[2] Direct switched capacitor bl ock input. 34 I/O M P1[4] Optional External Clock Input (EXTCLK). 53 I/O M P2[4] External Analog Ground (AGND) input. 35 I/O M P1[6] 54 I/O M P2[6] External Voltage Reference (VREF) input. 36 I/O M P5[0] 55 I/O I,M P0[0] Analog column mux input. 37 I/O M P5[2] 56 I/O I,M P0[2] Analog column mux input and column output. 38 I/O M P5[4] 57 I/O I,M P0[4] Analog column mux input and column output. 39 I/O M P5[6] 58 I/O I,M P0[6] Analog column mux input. 40 I/O M P3[0] 59 Power Vdd Supply voltage. 41 I/O M P3[2] 60 Power Vss Ground connection. 42 I/O M P3[4] 61 I/O I,M P0[7] Analog column mux input, integration input #1 43 I/O M P3[6] 62 I/O I/O,M P0[5] Analog column mux input and column output, integration

44 45 46

Input XRES Active high pin reset with internal pull

47 I/O M P4[0] 66 I/O M P2[5] 48 I/O M P4[2] 67 I/O I,M P2[3] Direct switched capacitor block input.

I/O M P4[4] 68 I/O I,M P2[1] Direct switched capacitor block input.

49 LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.

NC No connection. 63 I/O I/O,M P0[3] Analog column mux input and column output. NC No connection. 64 I/O I,M P0[1] Analog column mux input.

down.

65 I/O M P2[7]

input #2.

Document Number: 38-12018 Rev. *S Page 11 of 49

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CY8C24094, CY8C24794 CY8C24894, CY8C24994

8.4 68-Pin Part Pinout (On-Chip Debug)

M, P4[7] M, P4[5] M, P4[3]

M, P4[1]

OCDE OCDO

Vss

M, P3[7] M, P3[5] M, P3[3]

M, P3[1] M, P5[7] M, P5[5]

M, P5[3] M, P5[1]

I2C SCL, M, P1[7]

I2C SDA, M, P1[5]

M, P1[3]

P7[5]

I2C SDA, M, P1[0]

I2C SCL, M, P1[1]

Vss

D +

D -

Vdd

P7[7]

P7[6]

P7[4]

P7[3]

P7[2]

P7[1]

P7[0]

M, P1[2]

M, P1[4]

P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M

XRES CCLK HCLK

P3[6], M P3[4], M P3[2], M P3[0], M

P5[6], M P5[4], M P5[2], M P5[0], M P1[6], M

P2[1], M, AI

P2[3], M, AI

P2[5], M

P2[7], M

P0[1], M, AI

P0[3], M, AIO

P0[5], M, AIO

P0[7], M, AI

Vss

Vdd

P0[6], M, AI

P0[4], M, AI

P0[2], M, AI

P0[0], M, AI

P2[6], M, Ext. VREF

P2[4], M, Ext. AGND

P2[2], M, AI

51 50

49 48 47

46 45 44

43 42 41 40 39 38 37 36 35

6867666564636261605958575655545352

10 11 12 13 14 15 16 17

1 2 3 4 5 6 7 8 9

1819202122232425262728293031323334

QFN

(Top View)

EXTCLK

The following 68-pin QFN part table and drawing is for the CY8C24094 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production. Table 8-4. 68-Pin Part Pinout (QFN

[3]

)

Pin No.

Digital Analog

Type

Name Description

Figure 8-4. CY8C24094 68-Pin OCD PSoC Device

1 I/O M P4[7] 2 I/O M P4[5] 3 I/O MP4[3] 4 I/O MP4[1] 5 OCDE OCD even data I/O. 6 OCDO OCD odd data output. 7 Power Vss Ground connection. 8 I/O M P3[7] 9 I/O M P3[5] 10 I/O MP3[3] 11 I/O MP3[1] 12 I/O M P5[7] 13 I/O M P5[5] 14 I/O MP5[3] 15 I/O MP5[1] 16 I/O M P1[7] I2C Serial Clock (SCL). 17 I/O M P1[5] I2C Serial Data (SDA). 18 I/O M P1[3] 19 I/O M P1[1] I2C Serial Clock (SCL), ISSP SCLK

[2]

Pin No.

[2]

.51I/O I,M P2[0] Direct switched capacitor block input.

Type

Name Description

33 I/O M P1[2] 52 I/O I,M P2[2] Direct switched capacitor block input. 34 I/O M P1[4] Optional External Clock Input (EXTCLK). 53 I/O M P2[4] External Analog Ground (AGND) input. 35 I/O M P1[6] 54 I/O M P2[6] External Voltage Reference (VREF) input. 36 I/O M P5[0] 55 I/O I,M P0[0] Analog column mux input. 37 I/O M P5[2] 56 I/O I,M P0[2] Analog column mux input and column output. 38 I/O M P5[4] 57 I/O I,M P0[4] Analog column mux input and column output. 39 I/O M P5[6] 58 I/O I,M P0[6] Analog column mux input. 40 I/O M P3[0] 59 Power Vdd Supply voltage. 41 I/O M P3[2] 60 Power Vss Ground connection. 42 I/O M P3[4] 61 I/O I,M P0[7] Analog column mux input, integration input #1 43 I/O M P3[6] 62 I/O I/O,M P0[5] Analog column mux input and column output,

44 45 46

47 I/O M P4[0] 66 I/O M P2[5] 48 I/O M P4[2] 67 I/O I,M P2[3] Direct switched capacitor block input. 49 LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, OCD = On-Chip Debugger.

Input XRES Active high pin reset with internal pull

I/O M P4[4] 68 I/O I,M P2[1] Direct switched capacitor block input.

HCLK OCD high speed clock output. 63 I/O I/O,M P0[3] Analog column mux input and column output. CCLK OCD CPU clock output. 64 I/O I,M P0[1] Analog column mux input.

down.

integration input #2.

65 I/O M P2[7]

Document Number: 38-12018 Rev. *S Page 12 of 49

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8.5 100-Ball VFBGA Part Pinout

The 100-ball VFBGA part is for the CY8C24994 PSoC device.

Table 8-5. 100-Ball Part Pinout (VFBGA)

Pin No.

Digital

A1 Power Vss Ground connection. F1 NC No connection. A2 Power Vss Ground connection. F2 I/O M P5[7] A3 NC No connection. F3 I/O M P3[5] A4 NC No connection. F4 I/O M P5[1] A5 NC No connection. F5 Power Vss Ground connection. A6 Power Vdd Supply voltage. F6 Power Vss Ground connection. A7 NC No connection. F7 I/O M P5[0] A8 NC No connection. F8 I/O M P3[0] A9 Power Vss Ground connection. F9 XRES Active high pin reset with internal pull down. A10 Power Vss Ground connection. F10 I/O P7[1] B1 Power Vss Ground connection. G1 NC No connection. B2 Power Vss Ground connection. G2 I/O M P5[5] B3 I/O I,M P2[1] Direct switched capacitor block input. G3 I/O M P3[3] B4 I/O I,M P0[1] Analog column mux input. G4 I/O M P1[7] I2C Serial Clock (SCL). B5 I/O I,M P0[7] Analog column mux input. G5 I/O M P1[1] I2C Serial Clock (SCL), ISSP SCLK B6 Power Vdd Supply voltage. G6 I/O M P1[0] I2C Serial Data (SDA), ISSP SDATA B7 I/O I,M P0[2] Analog column mux input. G7 I/O M P1[6] B8 I/O I,M P2[2] Direct switched capacitor block input. G8 I/O M P3[4] B9 Power Vss Ground connection. G9 I/O M P5[6] B10 Power Vss Ground connection. G10 I/O P7[2] C1 NC No connection. H1 NC No connection. C2 I/O MP4[1] H2 I/O M P5[3] C3 I/O MP4[7] H3 I/O M P3[1] C4 I/O M P2[7] H4 I/O M P1[5] I2C Serial Data (SDA). C5 I/O I/O,M P0[5] Analog column mux input and column output. H5 I/O M P1[3] C6 I/O I,M P0[6] Analog column mux input. H6 I/O M P1[2] C7 I/O I,M P0[0] Analog column mux input. H7 I/O M P1[4] Optional External Clock Input (EXTCLK). C8 I/O I,M P2[0] Direct switched capacitor block input. H8 I/O M P3[2] C9 I/O MP4[2] H9 I/O M P5[4] C10 NC No connection. H10 I/O P7[3] D1 NC No connection. J1 Power Vss Ground connection. D2 I/O MP3[7] J2 Power Vss Ground connection. D3 I/O MP4[5] J3 USB D+ D4 I/O M P2[5] J4 USB DD5 I/O I/O,M P0[3] Analog column mux input and column output. J5 Power Vdd Supply voltage. D6 I/O I,M P0[4] Analog column mux input. J6 I/O P7[7] D7 I/O M P2[6] External Voltage Reference (VREF) input. J7 I/O P7[0] D8 I/O M P4[6] J8 I/O M P5[2] D9 I/O M P4[0] J9 Power Vss Ground connection. D10 NC No connection. J10 Power Vss Ground connection. E1 NC No connection. K1 Power Vss Ground connection. E2 NC No connection. K2 Power Vss Ground connection. E3 I/O MP4[3] K3 NC No connection. E4 I/O I,M P2[3] Direct switched capacitor block input. K4 NC No connection. E5 Power Vss Ground connection. K5 Power Vdd Supply voltage. E6 Power Vss Ground connection. K6 I/O P7[6] E7 I/O M P2[4] External Analog Ground (AGND) input. K7 I/O P7[5] E8 I/O M P4[4] K8 I/O P7[4] E9 I/O M P3[6] K9 Power Vss Ground connection. E10 NC No connection. K10 Power Vss Ground connection.

Name Description

Analog

Pin No.

Name Description

Digital

Analog

[2]

LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection.

Document Number: 38-12018 Rev. *S Page 13 of 49

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CY8C24094, CY8C24794 CY8C24894, CY8C24994

Figure 8-5. CY8C24094 OCD (Not for Production)

Vss Vss NC NC NC Vdd NC NC Vss Vss

Vss Vss P2[1] P0[1] P0[7] Vdd P0[2] P2[2] Vss Vss

NC P4[1] P4[7] P2[7] P0[5] P0[6] P0[0] P2[0] P4[2] NC

NC P3[7] P4[5] P2[5] P0[3] P0[4] P2[6] P4[6] P4[0] NC

NC NC P4[3] P2[3] Vss Vss P2[4] P4[4] P3[6] NC

NC P5[7] P3[5] P5[1] Vss Vss P5[0] P3[0] XRES P7[1]

NC P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2]

NC P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3]

Vss Vss D + D - Vdd P7[7] P7[0] P5[2] Vss Vss

Vss Vss NC NC Vdd P7[6] P7[5] P7[4] Vss Vss

12345678910

A B C D E F G H

BGA (Top View)

8.6 100-Ball VFBGA Part Pinout (On-Chip Debug)

The following 100-pin VFBGA part table and drawing is for the CY8C24094 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production. Table 8-6. 100-Ball Part Pinout (VFBGA)

Pin No.

Digital

A1 Power Vss Ground connection. F1 OCDE OCD even data I/O. A2 Power Vss Ground connection. F2 I/O M P5[7] A3 NC No connection. F3 I/O M P3[5] A4 NC No connection. F4 I/O M P5[1] A5 NC No connection. F5 Power Vss Ground connection. A6 Power Vdd Supply voltage. F6 Power Vss Ground connection. A7 NC No connection. F7 I/O M P5[0] A8 NC No connection. F8 I/O M P3[0] A9 Power Vss Ground connection. F9 XRES Active high pin reset with internal pull down. A10 Power Vss Ground connection. F10 I/O P7[1] B1 Power Vss Ground connection. G1 OCDO OCD odd data output. B2 Power Vss Ground connection. G2 I/O M P5[5] B3 I/O I,M P2[1] Direct switched capacitor block input. G3 I/O M P3[3] B4 I/O I,M P0[1] Analog column mux input. G4 I/O M P1[7] I2C Serial Clock (SCL). B5 I/O I,M P0[7] Analog column mux input. G5 I/O M P1[1] I2C Serial Clock (SCL), ISSP SCLK B6 Power Vdd Supply voltage. G6 I/O M P1[0] I2C Serial Data (SDA), ISSP SDATA B7 I/O I,M P0[2] Analog column mux input. G7 I/O M P1[6] B8 I/O I,M P2[2] Direct switched capacitor block input. G8 I/O M P3[4] B9 Power Vss Ground connection. G9 I/O M P5[6] B10 Power Vss Ground connection. G10 I/O P7[2] C1 NC No connection. H1 NC No connection. C2 I/O MP4[1] H2 I/O M P5[3] C3 I/O MP4[7] H3 I/O M P3[1] C4 I/O M P2[7] H4 I/O M P1[5] I2C Serial Data (SDA). C5 I/O I/O,MP0[5] Analog column mux input and column output. H5 I/O M P1[3]

C6 I/O I,M P0[6] Analog column mux inp u t. H6 I/O M P1[2] C7 I/O I,M P0[0] Analog column mux input. H7 I/O M P1[4] Optional External Clock Input (EXTCLK).

Document Number: 38-12018 Rev. *S Page 14 of 49

Name Description

Analog

Pin No.

Name Description

Digital

Analog

[2]

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CY8C24094, CY8C24794 CY8C24894, CY8C24994

Table 8-6. 100-Ball Part Pinout (VFBGA) (continued)

Vss Vss NC NC NC Vdd NC NC Vss Vss

Vss Vss P2[1] P0[1] P0[7] Vdd P0[2] P2[2] Vss Vss

NC P4[1] P4[7] P2[7] P0[5] P0[6] P0[0] P2[0] P4[2] NC

NC P3[7] P4[5] P2[5] P0[3] P0[4] P2[6] P4[6] P4[0] CClk

NC NC P4[3] P2[3] Vss Vss P2[4] P4[4] P3[6] HClk

ocde P5[7] P3[5] P5[1] Vss Vss P5[0] P3[0] XRES P7[1]

ocdo P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2]

NC P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3]

Vss Vss D + D - Vdd P7[7] P7[0] P5[2] Vss Vss

Vss Vss NC NC Vdd P7[6] P7[5] P7[4] Vss Vss

12345678910

A B C D E F G H

BGA (Top View)

Pin No.

Digital

C8 I/O I,M P2[0] Direct switched capacitor block input. H8 I/O M P3[2] C9 I/O MP4[2] H9 I/O M P5[4] C10 NC No connection. H10 I/O P7[3] D1 NC No connection. J1 Power Vss Ground connection. D2 I/O MP3[7] J2 Power Vss Ground connection. D3 I/O MP4[5] J3 USB D+ D4 I/O M P2[5] J4 USB DD5 I/O I/O,MP0[3] Analog column mux input and column output. J5 Power Vdd Supply voltage.

D6 I/O I,M P0[4] Analog column mux input. J6 I/O P7[7] D7 I/O M P2[6] External Voltage Reference (VREF) input. J7 I/O P7[0] D8 I/O M P4[6] J8 I/O M P5[2] D9 I/O M P4[0] J9 Power Vss Ground connection. D10 CCLK OCD CPU clock output. J10 Power Vss Ground connection. E1 NC No connection. K1 Power Vss Ground connection. E2 NC No connection. K2 Power Vss Ground connection. E3 I/O MP4[3] K3 NC No connection. E4 I/O I,M P2[3] Direct switched capacitor block input. K4 NC No connection. E5 Power Vss Ground connection. K5 Power Vdd Supply voltage. E6 Power Vss Ground connection. K6 I/O P7[6] E7 I/O M P2[4] External Analog Ground (AGND) input. K7 I/O P7[5] E8 I/O M P4[4] K8 I/O P7[4] E9 I/O M P3[6] K9 Power Vss Ground connection. E10 HCLK OCD high speed clock output. K10 Power Vss Ground connection.

LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection, OCD = On-Chip Debugger.

Name Description

Analog

Pin No.

Name Description

Digital

Analog

Figure 8-6. CY8C24094 OCD (Not for Production)

Document Number: 38-12018 Rev. *S Page 15 of 49

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8.7 100-Pin Part Pinout (On-Chip Debug)

The 100-pin TQFP part is for the CY8C24094 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production. Table 8-7. 100-Pin Part Pinout (TQFP)

Pin No.

1 NC No connection. 51 I/O M P1[6] 2 NC No connection. 52 I/O M P5[0] 3 I/O I, M P0[1] Analog column mux input. 53 I/O M P5[2] 4 I/O M P2[7] 54 I/O M P5[4] 5 I/O M P2[5] 55 I/O M P5[6] 6 I/O I, M P2[3] Direct switched capacitor block input. 56 I/O M P3[0] 7 I/O I, M P2[1] Direct switched capacitor block input. 57 I/O M P3[2] 8 I/O M P4[7] 58 I/O M P3[4] 9 I/O M P4[5] 59 I/O M P3[6] 10 I/O M P4[3] 60 HCLK OCD high speed clock output. 11 I/O M P4[1] 61 CCLK OCD CPU clock output. 12 OCDE OCD even data I/O. 62 Input XRES Active high pin reset with internal pull down. 13 OCDO OCD odd data output. 63 I/O M P4[0] 14 NC No connection. 64 I/O M P4[2] 15 Power Vss Ground connection. 65 Power Vss Ground connection. 16 I/O M P3[7] 66 I/O M P4[4] 17 I/O M P3[5] 67 I/O M P4[6] 18 I/O M P3[3] 68 I/O I, M P2[0] Direct switched capacitor block input. 19 I/O M P3[1] 69 I/O I, M P2[2] Direct switched capacitor block input. 20 I/O M P5[7] 70 I/O P2[4] External Analog Ground (AGND) input. 21 I/O M P5[5] 71 NC No connection. 22 I/O M P5[3] 72 I/O P2[6] External Voltage Reference (VREF) input. 23 I/O M P5[1] 73 NC No connection. 24 I/O M P1[7] I2C Serial Clock (SCL). 74 I/O I P0[0] Analog column mux input. 25 NC No connection. 75 NC No connection. 26 NC No connection. 76 NC No connection. 27 NC No connection. 77 I/O I, M P0[2] Analog column mux input and column output. 28 I/O P1[5] I2C Serial Data (SDA) 78 NC No connection. 29 I/O P1[3] 79 I/O I, M P0[4] Analog column mux input and column output. 30 I/O P1[1] Crystal (XTALin), I2C Serial Clock (SCL),

31 NC No connection. 81 I/O I, M P0[6] Analog column mux input. 32 Power Vss Ground connection. 82 Power Vdd Supply voltage. 33 USB D+ 83 NC No connection. 34 USB D- 84 Power Vss Ground connection. 35 Power Vdd Supply voltage. 85 NC No connection. 36 I/O P7[7] 86 NC No connection. 37 I/O P7[6] 87 NC No connection. 38 I/O P7[5] 88 NC No connection. 39 I/O P7[4] 89 NC No connection. 40 I/O P7[3] 90 NC No connection. 41 I/O P7[2] 91 NC No connection. 42 I/O P7[1] 92 NC No connection. 43 I/O P7[0] 93 NC No connection. 44 NC No connection. 94 NC No connection. 45 NC No connection. 95 I/O I, M P0[7] Analog column mux input. 46 NC No connection. 96 NC No connection. 47 NC No connection. 97 I/O I/O, MP0[5] Analog column mux input and column output.

48 I/O P1[0] Crystal (XTALout), I2C Serial Data (SDA), 49 I/O P1[2] 99 I/O I/O, MP0[3] Analog column mux input and column output.

Name Description

Digital

Analog

ISSP SCLK

ISSP SDATA

[2]

Pin No.

Digital

98 NC No connection.

Name Description

Analog

NC No connection.

50 I/O P1[4] Optional External Clock Input (EXTCLK). 100 NC No connection. LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input, OCD = On-Chip Debugger.

Document Number: 38-12018 Rev. *S Page 16 of 49

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Figure 8-7. CY8C24094 OCD (Not for Production)

TQFP

NC NC

AI, M, P0[1]

M, P2[7]

M, P2[5] AI, M, P2[3] AI, M, P2[1]

M, P4[7]

M, P4[5]

M, P4[3]

M, P4[1]

OCDE

OCDO

Vss M, P3[7] M, P3[5]

M, P3[3] M, P3[1]

M, P5[7] M, P5[5] M, P5[3]

M, P5[1]

I2C SC L, P1[7]

D-

P7[3]

I2C SD A, M , P1[5]

M, P1[3]

I2C SC L, M, P1[1]

Vss

D+

Vdd

P7[7]

P7[6]

P7[5]

P7[4]

P7[2]

P7[1]

P7[0]

NCNCNC

I2C SD A, M , P1[ 0]

M, P1[2]

M, P1[4]

NC P0[0], M, AI NC P2[6], M, Ex ternal VR EF NC P2[4], M, Ex ternal AGND P2[2], M, AI

P2[0], M, AI P4[6], M P4[4], M

Vss P4[2], M

P4[0], M XRES

CCLK HCLK P3[6], M P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M

P1[6], M

P0[3], M, AINCP0[5], M , AINCP0[7], M, AI

NCNCNCNCNCNCNCNCNCNCVssNCVdd

P0[6], M, AINCP0[4], M , AINCP0[2], M , AI

75 74

73 72 71

70 69 68

67 66 65 64 63 62 61 60 59 58 57 56

55 54

53 52

100

9998979695949392919089888786858483828180797877

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

1 2 3 4 5 6 7 8

26272829303132333435363738394041424344454647485049

EXTCLK,

Document Number: 38-12018 Rev. *S Page 17 of 49

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9. Register Reference

This section lists the registers of the CY8C24x94 PSoC device family. For detailed register information, reference the PSoC Programmable System-on-Chip Technical Reference Manual.

9.1 Register Conventions

The register conventions specific to this section are listed in the following table.

Convention Description

R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific

9.2 Register Mapping Tables

The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1.

Note In the following register mapping tables, blank fields are Reserved and should not be accessed.

Document Number: 38-12018 Rev. *S Page 18 of 49

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9.3 Register Map Bank 0 Table: User Space

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access

PRT0DR 00 RW PMA0_DR 40 RW ASC10CR0 80 RW C0 PRT0IE 01 RW PMA1_DR 41 RW ASC10CR1 81 RW C1 PRT0GS 02 RW PMA2_DR 42 RW ASC10CR2 82 RW C2 PRT0DM2 03 RW PMA3_DR 43 RW ASC10CR3 83 RW C3 PRT1DR 04 RW PMA4_DR 44 RW ASD11CR0 84 RW C4 PRT1IE 05 RW PMA5_DR 45 RW ASD11CR1 85 RW C5 PRT1GS 06 RW PMA6_DR 46 RW ASD11CR2 86 RW C6 PRT1DM2 07 RW PMA7_DR 47 RW ASD11CR3 87 RW C7 PRT2DR 08 RW USB_SOF0 48 R 88 C8 PRT2IE 09 RW USB_SOF1 49 R 89 C9 PRT2GS 0A RW USB_CR0 4A RW 8A CA PRT2DM2 0B RW USBI/O_CR0 4B # 8B CB PRT3DR 0C RW USBI/O_CR1 4C RW 8C CC PRT3IE 0D RW 4D 8D CD PRT3GS 0E RW EP1_CNT1 4E # 8E CE PRT3DM2 0F RW EP1_CNT 4F RW 8F CF PRT4DR 10 RW EP2_CNT1 50 # ASD20CR0 90 RW CUR_PP D0 RW PRT4IE 11 RW EP2_CNT 51 RW ASD20CR1 91 RW STK_PP D1 RW PRT4GS 12 RW EP3_CNT1 52 # ASD20CR2 92 RW D2 PRT4DM2 13 RW EP3_CNT 53 RW ASD20CR3 93 RW IDX_PP D3 RW PRT5DR 14 RW EP4_CNT1 54 # ASC21CR0 94 RW MVR_PP D4 RW PRT5IE 15 RW EP4_CNT 55 RW ASC21CR1 95 RW MVW_PP D5 RW PRT5GS 16 RW EP0_CR 56 # ASC21CR2 96 RW I2C_CFG D6 RW PRT5DM2 17 RW EP0_CNT 57 # ASC21CR3 97 RW I2C_SCR D7 #

PRT7DR 1C RW EP0_DR4 5C RW 9C INT_CLR2 DC RW PRT7IE 1D RW EP0_DR5 5D RW 9D INT_CLR3 DD RW PRT7GS 1E RW EP0_DR6 5E RW 9E INT_MSK3 DE RW PRT7DM2 1F RW EP0_DR7 5F RW 9F INT_MSK2 DF RW DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW DBB00DR1 21 W AMUXCFG 61 RW A1 INT_MSK1 E1 RW DBB00DR2 22 RW 62 A2 INT_VC E2 RC DBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 W DBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RC DBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RC DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW DCB02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 W DCB02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 W DCB02DR2 2A RW 6A MUL1_DH AA R MUL0_DH EA R DCB02CR0 2B # 6B MUL1_DL AB R MUL0_DL EB R DCB03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RW DCB03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RW DCB03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RW DCB03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RW

Blank fields are Reserved and should not be accessed. # Access is bit specific.

18 EP0_DR0 58 RW 98 I2C_DR D8 RW 19 EP0_DR1 59 RW 99 I2C_MSCR D9 # 1A EP0_DR2 5A RW 9A INT_CLR0 DA RW 1B EP0_DR3 5B RW 9B INT_CLR1 DB RW

30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F

ACB00CR3 70 RW RDI0RI B0 RW F0 ACB00CR0 71 RW RDI0SYN B1 RW F1 ACB00CR1 72 RW RDI0IS B2 RW F2 ACB00CR2 73 RW RDI0LT0 B3 RW F3 ACB01CR3 74 RW RDI0LT1 B4 RW F4 ACB01CR0 75 RW RDI0RO0 B5 RW F5 ACB01CR1 76 RW RDI0RO1 B6 RW F6 ACB01CR2 77 RW B7 CPU_F F7 RL

78 B8 F8 79 B9 F9 7A BA FA 7B BB FB 7C BC FC 7D BD DAC_D FD RW 7E BE CPU_SCR1 FE # 7F BF CPU_SCR0 FF #

Document Number: 38-12018 Rev. *S Page 19 of 49

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9.4 Register Map Bank 1 Table: Configuration Space

Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access

PRT0DM0 00 RW PMA0_WA 40 RW ASC10CR0 80 RW USBI/O_CR2 C0 RW PRT0DM1 01 RW PMA1_WA 41 RW ASC10CR1 81 RW USB_CR1 C1 # PRT0IC0 02 RW PMA2_WA 42 RW ASC10CR2 82 RW PRT0IC1 03 RW PMA3_WA 43 RW ASC10CR3 83 RW PRT1DM0 04 RW PMA4_WA 44 RW ASD11CR0 84 RW EP1_CR0 C4 # PRT1DM1 05 RW PMA5_WA 45 RW ASD11CR1 85 RW EP2_CR0 C5 # PRT1IC0 06 RW PMA6_WA 46 RW ASD11CR2 86 RW EP3_CR0 C6 # PRT1IC1 07 RW PMA7_WA 47 RW ASD11CR3 87 RW EP4_CR0 C7 # PRT2DM0 08 RW 48 88 C8 PRT2DM1 09 RW 49 89 C9 PRT2IC0 0A RW 4A 8A CA PRT2IC1 0B RW 4B 8B CB PRT3DM0 0C RW 4C 8C CC PRT3DM1 0D RW 4D 8D CD PRT3IC0 0E RW 4E 8E CE PRT3IC1 0F RW 4F 8F CF PRT4DM0 10 RW PMA0_RA 50 RW 90 GDI_O_IN D0 RW PRT4DM1 11 RW PMA1_RA 51 RW ASD20CR1 91 RW GDI_E_IN D1 RW PRT4IC0 12 RW PMA2_RA 52 RW ASD20CR2 92 RW GDI_O_OU D2 RW PRT4IC1 13 RW PMA3_RA 53 RW ASD20CR3 93 RW GDI_E_OU D3 RW PRT5DM0 14 RW PMA4_RA 54 RW ASC21CR0 94 RW D4 PRT5DM1 15 RW PMA5_RA 55 RW ASC21CR1 95 RW D5 PRT5IC0 16 RW PMA6_RA 56 RW ASC21CR2 96 RW D6 PRT5IC1 17 RW PMA7_RA 57 RW ASC21CR3 97 RW D7

PRT7DM0 1C RW 5C 9C DC PRT7DM1 1D RW 5D 9D OSC_GO_EN DD RW PRT7IC0 1E RW 5E 9E OSC_CR4 DE RW PRT7IC1 1F RW 5F 9F OSC_CR3 DF RW DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW

DBB01FN 24 RW CMP_GO_EN 64 RW A4 VLT_CMP E4 R DBB01IN 25 RW 65 A5 E5 DBB01OU 26 RW AMD_CR1 66 RW A6 E6

DCB02FN 28 RW 68 A8 IMO_TR E8 W DCB02IN 29 RW 69 A9 ILO_TR E9 W DCB02OU 2A RW 6A AA BDG_TR EA RW

DCB03FN 2C RW TMP_DR0 6C RW AC MUX_CR4 EC RW DCB03IN 2D RW TMP_DR1 6D RW AD MUX_CR5 ED RW DCB03OU 2E RW TMP_DR2 6E RW AE EE

Blank fields are Reserved and should not be accessed. # Access is bit specific.

18 58 98 MUX_CR0 D8 RW 19 59 99 MUX_CR1 D9 RW 1A 5A 9A MUX_CR2 DA RW 1B 5B 9B MUX_CR3 DB RW

23 AMD_CR0 63 RW A3 VLT_CR E3 RW

27 ALT_CR0 67 RW A7 E7

2B 6B AB ECO_TR EB W

2F TMP_DR3 6F RW AF EF 30 31 32 33 ACB00CR2 73 RW RDI0LT0 B3 RW F3 34 35 36 37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 39 3A 3B 7B BB FB 3C 3D 3E 3F 7F BF CPU_SCR0 FF #

ACB00CR3 70 RW RDI0RI B0 RW F0 ACB00CR0 71 RW RDI0SYN B1 RW F1 ACB00CR1 72 RW RDI0IS B2 RW F2

ACB01CR3 74 RW RDI0LT1 B4 RW F4 ACB01CR0 75 RW RDI0RO0 B5 RW F5 ACB01CR1 76 RW RDI0RO1 B6 RW F6

78 B8 F8 79 B9 F9 7A BA FA

7C BC FC 7D BD DAC_CR FD RW 7E BE CPU_SCR1 FE #

Document Number: 38-12018 Rev. *S Page 20 of 49

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10. Electrical Specifications

5.25

4.75

3.00

93 kHz 12 MHz 24 MHz

CPU Frequency

Vdd Voltage

This section presents the DC and AC electrical specifications of the CY8C24x94 PSoC device family. For the most up to date electrical specifications, confirm that you have the most recent data sheet by visiting http://www.cypress.com/psoc.

Specifications are valid for -40 12 MHz are valid for -40

C ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Specifications for devices running at greater than

C ≤ TA ≤ 70oC and TJ ≤ 82oC.

Figure 10-1. Voltage versus CPU Frequency

The following table lists the units of measure that are used in this chapter.

Table 10-1. Units of Measure

Symbol Unit of Measure Symbol Unit of Measure

°C degree Celsius μW microwatts dB decibels mA milli-ampere

fF femto farad ms milli-second

Hz hertz mV milli-volts

KB 1024 bytes nA nanoampere Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts

kΩ kilohm Ω ohm

MHz megahertz pA picoampere

MΩ megaohm pF picofarad

μA microampere pp peak-to-peak μF microfarad ppm parts per million

μH microhenry ps picosecond

μs microsecond sps samples per second μV microvolts σ sigma: one standard deviation

μVrms microvolts root-mean-square V volts

Document Number: 38-12018 Rev. *S Page 21 of 49

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10.1 Absolute Maximum Ratings

Table 10-2. Absolute Maximum Ratings

Symbol Description Min Typ Max Units Notes

STG

Storage Temperature -55 25 +100 °C Higher storage temperatures

reduces data retention time. Recommended storage temperature is

+25

C ± 25oC. Extended duration storage temperatures above 65 degrades reliability.

Ambient Temperature with Power Applied -40 – +85 °C Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 V V

I/O

I/O2

MI/O

MAI/O

DC Input Voltage Vss -

0.5

DC Voltage Applied to Tri-state Vss -

0.5

– Vdd +

0.5

– Vdd +

0.5

Maximum Current into any Port Pin -25 – +50 mA

Maximum Current into any Port Pin

-50 – +50 mA

Configured as Analog Driver ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD. LU Latch -u p Current – – 200 mA

10.2 Operating Temperature

Table 10-3. Operating Temperature

Symbol Description Min Typ Max Units Notes

AUSB

Ambient Temperature -40 – +85 °C

Ambient Temperature using USB -10 – +85 °C

Junction Temperature -40 – +100 °C The temperature rise from ambient to

junction is package specific. See

Thermal Impedance on page 43. The

user must limit the power consumption to comply with this requirement.

Document Number: 38-12018 Rev. *S Page 22 of 49

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10.3 DC Electrical Characteristics

10.3.1 DC Chip Level Specifications

The following table lists guaranteed maximum and min imum specificat ions fo r the voltage and temperature rang es: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and are for design guidance only.

Table 10-4. DC Chip-Level Specifications

Symbol Description Min Typ Max Units Notes

Vdd Supply Voltage 3.0 – 5.25 V See DC POR and LVD specifications,

Table 10-14 on page 29.

DD5

DD3

SBH

Supply Current, IMO = 24 MHz (5V) – 14 27 mA Conditions are Vdd = 5.0V, TA = 25 °C,

CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off.

Supply Current, IMO = 24 MHz (3.3V) – 8 14 mA Conditions are Vdd = 3.3V, TA = 25 °C,

CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz, analog power = off.

Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.

[4]

Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temper-

[4]

ature.

– 3 6.5 μA Conditions are with internal slow

speed oscillator, Vdd = 3.3V , -40

≤ 55 °C, analog power = off.

– 4 25 μA Conditions are with internal slow

speed oscillator, Vdd = 3.3V, 55

°C < TA ≤ 85 °C, analog power = off.

°C ≤

10.3.2 DC General Purpose I/O Specifications

Table 10-5. DC GPI/O Specifications

Symbol Description Min Typ Max Units Notes

Pull Up Resistor 4 5.6 8 kΩ Pull Down Resistor 4 5.6 8 kΩ High Output Level Vdd - 1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V

(8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined I

Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V

(8 total loads, 4 on even port pins (for

budget.

example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 200

mA maximum combined I

High Level Source Current 10 – – mA VOH = Vdd-1.0V , see the limitations of

the total current in the note for V

budget.

IOL Low Level Sink Current 25 – – mA VOL = 0.75V , see the limitations of the V

V V I C

IL IH H

OUT

total current in the note for V Input Low Level – – 0.8 V Vdd = 3.0 to 5.25. Input High Level 2.1 – V Vdd = 3.0 to 5.25. Input Hysterisis – 60 – mV Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA. Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent.

Temp = 25 Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dependent.

Temp = 25

Document Number: 38-12018 Rev. *S Page 23 of 49

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10.3.3 DC Full Speed USB Specifications

Note

4. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions enabled.

The following table lists guaranteed maximum and min imum specificat ions fo r the voltage and temperature rang es: 4.75V to 5.25V and -10°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

Table 10-6. DC Full Sp eed (12 Mbps) USB Specifications

Symbol Description Min Typ Max Units Notes

USB Interface V V V C I

I/O

R V

Z V

DI CM SE

EXT

UOH

UOHI

UOL

O CRS

Differential Input Sensitivity 0.2 – – V | (D+) - (D-) | Differential Input Common Mode Range 0.8 – 2.5 V Single Ended Receiver Threshold 0.8 – 2.0 V Transceiver Capacitance – – 20 pF High-Z State Data Line Leakage -10 – 10 μA0V < VIN < 3.3V. External USB Series Resistor 23 – 25 W In series with each USB pin. Static Output High, Driven 2.8 – 3.6 V 15 kΩ ± 5% to Ground. Internal

pull up enabled.

Static Output High, Idle 2.7 – 3.6 V 15 kΩ ± 5% to Ground. Internal

pull up enabled.

Static Output Low – – 0.3 V 15 kΩ ± 5% to Ground. Internal

pull up enabled.

USB Driver Output Impedance 28 – 44 W Including R

Resistor.

EXT

D+/D- Crossover Voltage 1.3 – 2.0 V

10.3.4 DC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25 V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.

Table 10-7. 5V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units Notes

OSOA

TCV I

EBOA

INOA

CMOA

Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

Average Input Offset Voltage Drift – 7.0 35.0 μV/°C

OSOA

– – –

1.6

1.3

1.2

7.5

mV mV mV

Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 μA. Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin

dependent. Temp =

Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias)

0.0 – Vdd

0.5 –

Vdd - 0.5

V The common-mode

input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer.

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Table 10-7. 5V DC Operational Amplifier Specifications (continued)

Symbol Description Min Typ Max Units Notes

OLOA

OHIGHO

OLOWOA

SOA

PSRR

Open Loop Gain Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

60 60 80

High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

Vdd - 0.2 Vdd - 0.2 Vdd - 0.5

Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High

– – –

Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High

Supply Voltage Rejection Ratio 65 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25)

– – – – – –

––dB

– – –

400 500

800 1200 2400 4600

– – –

0.2

0.5

800

900 1000 1600 3200 6400

V V V

μA μA μA μA μA μA

or (Vdd - 1.25V) ≤ VIN ≤ Vdd.

10.3.5 DC Low Power Comparator Specifications

The following table lists guaranteed maximum and min imum specificat ions fo r the voltage and temperature rang es: 4.75V to 5.25V and -40°C ≤ T apply to 5V at 25°C and are for design guidance only.

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

Table 10-8. DC Low Power Comparator Specifications

Symbol Description Min Typ Max Units Notes

REFLPC

SLPC

OSLPC

Low power comparator (LPC) reference voltage range

LPC supply current – 10 40 μA LPC voltage offset – 2.5 30 mV

0.2 – Vdd - 1 V

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10.3.6 DC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25 V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

Table 10-9. 5V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units Notes

OSOB

TCV

OSOB

CMOB

OUTOB

OHIGHOB

OLOWOB

SOB

PSRR

Input Offset Voltage (Absolute Value) – 3 12 mV Average Input Offset Voltage Drift – +6 – μV/°C Common-Mode Input Voltage Range 0.5 – Vdd - 1.0 V Output Resistance

Power = Low Power = High

– –

0.6

– –

W W

High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High

0.5 x Vdd + 1.1

0.5 x Vdd

+ 1.1

– –

V V

Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High

– –

––0.5 x Vdd - 1.3

0.5 x Vdd

- 1.3

V V

Supply Current Including Bias Cell (No Load) Power = Low Power = High

Supply Voltage Rejection Ratio 53 64 – dB (0.5 x Vdd - 1.3) ≤ V

– –

1.1

2.6

5.1

8.8

mA mA

≤ (Vdd - 2.3).

OUT

Table 10-10. 3.3V DC Analog Output Buffer Specificatio ns

Symbol Description Min Typ Max Units Notes

OSOB

TCV

OSOB

CMOB

OUTOB

OHIGHOB

OLOWOB

SOB

PSRR

Input Offset Voltage (Absolute Value) – 3 12 mV Average Input Offset Voltage Drift – +6 – μV/°C Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 V Output Resistance

Power = Low Power = High

– –

1 1

– –

W W

High Output Voltage Swing (Load = 1K ohms to Vdd/2) Power = Low Power = High

0.5 x Vdd + 1.0

0.5 x Vdd

+ 1.0

– –

V V

Low Output Voltage Swing (Load = 1K ohms to Vdd/2) Power = Low Power = High

– –

––0.5 x Vdd - 1.0

0.5 x Vdd

- 1.0

V V

Supply Current Including Bias Cell (No Load) Power = Low Power = High

Supply Voltage Rejection Ratio 34 64 – dB (0.5 x Vdd - 1.0) ≤ V

–

0.8

2.0

4.3

mA mA

≤ (0.5 x Vdd + 0.9).

OUT

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10.3.7 DC Analog Reference Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25 V and -40°C ≤ T are for design guidance only.

The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Anal og Reference Control register. The limits stated for AGND include the offset error o f the AGND buffer local to the Analog Continuou s Time PSoC block. Reference control power is high.

Table 10-11. 5V DC Analog Reference Specifications

Symbol Description Min Typ Max Units

BG Bandgap Voltage Reference 1.28 1.30 1.32 V – AGND = Vdd/2 – AGND = 2 x BandGap – AGND = P2[4] (P2[4] = Vdd/2) – AGND = BandGap – AGND = 1.6 x BandGap – AGND Block to Block Variation (AGND = Vdd/2) – RefHi = Vdd/2 + BandGap Vdd/2 + BG - 0.10 Vdd/2 + BG Vdd/2 + BG + 0.10 V – RefHi = 3 x BandGap 3 x BG - 0.06 3 x BG 3 x BG + 0.06 V – RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] -

– RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098 V – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] -

– RefHi = 3.2 x BandGap 3.2 x BG - 0.112 3.2 x BG 3.2 x BG + 0.076 V – RefLo = Vdd/2 – BandGap Vdd/2 - BG - 0.04 Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.04 V – RefLo = BandGap BG - 0.06 BG BG + 0.06 V – RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] -

– RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 V – RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] -

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

[5, 6]

Vdd/2 - 0.04 Vdd/2 - 0.01 Vdd/2 + 0.007 V

2 x BG - 0.048 2 x BG - 0.030 2 x BG + 0.024 V

P2[4] - 0.011 P2[4] P2[4] + 0.011 V

BG - 0.009 BG + 0.008 BG + 0.016 V

1.6 x BG - 0.022 1.6 x BG - 0.010 1.6 x BG + 0.018 V

-0.034 0.000 0.034 V

0.113

0.133

0.084

0.057

2 x BG + P2[6] -

0.018

P2[4] + P2[6] -

0.016

2 x BG - P2[6] +

0.025

P2[4] - P2[6] +

0.026

2 x BG + P2[6] +

0.077

P2[4] + P2[6]+

0.100

2 x BG - P2[6] +

0.134

P2[4] - P2[6] +

0.110

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Table 10-12. 3.3V DC Analog Reference Specifications

Note

5. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is

1.3V ± 0.02V.

6. Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the AGND.

Symbol Description Min Typ Max Units

BG Bandgap Voltage Reference 1.28 1.30 1.32 V – AGND = Vdd/2 – AGND = 2 x BandGap

[5, 6]

Vdd/2 - 0.03 Vdd/2 - 0.01 Vdd/2 + 0.005 V

Not Allowed – AGND = P2[4] (P2[4] = Vdd/2) P2[4] - 0.008 P2[4] + 0.001 P2[4] + 0.009 V – AGND = BandGap – AGND = 1.6 x BandGap – AGND Column to Column Variation (AGND =

Vdd/2)

[5, 6]

BG - 0.009 BG + 0.005 BG + 0.015 V

1.6 x BG - 0.027 1.6 x BG - 0.010 1.6 x BG + 0.018 V

-0.034 0.000 0.034 V

– RefHi = Vdd/2 + BandGap Not Allowed – RefHi = 3 x BandGap Not Allowed – RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed – RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed – RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] -

0.075

P2[4] + P2[6] -

0.009

P2[4] + P2[6] +

0.057 – RefHi = 3.2 x BandGap Not Allowed – RefLo = Vdd/2 - BandGap Not Allowed – RefLo = BandGap Not Allowed – RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed – RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed – RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.048 P2[4]- P2[6] +

0.022

P2[4] - P2[6] +

0.092

10.3.8 DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and min imum specificat ions fo r the voltage and temperature rang es: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

Table 10-13. DC Analog PSoC Block Specification s

Symbol Description Min Typ Max Units Notes

Resistor Unit Value (Continuous Time) – 12.2 – kΩ Capacitor Unit Value (Switched Capacitor) – 80 – fF

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10.3.9 DC POR and LVD Specifications

Notes

7. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.

8. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.

The following table lists guaranteed maximum and min imum specificat ions fo r the voltage and temperature rang es: 4.75V to 5.25V and -40°C ≤ T for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters apply to 5V or 3.3V at 25°C and are

Note The bits PORLEV and VM in the following table refer to bits in the VL T_CR register . See the PSoC Technical Reference Manual for more information on the VL T_ C R register.

Table 10-14. DC POR and LVD Specifications

Symbol Description Min Typ Max Units Notes

Vdd Value for PPOR Trip (positive ramp)

PPOR0R

PPOR1R

PPOR2R

PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

2.91

–

4.39

–

4.55

V V V

Vdd Value for PPOR Trip (negative ramp)

PPOR0

PPOR1

PPOR2

PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b

2.82

–

4.39

–

4.55

V V V

PPOR Hysteresis V V V

V V V V V V V V

PH0 PH1 PH2

LVD0 LVD1 LVD2 LVD3 LVD4 LVD5 LVD6 LVD7

PORLEV[1:0] = 00b

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

Vdd Value for LV D Trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 01 1b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 1 10b

VM[2:0] = 1 11b

– – –

2.86

2.96

3.07

3.92

4.39

4.55

4.63

4.72

0 0

2.92

3.02

3.13

4.00

4.48

4.64

4.73

4.81

2.98

3.08

3.20

4.08

4.57

4.74

4.82

4.91

– – –

mV mV mV

[7]

V V V V V

[8]

V V V V

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10.3.10 DC Programming Specifications

Note

9. The 50,000 cycle flash endurance per block will only be guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4V to 3.0V, 3.0V to 3.6V and 4.75V to 5.25V.

10.A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,0 00 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total numb er of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.

The following table lists guaranteed maximum and min imum specificat ions fo r the voltage and temperature rang es: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

Table 10-15. DC Programming Specifications

Symbol Description Min Typ Max Units Notes

DDP

ILP

IHP

ILP

IHP

OLV

OHV

Flash

Flash Flash

Supply Current During Programming or Verify – 15 30 mA Input Low Voltage During Programming or

– – 0.8 V

Verify Input High Voltage During Programming or

2.1 – – V

Verify Input Current when Applying Vilp to P1[0] or

– – 0.2 mA Driving internal pull down

P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or

– – 1.5 mA Driving internal pull down

P1[1] During Programming or Verify Output Low Voltage During Programming or

– – Vss + 0.75 V

Verify Output High Voltage During Programming or

Vdd - 1.0 – Vdd V

Verify

[10]

[9]

50,000 – – – Erase/write cycles per

1,800,000 – – – Erase/write cycles.

Flash Endurance (per block)

ENPB

Flash Endurance (total)

ENT

Flash Data Retention 10 – – Years

resistor.

block.

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10.4 AC Electrical Characteristics

Jitter24M1

24M

10.4.1 AC Chip-Level Specifications

The following table lists guaranteed maximum and min imum specificat ions fo r the voltage and temperature rang es: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

Table 10-16. AC Chip-Level Specifications

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

Symbol Description Min Typ Max Units Notes

IMO245V

IMO243V

IMOUSB5V

Internal Main Oscillator Frequency for 24 MHz (5V)

Internal Main Oscillator Frequency for 24 MHz (3.3V)

Internal Main Oscillator Frequency with USB (5V)

23.04 24 24.96

22.08 24 25.92

23.94 24 24.06

[11,12]

[12,13]

[12]

MHz Trimmed for 5V operation

using factory trim values.

MHz Trimmed for 3.3V operation

using factory trim values.

MHz -10°C ≤ TA ≤ 85°Cn

4.35 ≤ Vdd ≤ 5.15 Frequency locking enabled and USB traffic present.

IMOUSB3V

Internal Main Oscillator Frequency with USB (3.3V)

23.94 24 24.06

[12]

MHz -0°C ≤ TA ≤ 70°C

3.15 ≤ Vdd ≤ 3.45 Frequency locking enabled and USB traffic present.

IMO6

Internal Main Oscillator Frequency for 6 MHz 5.5 6 6.5

[11,12,13]

MHz Trimmed for 5V or 3.3V

operation using factory trim values. See the figure on page 19. SLIMO Mode = 1.

CPU1

CPU2

BLK5

BLK3

32K1

Internal Low Speed Oscillator (ILO) Untrimmed

32K_U

CPU Frequency (5V Nominal) 0.93 24 24.96 CPU Frequency (3.3V Nominal) 0.93 12 12.96 Digital PSoC Block Frequency (5V Nominal) 0 48 49.92

Digital PSoC Block Frequency (3.3V Nominal) 0 24 25.92 Internal Low Speed Oscillator Frequency 15 32 64 kHz

Frequency

5 – – kHz After a reset and before the

[11,12] [12,13]

[11,12,14]

[12,14]

MHz MHz MHz Refer to the AC Digital Block

Specifications.

MHz

m8c starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual

for details on timing this Jitter32k 32 kHz Period Jitter – 100 ns DC

ILO

Internal Low Speed Oscillator Duty Cycle 20 50 80 % Step24M 24 MHz Trim Step Size – 50 – kHz Fout48M 48 MHz Output Frequency 46.08 48.0 49.92

[11,13]

MHz Trimmed. Utilizing factory

trim values. Jitter24M1 24 MHz Period Jitter (IMO) Peak-to-Peak – 300 ps F

MAX

POWER_UP

POWERUP

Maximum frequency of signal on row input or

– – 12.96 MHz

row output. Power Supply Slew Rate – – 250 V/ms Vdd slew rate during power

up.

Time from end of POR to CPU executing code – 16 100 ms Power up from 0V. See the

System Resets section of the

PSoC Technical Reference

Manual.

Figure 10-2. 24 MHz Period Jitter (IMO) Timing Diagram

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10.4.2 AC General Purpose I/O Specifications

Notes

11. 4.75V

< Vdd < 5.25V.

12.Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.

13.3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller T ri ms for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V.

14.See the individual user module data sheets for information on maximum frequencies for user modules

TFallF TFallS

TRiseF TRiseS

90%

10%

GPIO

Output

Voltage

The following table lists guaranteed maximum and min imum specificat ions fo r the voltage and temperature rang es: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

Table 10-17. AC GPI/O Specifications

Symbol Description Min Typ Max Units Notes

GPI/O

GPI/O Operating Frequency 0 – 12 MHz Normal Strong Mode TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.5 to 5.25V, 10% - 90% TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25V , 10% - 90% TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns V dd = 3 to 5.25V, 10% - 90 % TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10% - 90%

Figure 10-3. GPI/O Timing Diagram

10.4.3 AC Full Speed USB Specifications

The following table lists guaranteed maximum and min imum specificat ions fo r the voltage and temperature rang es: 4.75V to 5.25V and -10°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -10°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

Table 10-18. AC Full Speed (12 Mbps) USB Specifications

Symbol Description Min Typ Max Units Notes

RFS

FSS

RFMFS

DRATEFS

Document Number: 38-12018 Rev. *S Page 32 of 49

Transition Rise Time 4 – 20 ns For 50 pF load. Transition Fall Time 4 – 20 ns For 50 pF load . Rise/Fall Time Matching: (TR/TF)90– 111 % For 50 pF load. Full Speed Data Rate 12 -

0.25%

12 12 +

0.25%

Mbps

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10.4.4 AC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25 V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V.

Table 10-19. 5V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units

ROA

SOA

ROA

Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10

pF load, Unity Gain)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10

pF load, Unity Gain)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

Rising Slew Rate (20% to 80%)(10 pF load, Unity

Gain)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

– – –

0.15

1.7

6.5

–

– –

– – –

3.9

0.72

0.62

5.9

0.92

0.72

– – –

μs μs μs

V/μs V/μs V/μs

Power = High, Opamp Bias = High SR

FOA

Falling Slew Rate (20% to 80%)(10 pF load, Unity

Gain)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

0.01

0.5

4.0

– – –

V/μs V/μs V/μs

Power = High, Opamp Bias = High BW

NOA

Gain Bandwidth Product

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

0.75

3.1

5.4

– – –

Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

– – –

MHz MHz MHz

Table 10-20. 3.3V AC Operational Amplifier Specifications

Symbol Description Min Typ Max Units

ROA

SOA

ROA

Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10

pF load, Unity Gain)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Falling Settling Time from 20% of ΔV to 0.1% of ΔV

(10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Rising Slew Rate (20% to 80%)(10 pF load, Unity

Gain)

Power = Low, Opamp Bias = Low

– –

0.31

2.7

– –

3.92

0.72

5.41

0.72

– –

μs μs

V/μs V/μs

Power = Medium, Opamp Bias = High SR

FOA

Falling Slew Rate (20% to 80%)(10 pF load, Unity

Gain)

Power = Low, Opamp Bias = Low

0.24

1.8

– –

V/μs V/μs

Power = Medium, Opamp Bias = High BW

NOA

Gain Bandwidth Product

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

0.67

2.8

– –

Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

– –

MHz MHz

Document Number: 38-12018 Rev. *S Page 33 of 49

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When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up

100

1000

10000

0.001 0.01 0.1 1 10 100Freq (kHz)

dBV/rtHz

0.01

0.1

1.0 10

100

1000

10000

0.001 0.01 0.1 1 10 100

Freq (kHz)

nV/rtHz

PH_BH PH_BL PM_BL PL_BL

to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.

Figure 10-4. Typical AGND Noise with P2[4] Bypass

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level.

Figure 10-5. Typical Opamp Noise

Document Number: 38-12018 Rev. *S Page 34 of 49

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10.4.5 AC Low Power Comparator Specifications

Note

15.50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively . Typical parameters

Table 10-21. AC Low Power Comparator Specifications

Symbol Description Min Typ Max Units Notes

RLPC

LPC response time – – 50 μs ≥ 50 mV overdrive comparator

reference set within V

REFLPC

10.4.6 AC Digital Block Specifications

The following table lists guaranteed maximum and min imum specificat ions fo r the voltage and temperature rang es: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

Table 10-22. AC Digital Block Specifications

Function Description Min Typ Max Units Notes

Timer Capture Pulse Width 50

[15]

– – ns Maximum Frequency, No Capture – – 49.92 MHz 4.75V < Vdd < 5.25V. Maximum Frequency, With Capture – – 25.92 MHz

Counter Enable Pulse Width 50

[15]

– – ns Maximum Frequency, No Enable Input – – 49.92 MHz 4.75V < Vdd < 5.25V. Maximum Frequency, Enable Input – – 25.92 MHz

Dead Band

Kill Pulse Width:

Asynchronous Restart Mode 20 – – ns Synchronous Restart Mode 50 Disable Mode 50

[15] [15]

– – ns

– – ns Maximum Frequency – – 49.92 MHz 4.75V < Vdd < 5.25V.

CRCPRS

Maximum Input Clock Frequency – – 49.92 MHz 4.75V < Vdd < 5.25V.

(PRS Mode)

CRCPRS

Maximum Input Clock Frequency – – 24.6 MHz

(CRC Mode)

SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due

to 2 x over clocking.

SPIS Maximum Input Clock Frequency – – 4.1 MHz

[15]

– – ns

due to 8 x over clocking.

Transmitter

Width of SS_ Negated Between Transmissions 50 Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz

Receiver Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz

due to 8 x over clocking.

Document Number: 38-12018 Rev. *S Page 35 of 49

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10.4.7 AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25 V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

Table 10-23. AC External Clock Specifications

Symbol Description Min Typ Max Units Notes

OSCEXT

– Duty Cycle 47

Frequency for USB Applications 23.94 24 24.06 MHz

50 53 %

– Power up to IMO Switch 150 – – μs

10.4.8 AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25 V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

Table 10-24. 5V AC Analog Output Buffer Spe cifications

Symbol Description Min Typ Max Units Notes

ROB

SOB

ROB

FOB

Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High

Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High

Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High

Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load

OBSS

Power = Low Power = High

Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load

OBLS

Power = Low Power = High

– –

0.65

0.8

300 300

– –

2.5

2.2

– –

μs μs

V/μs V/μs

MHz MHz

kHz kHz

Table 10-25. 3.3V AC Analog Output Buffer Specificatio ns

Symbol Description Min Typ Max Units Notes

ROB

SOB

ROB

FOB

OBSS

OBLS

Document Number: 38-12018 Rev. *S Page 36 of 49

Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High

Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High

Rising Slew Rate (20% to 80%), 1V Ste p, 100 pF Load Power = Low Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High

Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High

Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High

– –

0.5

0.7

200 200

– –

3.8

2.6

– –

μs μs

V/μs V/μs

MHz MHz

kHz kHz

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10.4.9 AC Programming Specifications

Note

16.For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

The following table lists guaranteed maximum and min imum specificat ions fo r the voltage and temperature rang es: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

Table 10-26. AC Programming Specifications

Symbol Description Min Typ Max Units Notes

RSCLK

FSCLK

SSCLK

HSCLK

SCLK

ERASEB

WRITE

DSCLK

DSCLK3

ERASEALL

PROGRAM_HOT

PROGRAM_COLD

Flash Erase Time (Bulk) – 40 – ms Erase all Blocks and protection

Rise Time of SCLK 1 – 20 ns Fall Time of SCLK 1 – 20 ns Data Set up Time to Falling Edge of SCLK 40 – – ns Data Hold Time from Falling Edge of SCLK 40 – – ns Frequency of SCLK 0 – 8 MHz Flash Erase Time (Block) – 10 – ms Flash Block Write Time – 40 – ms Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6

fields at once

Flash Block Erase + Flash Block Write Time – – 100

Flash Block Erase + Flash Block Write Time – – 200

[16] [16]

ms 0°C <= Tj <= 100°C ms -40°C <= Tj <= 0°C

Document Number: 38-12018 Rev. *S Page 37 of 49

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10.4.10 AC I2C Specifications

SDA

SCL

Sr SP

BUFI2C

SPI2C

HDSTAI2C

SUSTOI2C

SUSTAI2C

LOWI2C

HIGHI2C

HDDATI2C

HDSTAI2C

SUDATI2C

Note

17.A Fast-Mode I2C-bus device can be used in a Standar d-Mode I2C-bus syst em, but the requirement t

SU;DAT

Š 250 ns must then be met. This automatically is the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t

rmax

+ t

SU;DAT

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

The following table lists guaranteed maximum and min imum specificat ions fo r the voltage and temperature rang es: 4.75V to 5.25V and -40°C ≤ T are for design guidance only.

≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25 °C and

Table 10-27. AC Characteristics of the I

Symbol Description

SCLI2C

HDSTAI2C

LOWI2C

HIGHI2C

SUSTAI2C

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

SPI2C

SCL Clock Frequency 0 100 0 400 kHz Hold Time (repeated) START Condition. After

this period, the first clock pulse is generated. LOW Period of the SCL Clock 4.7 –1.3– μs HIGH Period of the SCL Clock 4.0 –0.6– μs Setup Time for a Repeated START Condition 4.7 –0.6– μs Data Hold Time 0 –0– μs Data Setup Time 250 –100 Setup Time for STOP Condition 4.0 –0.6– μs Bus Free Time Between a STOP and START

Condition Pulse Width of spikes are suppressed by the

input filter.

Figure 10-6. Definition for Timing for Fast/Standard Mode on the I

C SDA and SCL Pins for Vdd

Standard Mode Fast Mode

Min Max Min Max

4.0 –0.6– μs

4.7 –1.3– μs

– – 0 50 ns

[17]

Units Notes

–ns

C Bus

Document Number: 38-12018 Rev. *S Page 38 of 49

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11. Packaging Dimensions

001-58740 Rev **

This section illustrates the package specification for the CY8C24x94 PSoC devices, along with the thermal impedance for the package and solder reflow peak temperatures.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/design/MR10161.

Figure 11-1. 56-Pin (7x7x0.6 mm) QFN

Document Number: 38-12018 Rev. *S Page 39 of 49

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Figure 11-2. 56-Pin (8x8 mm) QFN

001-12921 *A

001-53450 **

Figure 11-3. 56-Pin QFN (8 X 8 X 0.9 MM) - Sawn

Document Number: 38-12018 Rev. *S Page 40 of 49

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Figure 11-4. 68-Pin (8x8 mm x 0.89 mm) QFN

TOP VIEW

1 2 3

7.90[0.311]

BOTTOM VIEW

SIDE VIEW

PLANE

SEATING

0°-12°

0.05[0.002] MAX

0.2[0.008] REF

0.9[0.035] MAX

0.70[0.028] MAX

0.08 C

0.18[0.007]

0.4 B.S.C.

0.20 R.

1 2

8.10[0.319]

7.70[0.303]

7.80[0.307]

7.90[0.311]

8.10[0.319]

7.70[0.303]

7.80[0.307]

0.28[0.011]

0.24[0.009]

0.60[0.023]

6.50[0.255] REF

NOTE: EXPOSED PAD DIMENSION VARIES BY LEADFRAME CAVITY (PADDLE) SIZE

5.69

PIN1 ID

2. REFERENCE JEDEC#: MO-220

4. ALL DIMENSIONS ARE IN MM [MIN/ MAX]

NOTES

1. HATCH IS SOLDERABLE EXPOSED PAD.

PART #

PB-FREE

STANDARD

LY68

5. PACKAGE CODE

DESCRIPTION

3. PACKAGE WEIGHT: 0.17g

LF68

SOLDERABLE

EXPOSED

PAD

5.69

51-85214 *D

Important Note

■ For information on the preferred dimensions for mounting QFN packages, see the following Application Note at

http://www.amkor.com/index.cfm?objectid=42EDA4C7-5056-AA0A-E2A372F025BF8729.

■ Pinned vias for thermal conduction are not required for the low-power PSoC device.

Document Number: 38-12018 Rev. *S Page 41 of 49

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Figure 11-5. 68-Pin Sawn QFN (8X8 mm X 0.90 mm)

001-09618 *C

51-85209 *C

Figure 11-6. 100-Ball (6x6 mm) VFBGA

Document Number: 38-12018 Rev. *S Page 42 of 49

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Figure 11-7. 100-Pin (14x14 x 1.4 mm) TQFP

51-85048 *C

Notes

18.T

= TA + POWER x θ

19.To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.

20.Higher temperatures may be required based on the solder melting point. Typical temperatures for so lder are 220 ± 5

C with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste.

Refer to the solder manufacturer specifications

11.1 Thermal Impedance

Table 11-1. Thermal Impedance for the Package

[18]

56 QFN 68 QFN

Package Typical θ

[19] [19]

12.93 °C/W

13.05 °C/W 100 VFBGA 65 °C/W 100 TQFP 51 °C/W

11.2 Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 11-2. Solder Reflow Peak Temperature

Package Minimum Peak Temperature

56 QFN 240°C 260°C 68 QFN 240°C 260°C 100 VFBGA 240°C 260°C

[20]

Maximum Peak Temperature

Document Number: 38-12018 Rev. *S Page 43 of 49

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12. Development Too l Selection

12.1 Software

12.1.1 PSoC Designer

At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at

http://www.cypress.com/psocdesigner and includes a free C

compiler.

12.1.2 PSoC Programmer

Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at

http://www.cypress.com/psocprogrammer.

12.2 Development Kits

All development kits can be purchased from the Cypress Online Store.

12.2.1 CY3215-DK Basic Development Kit

The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes:

■ PSoC Designer Software CD

■ ICE-Cube In-Circuit Emulator

■ ICE Flex-Pod for CY8C29x66 Family

■ Cat-5 Adapter

■ Mini-Eval Programming Board

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ iMAGEcraft C Compiler (Registration Required)

■ ISSP Cable

■ USB 2.0 Cable and Blue Cat-5 Cable

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

12.3 Evaluation Tools

All evaluation tools can be purchased from the Cypress Online Store.

12.3.1 CY3210-MiniProg1

The CY3210-MiniProg1 kit enables a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:

■ MiniProg Programming Unit

■ MiniEval Socket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

12.3.2 CY3210-PSoCEval1

The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

■ Evaluation Board with LCD Module

■ MiniProg Programming Unit

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

12.3.3 CY3214-PSoCEvalUSB

The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes:

■ PSoCEvalUSB Board

■ LCD Module

■ MIniProg Programming Unit

■ Mini USB Cable

■ PSoC Designer and Example Projects CD

■ Getting Started Guide

■ Wire Pack

Document Number: 38-12018 Rev. *S Page 44 of 49

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12.4 Device Programmers

Notes

21.Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.

22.Foot kit includes surface mount feet that are soldered to the target PCB.

23.Programming adapter converts non-DIP package to DIP footprint. Specific details and ord ering information for each of the adapters are found at

http://www.emulation.com.

All device programmers can be purchased from the Cypress Online Store.

12.4.1 CY3216 Modular Programmer

The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:

■ Modular Programmer Base

■ 3 Programming Module Cards

■ MiniProg Programming Unit

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

12.4.2 CY3207ISSP In-System Serial Programmer (ISSP)

The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment.

Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

12.5 Accessories (Emulation and Programming)

Table 12-1. Emulation and Programming Accessories

Part # Pin Package Flex-Pod Kit

[21]

Foot Kit

CY8C24794-24LFXI 56 QFN CY3250-24X94QFN CY3250-56QFN-FK Adapters can be found at CY8C24894-24LFXI 56 QFN CY3250-24X94QFN CY3250-56QFN-FK CY8C24794-24LQXI 56 QFN CY3250-24X94QFN None

[22]

Adapter

[23]

http://www.emulation.com.

12.5.1 Third Party Tools

Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools are found at http://www.cypress.com under Design Resources > Evaluation Boards.

12.5.2 Build a PSoC Emulator into Your Board

For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note “Debugging - Build a PSoC Emulator into Your Board - AN2323” at

http://www.cypress.com/an2323.

Document Number: 38-12018 Rev. *S Page 45 of 49

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13. Ordering Information

Notes

24.This part may be used for in-circuit debugging. It is NOT available for production

Table 13-1. CY8C24x94 PSoC Device’s Key Fe atures and Ordering Information

Package

100 Pin OCD TQFP 100-Ball OCD (6x6 mm)

[24]

VFBGA 68 Pin OCD (8x8 mm) QFN 68-Pin QFN (Sawn) CY8C24094-24LTXI 16K 1K -40°C to +85°C 4 6 56 48 2 Yes 68-Pin QFN (Sawn) CY8C24094-24LTXIT 16K 1K -40°C to +85°C 4 6 56 48 2 Yes 56-Pin (8x8 mm) QFN CY8C24794-24LFXI 16K 1K -40°C to +85°C 4 6 50 48 2 No 56-Pin (8x8 mm) QFN

(Tape and Reel) 56 Pin (7x7 mm) QFN CY8C24794-24LQXI 16K 1K -40°C to +85°C 4 6 50 48 2 No 56 Pin (7x7 mm) QFN (Tape

and Reel) 56-Pin (8x8 mm) QFN (Sawn) CY8C24794-24LTXI 16K 1K -40°C to +85°C 4 6 50 48 2 No 56-Pin (8x8 mm) QFN (Sawn)

(Tape and Reel) 56-Pin (8x8 mm) QFN CY8C24894-24LFXI 16K 1K -40°C to +85°C 4 6 49 47 2 Yes 56-Pin (8x8 mm) QFN

(Tape and Reel) 56-Pin (8x8 mm) QFN (Sawn) CY8C24894-24LTXI 16K 1K -40°C to +85°C 4 6 49 47 2 Yes 56-Pin (8x8 mm) QFN (Sawn) CY8C24894-24LTXIT 16K 1K -40°C to +85°C 4 6 49 47 2 Yes 100-Ball (6x6 mm) VFBGA CY8C24994-24BVXI 16K 1K -40°C to +85°C 4 6 56 48 2 Yes 68 Pin (8x8 mm) QFN CY8C24994-24LFXI 16K 1K -40°C to +85°C 4 6 56 48 2 Yes 68 Pin (8x8 mm) QFN

(Tape and Reel) 68-Pin QFN (Sawn) CY8C24994-24LTXI 16K 1K -40°C to +85°C 4 6 56 48 2 Yes 68-Pin QFN (Sawn) CY8C24994-24LTXIT 16K 1K -40°C to +85°C 4 6 56 48 2 Yes

[24]

CY8C24094-24AXI 16K 1K -40°C to +85°C 4 6 56 48 2 Yes CY8C24094-24BVXI 16K 1K -40°C to +85°C 4 6 56 48 2 Yes

[24]

CY8C24094-24LFXI 16K 1K -40°C to +85°C 4 6 56 48 2 Yes

CY8C24794-24LFXIT 16K 1K -40°C to +85°C 4 6 50 48 2 No

CY8C24794-24LQXIT 16K 1K -40°C to +85°C 4 6 50 48 2 No

CY8C24794-24LTXIT 16K 1K -40°C to +85 °C 4 6 50 48 2 No

CY8C24894-24LFXIT 16K 1K -40°C to +85°C 4 6 49 47 2 Yes

CY8C24994-24LFXIT 16K 1K -40°C to +85°C 4 6 56 48 2 Yes

Ordering

Code

Flash

(Bytes)

SRAM

(Bytes)

Range

Temperature

Digital Blocks

Analog Blocks

Digital I/O Pins

Analog Inputs

Analog Outputs

XRES Pin

Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).

Document Number: 38-12018 Rev. *S Page 46 of 49

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13.1 Ordering Code Definitions

Package Type: PX = PDIP Pb-Free

SX = SOIC Pb-Free PVX = SSOP Pb-Free LFX/LKX/LQX/LTX = QFN Pb-Free AX = TQFP Pb-Free BVX = VFBGA Pb-Free

Speed: 24 MHz Part Number

Family Code Technology Code: C = CMOS

Marketing Code: 8 = PSoC Company ID: CY = Cypress

8 C 24 XXX-SP XX

Thermal Rating: C = Commercial I = Industrial E = Extended

Document Number: 38-12018 Rev. *S Page 47 of 49

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Document History Page

Document Title: CY8C24094, CY8C24794, CY8C24894, CY8C24994 PSoC® Programmable System-on-Chip Document Number: 38-12018

Rev. ECN No.

** 133189 01.27.2004 NWJ New silicon and new document – Advance Data Sheet. *A 251672 See ECN SFV First Preliminary Data Sheet. Changed title to encompass only the CY8C24794

*B 289742 See ECN HMT Add standard DS items from SFV memo. Add Analog Input Mux on pinouts. 2

*C 335236 See ECN HMT Add CY logo. Update CY copyright. Update new CY.com URLs. Re-add ISSP

*D 344318 See ECN HMT Add new color and logo. Expand analog arch. diagram. Fix I/O #. Update Electrical

*E 346774 See ECN HMT Add USB temperature specificatio ns. Make data sheet Final. *F 349566 See ECN HMT Remove USB logo. Add URL to preferred dimensions for mounting MLF

*G 393164 See ECN HMT Add new device, CY8C24894 56-pin MLF with XRES pin. Add Fimousb3v char. to

*H 469243 See ECN HMT Add ISSP note to pinout tables. Update typical and recommended Storage

*I 561158 See ECN HMT Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add

*J 728238 See ECN HMT Add CapSense SNR requirement reference. Update figure standards. Update

*K 2552459 08/14/08 AZIE/PYRS Add footnote on AGND descriptions to avoid using P2[4] for digi tal signalin g as it

*L 2616550 12/05/08 OGNE/PYRS Updated Programmable Pin Configuration detail.

*M 2657956 02/11/09 DPT/PYRS Added package diagram 001-09618 and updated Ordering Information table

Submission

Date

Orig. of Change

Description of Change

because the CY8C24494 and CY8C24694 are not being offered by Cypress.

MACs. Change 512 bytes of SRAM to 1K. Add dimension key to package. Remove HAPI. Update diagrams, registers and specs.

programming pinout notation. Add Reflow Temp. table. Update features (MAC, Oscillator, and voltage range), registers (INT_CLR2/MSK2, second MAC), and specs. (Rext, IMO, analog output buffer...).

Specifications.

packages.

specs. Upgrade to CY Perform logo and update corporate address and copyright.

Temperature per industrial specs. Update Low Output Level maximum I/OL budget. Add FLS_PR1 to Register Map Bank 1 for users to specify which Flash bank should be used for SROM operations. Add two new devices for a 68-pin QFN and 100-ball VFBGA under RPNs: CY8C24094 and CY8C24994. Add two packages for 68-pin QFN. Add OCD non-production pinouts and package diagrams. Update CY branding and QFN convention. Add new Dev. Tool section. Update copyright and trademarks.

CY8C20x34 to PSoC Device Characteristics table. Add detailed dimensions to 56-pin QFN package diagram and update revision. Secure one package diagram/manufacturing per QFN. Update emulation pod/feet kit part numbers. Fix pinout type-o per TestTrack.

Technical Training paragraphs. Add QFN package clarifications and dimensions. Update ECN-ed Amkor dimensioned QFN package diagram revisions. Reword SNR reference. Add new 56-pin QFN spec.

may add noise to AGND. Remove reference to CMP_GO_EN1 in Map Bank 1 Table on Address 65; this register has no functionality on 24xxx. Add footnote on die sales. Add description 'Optional External Clock Input’ on P1[4] to match description of P1[4].

Changed title from PSoC® Mixed-Signal Array to PSoC® Programmable System-on-Chip™

Document Number: 38-12018 Rev. *S Page 48 of 49

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CY8C24094, CY8C24794 CY8C24894, CY8C24994

Document History Page

Document Title: CY8C24094, CY8C24794, CY8C24894, CY8C24994 PSoC® Programmable System-on-Chip Document Number: 38-12018

*N 2708135 05/18/2009 BRW Added Note in the Pin Information section on page 8.

Removed reference to Hi-Tech Lite Compiler in the section Development Tools

Selection on page 42. *O 2718162 06/11/2009 DPT Added 56-Pin QFN (Sawn) package diagram and upda ted ordering information *P 2762161 09/10/2009 RLRM

*Q 2768530 09/24/09 RLRM

Updated the following parameters:

F32K_U, F

ILO,

PROGRAM_COLD.

, T

IMO6

POWERUP

Added SR

, T

POWER_UP

ERASE_ALL

parameter in AC specs table

, T

PROGRAM_HOT

, and

Ordering Information table: Changed XRES Pin value for CY8C24894-24LTXI and

CY8C24894-24LTXIT to ‘Yes’. *R 2817938 11/30/09 KRIS

Ordering Information: Updated CY8C24894-24LTXI and CY8C24894-24LTXIT

parts as Sawn and updated the Digital I/O and Analog Pin values

Added Contents page. Updated 68 QFN package diagram (51-85124) *S 2846641 1/12/10 RLRM

Added package diagram 001-58740 and updated Development Tools section.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office closest to you, visit us at cypress.com/sales.

Products

PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com

© Cypress Semiconductor Corporation, 2004- 2010. The infor mation cont ain ed herein is subj ect to change wi thout notice. C ypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress produc ts are n ot war ran ted no r inte nd ed to be us ed for medical, life support, life saving, critica l contr o l or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not auth or iz e it s pr o ducts for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the u ser . The inclusion of Cypr ess products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subj ect to worldwide patent pro tectio n (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy , us e, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypres s integrated circuit as specified in the ap plicable agreem ent. Any reprod uction, modificatio n, translation, co mpilation, or repr esentation of this Source Code except as specified above i s prohibited w ithout the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTIC ULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials de scribed herei n. Cypress doe s not assume any liability arising out of the applic ation or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot author ize its products for use as critical compon ent s in life-suppo rt systems where a malfunction or failure may reason ably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-12018 Rev. *S Revised January 12, 2010 Page 49 of 49

PSoC Designer™ is a trademark a nd PSoC® is a r egistered tradema rk of C ypress Se miconducto r Corp. All oth er tradem arks or registered trademar ks referenced herei n are property of the re spective corporations.

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Cypress Semiconductor CY8C24094, CY8C24794, CY8C24894, CY8C24994 User manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Features

Logic Block Diagram

2. Contents

3. PSoC Functional Overview

3.2 The Digital System

3.1 The PSoC Core

3.3 The Analog System

3.3.1 The Analog Multiplexer System

3.4 Additional System Resources

3.5 PSoC Device Characteristics

4. Getting Started

4.1 Application Notes

4.2 Development Kits

4.3 Training

4.4 CyPros Consultants

4.5 Solutions Library

4.6 Technical Support

5. Development Tools

5.1 PSoC Designer Software Subsystems

5.1.1 System-Level View

5.1.2 Chip-Level View

5.1.3 Hybrid Designs

5.1.4 Code Generation Tools

5.1.5 Debugger

5.1.6 Online Help System

5.2 In-Circuit Emulator

6. Designing with PSoC Designer

6.1 Select Components

6.2 Configure Components

6.3 Organize and Connect

6.4 Generate, Verify, and Debug

7. Document Conventions

7.1 Acronyms Used

7.2 Units of Measure

7.3 Numeric Naming

8. Pin Information

8.1 56-Pin Part Pinout

8.2 56-Pin Part Pinout (with XRES)

8.3 68-Pin Part Pinout

8.4 68-Pin Part Pinout (On-Chip Debug)

8.5 100-Ball VFBGA Part Pinout

8.6 100-Ball VFBGA Part Pinout (On-Chip Debug)

8.7 100-Pin Part Pinout (On-Chip Debug)

9. Register Reference

9.1 Register Conventions

9.2 Register Mapping Tables

9.3 Register Map Bank 0 Table: User Space

9.4 Register Map Bank 1 Table: Configuration Space

10. Electrical Specifications

10.1 Absolute Maximum Ratings

10.2 Operating Temperature

10.3 DC Electrical Characteristics

10.3.1 DC Chip Level Specifications

10.3.2 DC General Purpose I/O Specifications

10.3.3 DC Full Speed USB Specifications

10.3.4 DC Operational Amplifier Specifications

10.3.5 DC Low Power Comparator Specifications

10.3.6 DC Analog Output Buffer Specifications

10.3.7 DC Analog Reference Specifications

10.3.8 DC Analog PSoC Block Specifications

10.3.9 DC POR and LVD Specifications

10.3.10 DC Programming Specifications

10.4 AC Electrical Characteristics

10.4.1 AC Chip-Level Specifications

10.4.2 AC General Purpose I/O Specifications

10.4.3 AC Full Speed USB Specifications

10.4.4 AC Operational Amplifier Specifications

10.4.5 AC Low Power Comparator Specifications

10.4.6 AC Digital Block Specifications

10.4.7 AC External Clock Specifications

10.4.8 AC Analog Output Buffer Specifications

10.4.9 AC Programming Specifications

10.4.10 AC I2C Specifications

11. Packaging Dimensions

11.1 Thermal Impedance

11.2 Solder Reflow Peak Temperature