Cypress Semiconductor CY8C20110, CY8C20180, CY8C20160, CY8C20140, CY8C20142 User guide
CY8C20110/CY8C20180/CY8C20160
CY8C20140/CY8C20142
CapSense® Express™ Button
Capacitive Controllers
Features
■
10/8/6/4 Capacitive Button Input
❐
Robust sensing algorithm
❐
High sensitivity, low noise
❐
Immunity to RF and AC noise
❐
Low radiated EMC noise
❐
Supports wide range of input capacitance, sensor shapes,
and sizes
■
Target Applications
❐
Printers
❐
Cellular handsets
❐
LCD monitors
❐
Portable DVD players
■
Low Operating Current
❐
Active current: continuous sensor scan: 1.5 mA
❐
Deep sleep current: 4 uA
■
Industry's Best Configurability
❐
Custom sensor tuning, one optional capacitor
❐
Output supports strong drive for LED
❐
Output state can be controlled through I2C or directly from
CapSense® input state
❐
Run time re-configurable over I2C
■
Advanced Features
❐
All GPIOs support LED dimming with configurable delay
option in CY8C21110
❐
Interrupt outputs
❐
User defined Inputs
❐
Wake on interrupt input
❐
Sleep control pin
❐
Nonvolatile storage of custom settings
❐
Easy integration into existing products – configure output to
match system
❐
No external components required
❐
World class free configuration tool
■
Wide Range of Operating Voltages
❐
2.4V to 2.9V
❐
3.10V to 3.6V
❐
4.75V to 5.25V
■
I2C Communication
❐
Supported from 1.8V
❐
Internal pull up resistor support option
❐
Data rate up to 400 kbps
❐
Configurable I2C addressing
■
Industrial temperature range: –40°C to +85°C.
■
Available in16-pin COL, 8-pin, and 16-pin SOIC Packages
Overview
These CapSense Express™ controllers support 4 to 10 capacitive sensing (CapSense buttons). The device functionality is
configured through an I2C port and can be stored in onboard
nonvolatile memory for automatic loading at power on. The
CY8C20110 is optimized for dimming LEDs in 15 selectable duty
cycles for back light applications. The device can be configured
to have up to 10 GPIOs connected to the PWM output. The PWM
duty cycle is programmable for variable LED intensities.
The four key blocks that make up these devices are: a robust
capacitive sensing core with high immunity against radiated and
conductive noise, control registers with nonvolatile storage,
configurable outputs, and I
configure registers with parameters needed to adjust the
operation and sensitivity of the CapSense buttons and outputs
and permanently store the settings. The standard I
communication interface enables the host to configure the
device and read sensor information in real time. The I2C address
is fully configurable without any external hardware strapping.
2
C communications. The user can
2
C serial
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-54606 Rev. *A Revised December 16, 2009
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Contents
Features ..............................................................................1
Overview .............................................................................1
Contents ............................................................................. 2
Pinouts ...............................................................................3
Typical Circuits ..................................................................6
Circuit-1: Five Button and Five LED with I2C Interface 6
Circuit 2 - Two Buttons and Two LEDs
with I2C Interface .........................................................6
Circuit 3 - Compatibility with 1.8V I2C Signaling .........7
Circuit 4 - Powering Down CapSense Express
Device for Low Power Requirements ...........................7
I2C Interface .......................................................................8
I2C Device Addressing .................................................8
I2C Clock Stretching .....................................................8
Format for Register Write and Read ............................9
Operating Modes of I2C Commands ..............................10
Normal Mode ..............................................................10
Setup Mode .............................................................. ..10
Device Operation Modes .................................................10
Active Mode ................................................................10
Periodic Sleep Mode ..................................................10
Deep Sleep Mode .......................................................10
Sleep Control Pin .............................................................10
Interrupt Pin to Master ....................................................10
LED Dimming ...................................................................10
LED Dimming Mode 1: Change Intensity on
ON/OFF Button Status ...............................................11
LED Dimming Mode 2: Flash Intensity on
ON Button Status .......................................................11
LED Dimming Mode 3: Hold Intensity After
ON/OFF Button Transition ..........................................12
LED Dimming Mode 4: Toggle Intensity on
ON/OFF or OFF/ON Button Transitions .....................12
Register Map ............................................................ ........13
CapSense Express Commands ................................17
Register Conventions .................................................17
Layout Guidelines and Best Practices ..........................18
CapSense Button Shapes ..........................................18
Button Layout Design .................................................18
Recommended via Hole Placement ...........................18
Example PCB Layout Design with
Two CapSense Buttons and Two LEDs .....................20
Operating Voltages ..........................................................21
CapSense Constraints ............ ........................................21
Electrical Specifications .................................................22
Absolute Maximum Ratings ........................................22
Operating Temperature ..............................................22
DC Electrical Characteristics .........................................22
DC Chip Level Specifications .....................................22
5V and 3.3V DC General Purpose I/O Specifications 22
2.7 DC General Purpose IO Specifications ................23
2.7V DC Spec for I2C Line with 1.8V
External Pull Up ..........................................................24
DC POR and LVD Specifications ...............................24
DC Flash Write Specifications ....................................25
CapSense Electrical Characteristics ..........................25
AC Electrical Specifications ...........................................26
5V and 3.3V AC General Purpose I/O Specifications 26
2.7V AC General Purpose I/O Specifications .............26
2
C Specifications .................................................26
AC I
Appendix- Examples of Frequently Used
I2C Commands ................................................................27
Ordering Information .......................................................28
Ordering Code Definition ............................................28
Package Diagrams ...........................................................29
Document History Page ............................................ ......31
Sales, Solutions, and Legal Information .......................31
Worldwide Sales and Design Support ........................31
Products .....................................................................31
PSoC Solutions ..........................................................31
Document Number: 001-54606 Rev. *A Page 2 of 31
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Pinouts
Note
1. 8/6/4 available configurable IOs can be configured to any of the 10 IOs of the package. Af ter any of the 8/6/4 IOs are ch osen, the remaining 2/ 4/6 IOs of the p ackage
are not available for any functionality.
Figure 1. Pin Diagram - 16 COL- CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons)
Table 1. Pin Definitions – 16 COL- CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons)
CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons)
Pin No. Pin Name Description
1 GP0[0] Configurable as CapSense or GPIO
2 GP0[1] Configurable as CapSense or GPIO
3I
4I
5 GP1[0] Configurable as CapSense or GPIO
6 GP1[1] Configurable as CapSense or GPIO
7 VSS Ground Connection
8 GP1[2] Configurable as CapSense or GPIO
9 GP1[3] Configurable as CapSense or GPIO
10 GP1[4] Configurable as CapSense or GPIO
11 XRES Active high external reset with internal pull up
12 GP0[2] Configurable as CapSense or GPIO
13 VDD Supply voltage
14 GP0[3] Configurable as CapSense or GPIO
15 CSInt Integrating Capacitor Input. The external capacitance is required
16 GP0[4] Configurable as CapSense or GPIO
CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons)
[1]
2
C SCL I2C Clock
2
C SDA I2C Data
only if 5:1 SNR cannot be achieved. Typical range is 1 nF to 4.7 nF
Document Number: 001-54606 Rev. *A Page 3 of 31
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Figure 2. Pin Diagram – 16 SOIC– CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons)
CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons)
Table 2. Pin Definitions – 16 SOIC– CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons)
CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons)
Pin No Name Description
1 GP0[3] Configurable as CapSense or GPIO
2 CSint Integrating Capacitor Input. The external capacitance is required only if 5:1 SNR
3 GP0[4] Configurable as CapSense or GPIO
4 GP0[0] Configurable as CapSense or GPIO
5 GP0[1] Configurable as CapSense or GPIO
6I
7I
8 GP1[0] Configurable as CapSense or GPIO
9 GP1[1] Configurable as CapSense or GPIO
10 VSS Ground Connection
11 GP1[2] Configurable as CapSense or GPIO
12 GP1[3] Configurable as CapSense or GPIO
13 GP1[4] Configurable as CapSense or GPIO
14 XRES Active high external reset with internal pull up
15 GP0[2] Configurable as CapSense or GPIO
16 VDD Supply voltage
2
C SCL I2C Clock
2
C SDA I2C Data
1]
cannot be achieved. Typical range is 1 nF to 4.7 nF
Document Number: 001-54606 Rev. *A Page 4 of 31
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Figure 3. Pin Diagram - 8-Pin SOIC- CY8C20142 (4 Button)
Table 3. Pin Definitions - 8-Pin SOIC - CY8C20142 (4 Button)
Pin No Name Description
1 VSS Ground
2I
3I
4 GP1[0] Configurable as CapSense or GPIO
5 GP1[1] Configurable as CapSense or GPIO
6 GP0[0] Configurable as CapSense or GPIO
7 GP0[1] Configurable as CapSense or GPIO
8 VDD Supply voltage
2
C SCL I2C Clock
2
C SDA I2C Data
Document Number: 001-54606 Rev. *A Page 5 of 31
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Typical Circuits
Circuit-1: Five Button and Five LED with I2C Interface
2
Circuit 2 - Two Buttons and Two LEDs with I
C Interface
Document Number: 001-54606 Rev. *A Page 6 of 31
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Circuit 3 - Compatibility with 1.8V I2C Signaling
Master
Or
Host
LDO
CapSense Express
I2C Pull
UPs
LED
I2C
BUS
SDA
SCL
VDDOutput
Output
enable
Note 1.8V ≤ VDD_I2C ≤ VDD_CE and 2.4V ≤ VDD_CE ≤ 5.25V
Circuit 4 - Powering Down CapSense Express Device for Low Power Requirements
For low power requirements, if Vdd is to be turned off, this concept can be used. The requirement is that the Vdds of CapSense
Express, I
the device while it is unpowered. The I
pins of the master can cater to the power supply requirements of the circuit, the LDO can be avoided.
2
C pull ups, and LEDs should be from the same source such that turning off the Vdd ensures that no signal is applied to
2
C signals should not be driven high by the master in this situation. If a port pin or group of port
Document Number: 001-54606 Rev. *A Page 7 of 31
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I2C Interface
The CapSense Express devices support the industry standard I2C protocol, which can be used for:
■
Configuring the device
■
Reading the status and data registers of the device
■
Controlling device operation
■
Executing commands
2
The I
C address can be modified during configuration.
I2C Device Addressing
The device uses a seven bit addressing protocol. The I2C data transfer is always ini tiated by the master sending a one byte address:
the first 7 bits contain the address and the LSB indicates the data transfer direction. Zero in the LSB bit indicates the write transaction
from master and one indicates read transfer by the master. The following table shows examples for different I
2
Table 4. I
C Address Examples
2
C addresses.
7 Bit Slave
Address
D7 D6 D5 D4 D3 D2 D1 D0 8 Bit Slave Address
1 00000 0 10(W) 02
1 00000 0 11(R) 03
75 10010 1 10(W) 96
75 10010 1 11(W) 97
I2C Clock Stretching
‘Clock stretching’ or ‘bus stalling’ in I2C communication protocol
is a state in which the slave holds the SCL line low to indicate
that it is busy. In this condition, the master is expected to wait till
the SCL is released by the slave.
When an I
device, the CapSense Express stalls the I
reception of each byte (that is, just before the ACK/NAK bit) until
processing of the byte is complete and critical internal functions
are executed. Use a fully I
with the CapSense Express device.
2
C master communicates with the CapSense Express
2
C compliant master to communicate
2
C bus after the
If the I2C master does not support clock stretching (a bit banged
software I
2
C Master), the master must wait for a specific amount
of time (as specified in “Format for Register Write and Read” on
page 9) for each register write and read operation before the next
bit is transmitted. The I
should be high) before the I
2
C master must check the SCL status (it
2
C master initiates any data transfer
with CapSense Express. If the master fails to do so and
continues to communicate, the communication is erroneous.
The following diagrams represent the ACK time delays shown in
“Format for Register Write and Read” on page 9 for write and
read.
Document Number: 001-54606 Rev. *A Page 8 of 31
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Figure 4. Write ACK Time Representation
Notes
2. Time to process the received data
3. Time taken for the device to send next byte
[2]
Figure 5. Read ACK Time Representation
[3]
Format for Register Write and Read
Register write format
Start Slave Addr + W AReg AddrADataADataA . . . . . Data A Stop
Register read format
Start Slave Addr + W
Start Slave Addr + R
Legends:
Master A - ACK
Slave N- NAK
AReg AddrAStop
A Data A Data A . . . . . Data NStop
Document Number: 001-54606 Rev. *A Page 9 of 31
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Operating Modes of I2C Commands
Normal Mode
In normal mode of operation, the acknowledgment time is
optimized. The timings remain approximately the same for
different configurations of the slave. To reduce the acknowledgment times in normal mode, the registers 0x06-0x09, 0x0C,
0x0D, 0x10-0x17, 0x50, 0x51, 0x57-0x60, 0x7E are given only
read access. Write to these registers can be done only in setup
mode.
Setup Mode
All registers have read and write access (except those which are
read only) in this mode. The acknowledgment times are longer
compared to normal mode. When CapSense scanning is
disabled (command code 0x0A in command register 0xA0), the
acknowledgment times can be improved to values similar to the
normal mode of operation.
Device Operation Modes
CapSense Express devices are configured to operate in any of
the following three modes to meet different power consumption
requirements:
■
Active Mode
■
Periodic Sleep Mode
■
Deep Sleep Mode
Active Mode
In the active mode, all the device blocks including the CapSense
sub system are powered. Typical active current consumption of
the device across the operating voltage range is 1.5 mA.
Periodic Sleep Mode
Sleep mode provides an intermediate power operation mo de. It
is enabled by configuring the corresponding device registers
(0x7E, 0x7F). The device goes into sleep after there is no event
for stay awake counter (Reg 0x80) number of sleep intervals.
The device wakes up on sleep interval and It scans the capacitive sensors before going back to sleep again. If any sensor is
active, then the device wakes up. The device can also wake up
from sleep mode with a GPIO interrupt. The following sleep
intervals are supported in CapSense Express. The sleep interval
is configured through registers.
■
1.95 ms (512 Hz)
■
15.6 ms (64 Hz)
■
125 ms (8 Hz)
■
1s (1 Hz)
Deep Sleep Mode
Deep sleep mode provides the lowest power consumption
because there is no operation running. All CapSense scanning
is disabled during this mode. In this mode, the device wakes up
only using an external GPIO interrupt. A sleep timer interrupt
cannot wake up a device from deep sleep mode. This is treated
as a continuous sleep mode without periodic wakeups. Refer to
the application note CapSense Express Power and Sleep
Considerations - AN44209 for details on different sleep modes.
To get the lowest power during this mode the sleep timer
frequency should be set to 1 Hz.
Sleep Control Pin
The devices require a dedicated sleep control pin to enable
reliable I
This is achieved by pulling the sleep control pin low to wake up
the device and start I2C communication. The sleep control pin
can be configured on any GPIO.
2
C communication in case any sleep mode is enabled.
Interrupt Pin to Master
To inform the master of any button press a GPIO can be
configured as interrupt output and all CapSense buttons can be
connected to this GPIO with an OR logic operator. This can be
configured using the software tool.
LED Dimming
To change the brightness and intensity of the LEDs, the host
master (MCU, MPU, DSP, and so on) must send I
and program the PWM registers to enable output pins, set duty
cycle, and mode configuration. The single PWM source is
connected to all GPIO pins and has a common user defined duty
cycle. Each PWM enabled pin has two possible outputs: PWM
and 0/1 (depending on the configuration). Four different modes
of LED dimming are possible, as shown in “LED Dimming Mode
1: Change Intensity on ON/OFF Button Status” on page 11 to
“LED Dimming Mode 4: Toggle Intensity on ON/OFF or OFF/ON
Button Transitions” on page 12. The operation mode and duty
cycle of the PWM enabled pins is common. This means that one
pin cannot behave as in Mode1 and another pin as in Mode 2.
2
C commands
Document Number: 001-54606 Rev. *A Page 10 of 31
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