Cypress Semiconductor CY7C961-NC, CY7C960-UMB, CY7C960-UM, CY7C960-NC, CY7C960-ASC Datasheet

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f

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ax id: 5603

CY7C960

CY7C961

Low Cost VMEbus Interface

Controller Famil

Features

• 80-Mbyt e-per-second block transfer rate s

• All VME64 transactions provided, including A64/D64,
A40/MD32 transfers

• Auto Slot ID

• CR/CSR space

• All standar d (Rev C) VMEbus transactio ns implemented

• VMEbus Inter rupter

• No local CPU required

• Programmabl e from VMEbus, serial PROM, or local bus

• DRAM controller, including refresh

• On-chip DMA controller

• Local I/O controller

• Flexibl e VMEb us address scheme

• User-configured VMEbus response

• 64-pin TQFP, 10x10mm (CY7C960)

• 100-pin TQFP, 14x14mm (CY7C961)

CY7C960 Logic Block Diagram

D64

STROBE

DENO*

REGION [3:0]

DENIN*

Functional Description

The CY7C960 Slave VMEbus In terface Cont roller provides the
board designer with an integrated, full-featured VME64 inter­face. This 64-pin device can be programmed to handle every
transacti on defi ned i n t he VM E64 speci fic ation . The CY7C961
is based upon the CY7C960: additional features include Re­mote Master capability whereby th e CY7C961 c an be com­manded to move data as a VMEbus master. The CY7C961 is
packaged in a 100-pi n outline.

The CY7C960 contains all the circuitry needed to co ntrol large
DRAM arra ys and loca l I/O circu it ry without the intervention of
a local CPU. There are no registers to read or write, no com­plex command blocks to be constructed in memory. The
CY7C960 simply fetches its own configuration parameters
during the power-on reset period. After reset the CY7C960
responds appropriately to VMEbus activity and controls local
circuitry transparently.

DENIN1*

LADI

LAEN

LDS

LEDI

LEDO

ABEN*

AM [5:0]

SYSRESET*

CLK

AS*
DS0*
DS1*

DTACK*

WRITE*

IRQ*

IACK*

IACKIN*

IACKOUT*

REGION/

AM T ABLE

POWER-ON

RESET

GENERATOR

VMECONTROL

INTERF

ACE

VME INTERRUPT

INTERFACE

LIRQ*

CY7C964CONTROLLER

TIMING

GENERATOR

REFRESH

CONTROLLER

DRAM

CONTROLLER

COL

ROW

RAS*

CAS*

DATABYTE

LANE

DECODER

LOCAL ADDRESS

CONTROLLER

CHIP SELECT

OUTPUT PATTERN

TABLE

DATA BYTE

ENABLE

CONTROLLER

LOCAL

CONTROL

CIRCUIT

LA[7:1]
LWORD

CS[5:0]

DBE[3:0]
LACK*

LDEN*
PREN*
SWDEN*
R/W

c960–1

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1994 – Revised December 4

1997

CY7C961LogicBlockDiagram

REGION[3:0]

SELECTLM

CY7C960

CY7C961

D64

STROBE

DENO*

DENIN*

DENIN1*

LADI

LAEN

LEDI

LEDO

ABEN*

LDS

MWB*

BLT

LADO

FC1

LAEN321

VMECNT

AM[5:0]

REGION/

AMTABLE

POWER-ON

SYSRESET*

RESET

GENERATOR

CLK

AS*
DS0*
DS1*

DTACK*

WRITE*

BR*

BBSY*

VME

CONTROL

INTERFACE

BERR*

BGIN*

BGOUT*

IRQ*

IACK*

IACKIN*

IACKOUT*

VME
INTERRUPT
INTERFACE

CY7C960 Pin Configuration

LIRQ*

TQFP

Top View

CY7C964 CONTROLLER

GENERATOR

CONTROLLER

LOCK

CONTROLLER

TIMING

DMA

REFRESH

CONTROLLER

DATABYTE

DECODER

DRAM

CONTROLLER

COL

ROW

RAS*

CAS*

CONTROLLER

DMA CHANNEL

CHIPSELECT

PATTERN TABLE

LANE

LOCAL

ADDRESS

REGISTERS

OUTPUT

DATA BYTE

ENABLE

CONTROLLER

LOCAL

CONTROL

CIRCUIT

c960–2

LA[7:1]
LWORD

LD[7:0]

CS[5:0]

DBE[3:0]
LACK*

LBERR*

LDEN*
PREN*
SWDEN*
R/W

LACK*

LIRQ*

LDEN*

CS0
CS1
AM3

REGION3/CS2

AM4
VCC

GND

REGION2

CLK

WRITE*
REGION1
REGION0

DENIN*

SWDEN*

PREN*

64 63 6162 60
1
2
3

4
5
6
7
8
9
10
11
12
13
14
15
16

17

18 19 2120 22 23 2625 2728 2924

DENO*

IACKOUT*

AM1

RAS*/CS4

CAS*/CS5

AM2

59 58

AS*

IACK*

IACKIN*

GND

ROW/CS2

COL/CS3

LADI

STROBE

AM0

VCC

DBE0

53 52 5051 4957 56

5455

VCC

GND

DS0*

ABEN*

DTACK*

DBE1

SYSRESET*

DBE2

D64

R/W

DBE3

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

32

3130

LEDI

LEDO

LA7
LA6

LA5
LA4
IRQ*
LA3
GND
AM5
LA2

VCC
LA1
DS1*
LWORD
LDS
DENIN1*
LAEN

c960–3

2

CY7C960

CY7C961

CY7C961 Pin Configuration

SWDEN*

PREN*

10099 9798 96

LACK*

LIRQ*

LDEN*

LD1

CS0

VCC

LD2

CS1

NC

AM3

REGION3/CS2

AM4
VCC

BERR*

GND

VMECNT

REGION2

LD0

CLK

NC

WRITE*

NC
REGION1
REGION0

DENIN*

1
2
3
4
5

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26

27 28 3029 31 32 3534 3637 3833

TQFP

Top View

AM2

RAS*/CS4

LD3

CAS*/CS5

95 94

NC

LD4

NC

LD5

COL/CS3

ROW/CS2

89 88 8687 8593 92 84

9091

DBE0

GND

BR*

4241

4039

AM0

NC

VCC

LD6

DBE1

GND

DBE2

83 82 81 80 79 78 77 76

43 44 4546 47 48 49

DBE3

R/W

75
74
73
72
71
70
69

68
67
66
65
64
63
62
61
60

59
58

57
56
55
54
53
52
51

50

LA7
LA6

LA5
LD7
LA4
SELECTLM*
LBERR*
IRQ*
NC

LA3
LAEN321
GND
AM5
LA2
BBSY*
VCC
LA1

NC
DS1*
NC
LWORD
FC1
LDS
DENIN1*
LAEN

AM1

NC

NC

AS*

LADI

BGIN*

ABEN*

STROBE

Functional Description

DENO*

IACKIN*

BGOUT*

IACKOUT*

(continued)

IACK*

MWB*

The CY7C960 controls a bridge between t he VM Ebus and lo­cal DRAM and I/O. Once programmed, the CY7C960 provi des
activities such as DRAM refresh and local I/ O handshaking in
a manner that requires no additional local circuitry. The VME­bus control signals are connected directly to the CY7C960.
The VMEbus add ress and d ata signal s are con nect ed to com­panion address/data transceivers which are controlled by the
CY7C960. The CY7C964 VM Ebus Int erface Logic Circui t is an
ideal compani on dev ice: the CY7C964 pr ov ides a sli ce o f dat a
and address logic that has been optimized for VME64 trans­actions. In addition to providing the specified drive strength
and timing for VME64 transactio ns, the CY7C964 contains all
the circ uitry needed to multiplex the address/data bus for mul­tiplexed VMEbus transactions. It contains counters and latch­es needed during BLT operati ons; and it also cont ains address
comparators which can be used in the board’s Slave Address
Decoder. For a 6U or 9U application, four CY7C964 devices
are controlled by a single CY7C960. For 3U applications, the
CY7C960 controls two CY7C964 devices and an address
latch.

The design of t he CY7C960 mak es it unnece ssary to know th e
details of the VMEbus transaction timing and protocol. The
comple x VMEb us ac tivi ties are t r anslat ed by CY7C96 0 t o sim­ple local cycl es inv olving a f ew f amili ar control signals. Similar­ly, it is not necess ar y to understand the operation of the com-

c960–4

NC

NC

BLT

GND

DTACK*

VCC

DS0*

D64

LEDI

LADO

LEDO

SYSRESET*

panion devi ce, CY7C964: all control sequences f or the part are
generated auto matically b y the CY7C960 in r esponse to VME­bus or local activity. If more i nformation i s desired, consult the
CY7C964 chapter in the

VIC64 Design Notes

(av ail ab l e sep a-

rately).
VMEbus transactions supported by the CY7C960 include D8,

D16, D32 (incl. UAT), MD32, D64, A16, A24, A32, A40, A64
single-cycle and block-transfer reads and writes, Read-Modi­fy-Write cycles (incl. multiplexed), and Address-only (with or
without Handshake). The CY7C960 functions as a VMEbus
Interrupter, and supports the new Auto Slot ID standard and
CR/CSR space. The CY7C960 also han dles LOCK cycles , al­though full LOCK support is not possible within the constrai nts
of the CY7C960 pinout. Full LOCK support is provided by the
CY7C961.

On the local side , no CPU is neede d to progr am the CY7C960,
nor to manage tr ansactions . All pr ogramma ble par ameters are
initialized through the use of either the VMEbus, a serial PROM, or
some other local circuit. As the CY7C960 incorporates a reliable
power -o n re se t ci rcu i t, pa r am ete rs are se l f-l oad ed by th e de vi ce at
power-up or after a system reset. If the VMEbus is used to provide
param eters , a VMEb us Mas ter pr ovi des the prog rammi ng inf o rma­tion using a protocol, des cribed in the Us er’ s Guide, which is c om­pliant with the Auto Slot ID protocol from the new VME64 specifica­tion.

3

CY7C960

CY7C961

To assist in generating the configuration file, a Win­dows™-based program is available which guides the user through
the proces s of select ing appropr iate opt ions. Conta ct your Sales
Office for further details.

The CY7C961 is a true s uperset of the CY7C960. Signal pins
hav e been added to control CY7C964 DMA function s. Existin g
VMEbus input pins have been changed to bidirectional and
augmented to complete a master interface. A data port and
chip select signal (SELECTLM*) complete the pin additions.
As a VMEbus Slave, the CY7C961 behaves in every respect
like the CY7C960. It simply has more pins, a master block
transf er f acilit y , and (becau se of the additio n of the BBSY* con­nection) full lock cycle support.

Fr om a system persp ective, the CY7C961 master block tr ans­fer cap abi lity can be v iew ed as a DMA ch annel t hat re sides o n
the slave card, but is controlled over the VMEbus by one or
more VMEbus masters or programmed from the local bus.

System Diagram Using the CY7C960

LA [31:0]

DRAMMEMORY I/O

DBE[3:0], RW

LACK*

RAS*,CAS*, ROW,

COL

The CY7C961 master bloc k f acili ty provi des “bl ock tr an sf er on
demand” capability for slave cards built around the Cypress
CY7C961/CY7C964 chipset. This facility allows one or many
VMEbus masters to write short series of commands to the
slave card, telling it how much data to move, where to get it
from, where to put it, and what transfer protocol to use while
moving it. Bl ock s can be mo ved over the VMEb us as indivisib le
single cycles or BLTs. The protocol menu includes D8, D16,
D32, MD32, or D64. A16, A24, A32, A40, and A64 address
spaces can be specified. Burst lengths from 16 bytes to 8
megabytes can be re quested. Eight regis ters accessib le from
the VMEbus make the facility simple to configure and simple
to control . The f acili ty has a b usy sem aphore , a VM Ebus Int er­rupt on completion feature with a programmable Status/ID
byte, and a bui lt in requester and b us grant daisy chain.

LIRQ*

CS[2:0]

D[31:16]

CY7C964

A[31:24]

SWDEN

RW

SWAP

BUFFER

VCOMP

LA[31:0]

CY7C964 CY7C964CY7C964 CY7C960

D[31:24]

D[23:16]

A[23:16]

VMEDATABUS

VME ADDRESSBUS

LD[15:0]

D[15:8]

A[15:8]

DECODER

REGION

LA [7:1, LWORD]

D[7:0]

D[31:0]

A[7:1], LWORD*

A [31:1], LWORD*

AS*

AM[5:0]

DS1/0*

DTACK

WRITE*

IRQ*

IACK*

IACKIN*

IACKOUT*

SYSRESET*

VMEINTERRUPT BUS

4

c960–5

CY7C960

CY7C961

DC Specifications - VMEbus Signals AS*, DS1*, DS0*, DTACK*, BBSY

Parameter Description Test Conditions Comm. Industrial Military Units

V

IH

V

IL

V

OH

V

OL

I

L

V

IK

I

OZ

Minimum High-Level
Input Voltage

Maximum Low-Level
Input Voltage

Minimum High-Level
Output Voltage

Maximum Low-Level
Output Voltag e

Maximum Input
Leakage Current

VCC = Min.,
I

=

OH

VCC = Min.,
I

=

OL

VCC = Max.,
GND < V

IN

Input Clamp Voltage VCC = Min., I
Maximum Output

Leakage Current

VCC = Max.
GND <

V

Outputs Disabled

OUT

2.0 2.0 2.0 V

0.8 0.8 0.8 V

2.4
–16 mA

0.6
64 mA

2.4
–10 mA

0.6
60 mA

2.4
–9 mA

0.6
52 mA

±5 ±5 ±5

< V

CC

= –18 mA –1.2 –1.2 –1.2 V

IN

±10 ±10 ±10

< V

CC

V

V

µA

µA

DC Specifications - VMEbus Signals AM5, AM4, AM3, AM2, AM1, AM0, IRQ*, BERR*, Write, BR

Parameter Description Test Conditions Comm. Industrial Military Units

V

IH

V

IL

V

OH

V

OL

I

L

V

IK

I

OZ

DC Specifications - All Other Output Signals

Parameter Description Test Conditions Comm. Industrial Military Units

V

IH

V

IL

V

OH

V

OL

I

L

V

IK

I

OZ

Notes:

1. The BERR* signal has an on-chip pull-up resistor. For this signal the I

2. Some signals have an on-chip pull-up or pull-down resistors. For these signals I

Maximum High-Level
Input Voltage

Maximum Low-Level
Input Voltage

Minim um H igh -L evel
Output Voltage

Minim u m Low-Lev el
Output Voltag e

Maximum Input
Leakage Current

V

= Min.,

CC

I

=

OH

VCC = Min.,
I

=

OL

VCC = Max.,
GND < V

IN

Input Clamp Voltage VCC = Min., I
Maximum Output

Leakage Current

VCC = Max.
GND < V
Outputs Disabled

OUT

Maximum High-Level
Input Voltage

Maximum Low-Level
Input Voltage

Minim um H igh -L evel
Output Voltage

Minim u m Low-Lev el
Output Voltag e

Maximum Input
Leakage Current

VCC = Min.,
I

=

OH

VCC = Min.,
I

=

OL

VCC = Max.,
GND < V

IN

Input Clamp Voltage VCC = Min., I
Maximum Output

Leakage Current

VCC = Max.
GND < V
Outputs Disabled

OUT

2.0 2.0 2.0 V

0.8 0.8 0.8 V

2.4
–16 mA

0.6
48 mA

2.4
–10 mA

0.6
44 mA

2.4
–9 mA

0.6
38 mA

±5 ±5 ±5

< V

CC

= –18 mA –1.2 –1.2 –1.2 V

IN

±5 ±5 ±10

< V

CC

[2]

2.0 2.0 2.0 V

0.8 0.8 0.8 V

2.4
–16 mA

0.6
20 mA

2.4
–10 mA

0.6
18 mA

2.4
–9 mA

0.6
16 mA

±5 ±5 ±5

< VCC

= –18 mA –1.2 –1.2 –1.2 V

IN

±5 ±5 ±10

< V

CC

value is modified by Pullup/Pulldown Current.

OZ

value is modified.

OZ

V

V

µA

µA

V

V

µA

µA

[1]

5

Capacitance - All Signals

Parameters Description Test Conditions Max. Units

C
C

IN
OUT

Input Capacitance TA = 25°C, f = 1 MHz,

V

= 5.0V

Output Capacitance 15 pF

CC

15 pF

Pullup/Pulldown Current - All Signals

Parameters Description Test Conditions Typ. Max.

I

PU

I

PU

Input Pullup
Current

Input Pullup
Current

TA = –55°C, VCC = 5.5V
V

= GND

IN

TA = –55°C, VCC = 5.5V
V

= V

IN

CC

100 µA 250 µA

100 µA 250 µA

Operating Current (CY7C960/CY7C961)

Parameters Description Test Conditions Max. Units

I

DD

Maximum Operating Current No external DC load 100 mA

Related Documents

VMEBus Interface Handbook

CY7C960

CY7C961

Ordering Information

Pac kage

Ordering Code

CY7C960-ASC A64 10x10 mm body 64-Lead Pl astic Thin Quad Flatpac k Commercial
CY7C960-NC N65 14x14 mm body 64-Lead Plastic Thin Quad Flat pack
CY7C960-UM U65 14x14 mm body 64 lead Ceramic Quad Flatpack Military
CY7C960-UMB U65 14x14 mm body 64 lead Ceramic Quad Flatpack

Ordering Code

CY7C961-NC A100 14x14 mm body 100-Lead Plasti c Thin Quad F latpac k Commercial
Windows is a trademark of Microsoft Corporation.

Document #: 38-00250-D

Name

Package

Name Packag e Type

Packag e Type

Operating

Range

Operating

Range

6

Package Diagrams

CY7C960

CY7C961

64-PinThinQuadFlatpackA64

7

CY7C960

CY7C961

Package Diagrams

(continued)

100-Pin Thin Quad Flatpack

A100

8

CY7C960

CY7C961

Package Diagrams

(continued)

64-Lead Plastic Thin Quad Flatpack

N65

9

CY7C960

CY7C961

Package Diagrams

(continued)

64-Lead Ceramic Quad Flatpack (Cavity Up) U65

© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any l icense under patent or other rights. Cypress Semi conductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.