Cypress Semiconductor CY7C64215 User Manual

CY7C64215

enCoRe™ III Full Speed USB Controller

Features

enCoRe III Core

Block Diagram

■

Powerful Harvard Architecture Processor

❐

M8C Processor Speeds to 24 MHz

❐

Two 8x8 Mu lt i pl y, 32-bit Accumu la te

❐

3.0V to 5.25V Operating Voltage

❐

USB 2.0 USB-IF certified. TID# 40000110

❐

Operating Temperature Range: 0°C to +70°C

■

Advanced Peripherals (enCoRe™ III Blocks)

❐

6 Analog enCoRe III Blocks provide:

• Up to 14-bit Incremental and Delta-Sigma ADCs

❐

Programmable Threshold Comparator

❐

4 Digital enCoRe III Blocks provide:

• 8-bit and 16-bit PWMs, timers and counters

•I2C Master

• SPI Master or Slave

• Full Duplex UART

• CYFISNP and CYFISPI modules to talk to Cypress CYFI
radio

■

Complex Peripherals by Combining Blocks

■

Full-Speed USB (12 Mbps)

❐

Four Unidirectional Endpoints

❐

One Bidirectional Control Endpoint

❐

Dedicated 256 Byte Buffer

❐

No External Crystal Required

❐

Operational at 3.0V – 3.6V or 4.35V – 5.25V

■

Flexible On-Chip Memory

❐

16K Flash Program Storage 50,000 Erase/Write Cycles

❐

1K SRAM Data Storage

❐

In-System Serial Programming (ISSP)

❐

Partial Flash Updates

❐

Flexible Protection Modes

❐

EEPROM Emulation in Flash

■

Programmable Pin Configuratio n s

❐

25-mA Sink on all GPIO

❐

Pull up, Pull down, High- Z, Strong, or Open Drain Drive
Modes on all GPIO

❐

Configurable Interrupt on all GPIO

■

Precision, Programmable Clocking

❐

Internal ±4% 24 and 48 MHz Oscillator

❐

Internal Oscillator for Watchdog and Sleep

❐

0.25% Accuracy for USB with no External Components

■

Additional System Resources

❐

I2C™ Slave, Master, and Multi-Master to 400 kHz

❐

Watchdog and Sleep Timers

❐

User-Configurable Low Voltage Detection

❐

Integrated Supervisory Circuit

❐

On-Chip Precision Voltage Reference

■

Complete Development T ools

❐

Free Development Software (PSoC® Designer™)

❐

Full-Featured, In-Circuit Emulator and Programmer

❐

Full Speed Emulation

❐

Complex Breakpoint Structure

❐

128K Bytes Trace Memory

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document 38-08036 Rev. *C Revised December 08, 2008

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CY7C64215

Applications

DIGITAL SYSTEM

To System Bus

D

i

g

i

t

a

l

C

l

o

c

k

s

F

r

o

m

C

o

r

e

Digital enCoRe III Block Array

To Analog

System

8

Row Inp ut

Configuration

Row Output

Configuration

88

8

Row 0

DBB00 DBB01 DCB02 DCB03

4

4

GIE[7:0]
GIO[7:0]

GOE[7:0]
GOO[7:0]

Global Digital
Interconnect

Port 1

Port 0

Port 3

Port 2

Port 5

Port 4

Port 7

■

PC HID devices

❐

Mouse (Optomechanical, Optical, Trackball)

❐

Keyboards

❐

Joysticks

■

Gaming

❐

Game Pads

❐

Console Keyboards

■

General Purpose

❐

Barcode Scanners

❐

POS Terminal

❐

Consumer Electronics

❐

Toys

❐

Remote Controls

❐

USB to Serial

enCoRe III Functional Overview

The enCoRe III is based on flexible PSoC architecture and is a
full-featured, full-speed (12 Mbps) USB part. Configurable
analog, digital, and interconnect circuitry enable a high level of
integration in a host of consumer, and communication applica­tions.

This architecture allows the user to create customized peripheral
configurations that match the requirements of each individual
application. Additionally, a fast CPU, Flash program memory,
SRAM data memory, and configurable IO are included in both
28-pin SSOP and 56-pin QFN packages.

The enCoRe III architecture, as illustrated in Figure , is
comprised of four main areas: enCoRe III Core, Digital System,
Analog System, and System Resources including a full-speed
USB port. Configurable global busing allows all the device
resources to combine into a complete custom system. The
enCoRe III CY7C64215 can have up to seven IO ports that
connect to the global digital and analog interconnects, providing
access to 4 digital blocks and 6 analog blocks.

communication. A low power 32 kHz ILO (internal low speed
oscillator) is provided for the Sleep timer and WDT. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the enCoRe III. In USB systems, the IMO
self-tunes to ±0.25% accuracy for USB communication.

enCoRe III GPIOs provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.

The Digital System

The Digital System is composed of four digital enCoRe III blocks.
Each block is an 8-bit resource that is used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.

Figure 1. Digital System Block Diagram

enCoRe III Core

The enCoRe III Core is a powerful engine that supports a rich
feature set. The core includes a CPU, memory, clocks, and
configurable GPIO (General Purpose IO).

The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture micropro­cessor. The CPU utilizes an interrupt controller with up to 20
vectors, to simplify programming of real-time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).

Memory encompasses 16K of Flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash utilizes four protection levels on
blocks of 64 bytes, allowing customized software IP protection.

enCoRe III incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to 8%
over temperature and voltage. The 24 MHz IMO is doubled to 48
MHz for use by the digital system, if needed. The 48 MHz clock
is required to clock the USB block and must be enabled for USB

Document 38-08036 Rev. *C Page 2 of 30

Digital configurations that can be built from the blocks include
those listed below.

■

PWMs, Timers and Counters (8-bit and 16-bit)

■

UART 8-bit with selectable parity

■

SPI master and slave

■

I2C Master

■

RF Interface: Interface to Cypress CYFI Radio

The digital blocks is connected to any GPIO through a series of
global buses that can route any signal to any pin. The buses also
allow for signal multiplexing and for performing logic operations.
This configurability frees your designs from the constraints of a
fixed peripheral controller.

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CY7C64215

The Analog System

ACB00 ACB01

Block
Ar r ay

Array Input

Configuration

ACI1[1:0]

ASD20

ACI0[1:0]

P0[6]

P0[4]

P0[2]
P0[0]

P2[2]
P2[0]

P2[6]

P2[4]

RefIn

AGNDIn

P0[7]

P0[5]

P0[3]
P0[1]

P2[3]

P2[1]

Reference

Generators

AGNDIn
RefIn
Bandgap

RefHi
RefLo
AGND

ASD11

ASC21

ASC10

Interface to

Di g it al System

M8C I n ter face (Addr ess B u s, D ata B us, Etc. )

Analog Reference

All IO

(Except Po r t 7)

Analog

Mux Bus

The Analog System is composed of six configurable blocks,
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and are
customized to support specific application requirements.
enCoRe III analog function supports the Analog-to-digital
converters (with 6 to 14-bit resolution, selectable as Incremental,
and Delta Sigma) and programmable threshold comparator).

Analog blocks are arranged in two columns of three, with each
column comprising one CT (Continuous Time - AC B00 or AC
B01) and two SC (Switched Capacitor - ASC10 and ASD20 or
ASD11 and ASC21) blocks, as shown in Figure 2.

Figure 2. Analog System Block Diagram

The Analog Multiplexer System

The Analog Mux Bus can connect to every GPIO pin in ports 0–5.
Pins which are connected to the bus individually or in any combi­nation. The bus also connects to the analog system for analysis
with comparators and analog-to-digital converters. It is split into
two sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.

Additional System Resources

System Resources provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power-on reset. Brief
statements describing the merits of each resource follow.

■

Full-Speed USB (12 Mbps) with five configurable endpoints and
256 bytes of RAM. No external components required except
two series resistors.

■

Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math and
digital filters.

■

The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.

■

Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks are routed to
both the digital and analog systems.

■

The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.

■

Low Voltage Detection (LVD) interrupts can signal the appli­cation of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.

enCoRe III Device Characteristics

enCoRe III devices have four digital blocks and six analog
blocks. The following table lists the resources available for
specific enCoRe III device.

Document 38-08036 Rev. *C Page 3 of 30

Table 1. enCoRe III Device Characteristics

Part

Number

CY7C64215

-28PVXC
CY7C64215

-56LFXC

Digital IODigital

Rows

Inputs

Digital

Blocks

Analog

Analog

Outputs

Blocks

Analog

Analog

Columns

up to 221 4 22 2 2 6 1K 16K

up to 501 4 48 2 2 6 1K 16K

Size

SRAM

Size

Flash

Getting Started

The quickest path to understanding enCoRe III silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the enCoRe III integrated circuit and presents specific pin,
register, and electrical specifications. enCoRe III is based on the
architecture of the CY8C24794. For in-depth information, along

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CY7C64215

with detailed programming information, reference the PSoC™

Commands

Results

PSoC

TM

Designer

Core

Engine

PSoC

Configuration

Sheet

M a nufacturing

Inf ormation

File

Dev ice

Database

Importable

Des ign

Database

Dev ice

Programmer

Graphical Designer

Interface

Context

Sensitive

Help

Emulation

Pod

In- Circuit
Em ulator

Project

Database

Application

Database

User

Modules

Library

PSoC

TM

Designer

Mixed-Signal Array Technical Reference Manual.
For up-to-date Ordering, Packaging, and Electrical Specification

information, reference the latest enCoRe III device data sheets
on the web at http://www.cypress.com.

Development Kits

Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
enCoRe III development. Go to the Cypress Online Store web
site at http://www.cypress.com, click the Online Store shopping
cart icon at the bottom of the web page, and click USB (Universal
Serial Bus) to view a current list of available items.

Development Tools

PSoC Designer is a Microsoft® Windows® based, integrated
development environment for enCoRe III. The PSoC Designer
IDE and application runs on Windows NT 4.0, Windows 2000,
Windows Millennium (Me), or Windows XP. (Refer to the PSoC
Designer Functional Flow diagram below).

PSoC Designer helps the customer to select an operating config­uration for the enCoRe III, write application code that uses the
enCoRe III, and debug the application. This system provides
design database management by project, an integrated
debugger with In-Circuit Emulator, in-system programming
support, and the CYASM macro assembler for the CPUs. PSoC
Designer also supports a high-level C language compiler
developed specifically for the devices in the family.

Figure 3. PSoC Designer Subsystems

PSoC Designer Software Subsystems

Device Editor

The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the enCoRe III blocks. Examples of user modules are
ADCs, SPIM, UART, and PWMs.

The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configu­ration allows for changing configurations at run time.

PSoC Designer sets up power-on initialization tables for selected
enCoRe III block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of enCoRe III block configurations at run
time. PSoC Designer can print out a configuration sheet for a
given project configuration for use during application
programming in conjunction with the Device Data Sheet. Once
the framework is generated, the user can add appli­cation-specific code to flesh out the framework. It is also possible
to change the selected components and regenerate the
framework.

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Application Editor

In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.

Assembler. The macro assembler allows the assembly code to
merge seamlessly with C code. The link libraries automatically
use absolute addressing or is compiled in relative mode, and
linked with other software modules to get absolute addressing.

C Language Compiler. A C language compiler is available that
supports the enCoRe III family of devices. Even if you have never
worked in the C language before, the product quickly allows you
to create complete C programs for the enCoRe III devices.

The embedded, optimizing C compiler provides all the features
of C tailored to the enCoRe III architecture. It comes complete
with embedded libraries providing port and bus operations,
standard keypad and display support, and extended math
functionality.

Debugger

The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the enCoRe
III device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break­points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE Cube is available for devel­opment support. This hardware has the capability to program
single devices.

The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal which operates with
all enCoRe III devices.

Designing with User Modules

The development process for the enCoRe III device differs from
that of a traditional fixed-function microprocessor. The config­urable analog and digital hardware blocks give the enCoRe III
architecture a unique flexibility that pays dividends in managing
specification change during development and by lowering
inventory costs. These configurable resources, called enCoRe
III Blocks, have the ability to implement a wide variety of
user-selectable functions. Each block has several registers that
determine its function and connectivity to other blocks, multi­plexers, buses and to the IO pins. Iterative development cycles
permit you to adapt the hardware and software. This substan­tially lowers the risk of having to select a different part to meet
the final design requirements.

To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral func tions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties.

The user module library contains the following digital and analog
module designs:

■

Analog Blocks

❐

Incremental ADC (ADCINC)

❐

Delta Sigma ADC (DelSig)

❐

Programmable Threshold Comparator (CMPPRG)

■

Digital Blocks

❐

Counters: 8-bit and 16-bit (Counter8 and Counter 16)

❐

PWMs: 8-bit and 16-bit (PWM8 and PWM16)

❐

Timers: 8-bit and 16-bit (Timer8 and Timer 16)

❐

I2C Master (I2Cm)

❐

SPI Master (SPIM)

❐

SPI Slave (SPIS)

❐

Full Duplex UART (UART)

❐

RF (CYFISNP and CYFISPI)

■

System Resources

❐

Protocols:

• USBFS

• I2C Bootheader (Boothdr I

• USB Bootheader (BoothdrUSBFS)

• USBUART

❐

Digital System Resources

•E2PROM

•LCD

•LED

• 7-segment LED (LED7SEG)

• Shadow Registers (SHADOWREG)

• Sleep Timer

2

C)

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Each user module establishes the basic register settings that

Debugger

Interface

to ICE

Application Editor

Device Editor

Project

M anage r

Source

Code

Editor

Storage

I nspector

User

Module

Selection

Placement

and

Parameter

-ization

Generate
Application

Build
All

Event &

Breakpoint

Manager

Build

Manager

Source

Code

Generator

implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
of resolution. The user module parameters permit the desi gner
to establish the pulse width and duty cycle. User modules also
provide tested software to cut development time. The user
module application programming interface (API) provides
high-level functions to control and respond to hardware events
at run-time. The API also provides optional interrupt service
routines that is adapted as needed.

The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.

The development process starts when you open a new project
and bring up the Device Editor/Chip Layout View, a graphical
user interface (GUI) for configuring the hardware. You pick the
user modules you need for your project and map them onto the
PSoC blocks with point-and-click simplicity. Next, you build
signal chains by interconnecting user modules to each other and
the IO pins. At this stage, you also configure the clock source
connections and enter parameter values directly or by selecting
values from drop-down menus. When you are ready to test the
hardware configuration or move on to developing code for the
project, you perform the “Generate Application” step. This
causes PSoC Designer to generate source code that automati ­cally configures the device to your specification and provides the
high-level user module API functions.

Figure 4. User Module and Source Code Develo pment Flows

The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open the project source code files (including
all generated code files) from a hierarchal view. The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.

The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE CUBE)
where it runs at full speed. Debugger capabilities rival those of
systems costing many times more. In addition to traditional
single-step, run-to-breakpoint and watch-variable features, the
Debugger provides a large trace buffer and allows you define
complex breakpoint events that include monitoring address and
data bus values, memory locations and external signals.

Document 38-08036 Rev. *C Page 6 of 30

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Document Conventions

Acronyms Used

The following table lists the acronyms that are used in this
document.

Acronym Description

AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only

memory
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human body model
LSb least-significant bit
LVD low voltage detect
MSb most-significan t bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision power on reset
PSoC Programmable System-on-Chip™
PWM pulse width modulator
SC switched capacitor
SRAM static random access memory
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset

Units of Measure

A units of measure table is located in the Electrical Specifications
section. Table 5 on page 13 lists all the abbreviations used to
measure the enCoRe III devices.

Numeric Naming

Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (For example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.

Document 38-08036 Rev. *C Page 7 of 30

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MLF

(Top View)

A, I, M, P2[3]
A, I, M, P2[1]

M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]

1
2

3
4
5
6
7

8
9
10

11
12
13
14

M, I2C SCL, P1[7]

M, I2C SD A, P1[5]

M, P1[3]

M, I2C SCL, P1[1]

Vss

D+

D-

Vdd

P7[7]

P7[0]

M, I 2C SD A, P1[0]

M, P1[2]

M, P1[4]

M, P1[6]

15161718192021

22

2324252627

28

P2[4], M

P2[6], M

P0[0], A, I, M

P0[2], A, I, M

P0[4], A, I, M

P0[6], A, I, M

Vdd

Vss

P0[7], A, I, M

P0[5], A, IO, M

P0[3], A, IO, M

P0[1], A, I, M

P2[7], M

P2[5], M

43

44

45

46

47

48

49

50

51

52

53

54

55

56

P2[2], A, I, M
P2[0], A, I, M
P4[6], M
P4[4], M
P4[2], M
P4[0], M
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M

42

41
40
39
38
37
36

35

34
33
32
31
30
29

56-Pin Part Pinout

The CY7C64215 enCoRe III device is available in a 56-pin package which is listed and illustrated in the following table. Every port pin
(labeled “P”) is capable of Digital IO. However, Vss and Vdd are not capable of Digital IO.

Table 2. 56-Pin Part Pinout (MLF*)

Pin

No.

Type

Digital Analog

Name Description

1 IO I, M P2[3] Direct switched capacitor block input.
2 IO I, M P2[1] Direct switched capacitor block input.
3 IO M P4[7]
4 IO M P4[5]
5 IO M P4[3]
6 IO M P4[1]
7 IO M P3[7]
8 IO M P3[5]

9 IO M P3[3]
10 IO M P3[1]
11 IO M P5[7]
12 IO M P5[5]
13 IO M P5[3]
14 IO M P5[1]
15 IO M P1[7] I2C Serial Clock (SCL).
16 IO M P1[5] I2C Serial Data (SDA).
17 IO M P1[3]
18 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK.
19 Power Vss Ground connection.
20 USB D+
21 USB D­22 Power Vdd Supply voltage.
23 IO P7[7]
24 IO P7[0]
25 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA.
26 IO M P1[2]
27 IO M P1[4]
28 IO M P1[6]
29 IO M P5[0]

Pin
No.

31 IO M P5[4] 44 IO M P2[6] External Voltage Reference (VREF) input.
32 IO M P5[6] 45 IO I, M P0[0] Analog column mux input.
33 IO M P3[0] 46 IO I, M P0[2] Analog column mux input and column output.
34 IO M P3[2] 47 IO I, M P0[4] Analog column mux input and column output.
35 IO M P3[4] 48 IO I, M P0[6] Analog column mux input.
36 IO M P3[6] 49 Power Vdd Supply voltage.
37 IO M P4[0] 50 Power Vss Ground connection.
38 IO M P4[2] 51 IO I, M P0[7] Analog column mux input.
39 IO M P4[4] 52 IO IO, M P0[5] Analog column mux input and column output
40 IO M P4[6] 53 IO IO, M P0[3] Analog column mux input and column output.
41 IO I, M P2[0] Direct switched capacitor block input. 54 IO I, M P0[1] A nalog column mux input.
42 IO I, M P2[2] Direct switched capacitor block input. 55 IO M P2[7]
43 IO M P2[4] External Analog Ground (AGND) in-

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* The MLF package has a center pad that must be connected to ground (Vss).

put.

56 IO MP2[5]

CY7C64215 56-Pin enCoRe III Device

Type

Name Description30 IO M P5[2] Digital Analog

Document 38-08036 Rev. *C Page 8 of 30

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CY7C64215

28-Pin Part Pinout

SSOP

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P2[4]
P2[2], AI
P2[0], AI
P1[6]
P1[4]
P1[2]
P1[0], I2C SDA
Vdd
D-

Vss

AI, P0[7]
AIO, P0[5]
AIO, P0[3]

AI, P0[1]

P2[5]

AI, P 2[3]

AI, P2[1]

I2C SCL, P1[7]

I2C SDA, P1[5]

P1[3]

I2C SCL, P1[1]

Vss

D+

The CY7C64215 enCoRe III device is available in a 28-pin package which is listed and illustrated in the following table. Every port pin
(labeled with a “P”) is capable of Digital IO. However, Vss and Vdd are not capable of Digital IO.

Table 3. 28-Pin Part Pinout (SSOP)

Pin
No.

1 Power GND Ground connection
2 IO I, M P0[7] Analog column mux input.
3 IO IO,M P0[5] Analog column mux input and column

4 IO IO,M P0[3] Analog column mux input and column
5 IO I,M P0[1] Analog column mux input.

6 IO M P2[5]
7 IO M P2[3] Direct switched capacitor block input.
8 IO M P2[1] Direct switched capacitor block input.

9 IO M P1[7] I2C Serial Clock (SCL).
10 IO M P1[5] I2C Serial Data (SDA).
11 IO M P1[3]
12 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK.
13 Power GND Ground connection
14 USB D+
15 USB D­16 Power Vdd Supply voltage.
17 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA.
18 IO M P1[2]
19 IO M P1[4]
20 IO M P1[6]
21 IO M P2[0] Direct switched capacitor block input.
22 IO M P2[2] Direct switched capacitor block input.
23 IO M P2[4] External Analog Ground (AGND) input.
24 IO M P0[0] Analog column mux input.
25 IO M P0[2] Analog column mux input and column

26 IO M P0[4] Analog column mux input and column
27 IO M P0[6] Analog column mux input.

28 Power Vdd Supply voltage.

Type

Digital Analog

Name Description

output
output.

output.
output.

CY7C64215 28-Pin enCoRe III Device

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

* The MLF package has a center pad that must be connected to ground (Vss).

Document 38-08036 Rev. *C Page 9 of 30

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CY7C64215

Register Reference

The register conventions specific to this section are listed in the
following table

Table 4. Register Conventions

Convention Description

R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific

.

Register Mapping Tables

The enCoRe III device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.

Note In the following register mapping tables, blank fields are
Reserved and should not be accessed.

Document 38-08036 Rev. *C Page 10 of 30

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Register Map Bank 0 Table: User Space

Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access

PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2

PRT7DR
PRT7IE
PRT7GS
PRT7DM2
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0

Blank fields are Reserved and should not be accessed. # Access is bit specific.

00 RW PMA0_DR 40 RW
01 RW PMA1_DR 41 RW
02 RW PMA2_DR 42 RW
03 RW PMA3_DR 43 RW
04 RW PMA4_DR 44 RW
05 RW PMA5_DR 45 RW
06 RW PMA6_DR 46 RW
07 RW PMA7_DR 47 RW
08 RW USB_SOF0 48 R 88 C8
09 RW USB_SOF1 49 R 89 C9
0A RW USB_CR0 4A RW 8A CA
0B RW USBIO_CR0 4B # 8B CB
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18 EP0_DR0 58 RW 98
19 EP0_DR1 59 RW 99
1A EP0_DR2 5A RW 9A
1B EP0_DR3 5B RW 9B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F

RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW

RW
RW
RW
RW
# AMX_IN
W AMUXCFG
RW
# ARF_CR
# CMP_CR0
W ASY_CR
RW CMP_CR1
#
#
W
RW
#
# TMP_DR0
W TMP_DR1
RW TMP_DR2
# TMP_DR3

USBIO_CR1 4C RW 8C CC

EP1_CNT1 4E # 8E CE
EP1_CNT 4F RW 8F CF
EP2_CNT1 50 #
EP2_CNT 51 RW
EP3_CNT1 52 #
EP3_CNT 53 RW
EP4_CNT1 54 #
EP4_CNT 55 RW
EP0_CR 56 #
EP0_CNT 57 #

EP0_DR4 5C RW 9C
EP0_DR5 5D RW 9D
EP0_DR6 5E RW 9E
EP0_DR7 5F RW 9F

ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2

4D 8D CD

60
61
62 A2
63
64
65
66
67 A7
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78 B8 F8
79 B9 F9
7A BA FA
7B BB FB
7C BC FC
7D BD
7E BE
7F BF

RW
RW

RW
#
#
RW

RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW

ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3

ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3

MUL1_X
MUL1_Y
MUL1_DH
MUL1_DL
ACC1_DR1
ACC1_DR0
ACC1_DR3
ACC1_DR2
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1

80
81
82
83
84
85
86
87

90
91
92
93
94
95
96
97

A0
A1

A3
A4
A5
A6

A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7

RW
RW
RW
RW
RW
RW
RW
RW

RW CUR_PP
RW STK_PP
RW
RW IDX_PP
RW MVR_PP
RW MVW_PP
RW I2C_CFG
RW I2C_SCR

W
W
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW

I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2

CPU_F

DAC_D
CPU_SCR1
CPU_SCR0

C0
C1
C2
C3
C4
C5
C6
C7

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7

FD
FE
FF

RW
RW

RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW

RL

RW
#
#

Document 38-08036 Rev. *C Page 11 of 30

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CY7C64215

Register Map Bank 1 Table: Configuration Space

Name

PRT0DM0 00 RW PMA0_WA 40 RW ASC10CR0 80 RW USBIO_CR2 C0 RW
PRT0DM1 01 RW PMA1_WA 41 RW ASC10CR1 81 RW USB_CR1 C1 #
PRT0IC0 02 RW PMA2_WA 42 RW ASC10CR2 82 RW
PRT0IC1 03 RW PMA3_WA 43 RW ASC10CR3 83 RW
PRT1DM0 04 RW PMA4_WA 44 RW ASD11CR0 84 RW EP1_CR0 C4 #
PRT1DM1 05 RW PMA5_WA 45 RW ASD11CR1 85 RW EP2_CR0 C5 #
PRT1IC0 06 RW PMA6_WA 46 RW ASD11CR2 86 RW EP3_CR0 C6 #
PRT1IC1 07 RW PMA7_WA 47 RW ASD11CR3 87 RW EP4_CR0 C7 #
PRT2DM0 08 RW 48 88 C8
PRT2DM1 09 RW 49 89 C9
PRT2IC0 0A RW 4A 8A CA
PRT2IC1 0B RW 4B 8B CB
PRT3DM0 0C RW 4C 8C CC
PRT3DM1 0D RW 4D 8D CD
PRT3IC0 0E RW 4E 8E CE
PRT3IC1 0F RW 4F 8F CF
PRT4DM0 10 RW PMA0_RA 50 RW 90 GDI_O_IN D0 RW
PRT4DM1 11 RW PMA1_RA 51 RW ASD20CR1 91 RW GDI_E_IN D1 RW
PRT4IC0 12 RW PMA2_RA 52 RW ASD20CR2 92 RW GDI_O_OU D2 RW
PRT4IC1 13 RW PMA3_RA 53 RW ASD20CR3 93 RW GDI_E_OU D3 RW
PRT5DM0 14 RW PMA4_RA 54 RW ASC21CR0 94 RW D4
PRT5DM1 15 RW PMA5_RA 55 RW ASC21CR1 95 RW D5
PRT5IC0 16 RW PMA6_RA 56 RW ASC21CR2 96 RW D6
PRT5IC1 17 RW PMA7_RA 57 RW ASC21CR3 97 RW D7

PRT7DM0 1C RW 5C 9C DC
PRT7DM1 1D RW 5D 9D OSC_GO_EN DD RW
PRT7IC0 1E RW 5E 9E OSC_CR4 DE RW
PRT7IC1 1F RW 5F 9F OSC_CR3 DF RW
DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW
DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW
DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW

DBB01FN 24 RW CMP_GO_EN 64 RW A4 VLT_CMP E4 R
DBB01IN 25 RW 65 RW A5 E5
DBB01OU 26 RW AMD_CR1 66 RW A6 E6

DCB02FN 28 RW 68 A8 IMO_TR E8 W
DCB02IN 29 RW 69 A9 ILO_TR E9 W
DCB02OU 2A RW 6A AA BDG_TR EA RW

DCB03FN 2C RW TMP_DR0 6C RW AC MUX_CR4 EC RW
DCB03IN 2D RW TMP_DR1 6D RW AD MUX_CR5 ED RW
DCB03OU 2E RW TMP_DR2 6E RW AE EE

Blank fields are Reserved and should not be accessed. # Access is bit specific.

Addr

(1,Hex)

18 58 98 MUX_CR0 D8 RW
19 59 99 MUX_CR1 D9 RW
1A 5A 9A MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW

23 AMD_CR0 63 RW A3 VLT_CR E3 RW

27 ALT_CR0 67 RW A7 E7

2B 6B AB ECO_TR EB W

2F TMP_DR3 6F RW AF EF
30 ACB00CR3 70 RW RDI0RI B0 RW F0
31 ACB00CR0 71 RW RDI0SYN B1 RW F1
32 ACB00CR1 72 RW RDI0IS B2 RW F2
33 ACB00CR2 73 RW RDI0LT0 B3 RW F3
34 ACB01CR3 74 RW RDI0LT1 B4 RW F4
35 ACB01CR0 75 RW RDI0RO0 B5 RW F5
36 ACB01CR1 76 RW RDI0RO1 B6 RW F6
37 ACB01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39
3A
3B 7B BB FB
3C
3D
3E
3F 7F BF CPU_SCR0 FF #

Access Name

Addr

(1,Hex)

79 B9 F9
7A BA FA

7C BC FC
7D BD DAC_CR FD RW
7E BE CPU_SCR1 FE #

Access Name

Addr

(1,Hex)

Access Name

Addr

(1,Hex)

Access

Document 38-08036 Rev. *C Page 12 of 30

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CY7C64215

Electrical Specifications

CPU Frequency

Vdd Voltage (V)

5.25

4.35

3.60

3.00

4.75

93kHz 12MHz 24MHz

Valid operating region

Valid operating region

Valid operating region

[1]

Note

1. This is a valid operating region for the CPU, but USB hardware is non-functional in the voltage range from 3.60V – 4.35V .

This section presents the DC and AC electrical specifications of the CY7C64215 enCo Re III. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com.

Specifications are valid for 0°C <
12 MHz are valid for 0°C <

TA < 70°C and TJ < 100°C, except where noted. Specifications for devices running at greater than

TA < 70°C and TJ < 82°C.

Figure 5. Voltage versus CPU Frequency

The following table lists the units of measure that are used in this section.

Table 5. Units of Measure

Symbol Unit of Measure Symbol Unit of Measure

°C degree Celsius μW microwatts
dB decibels mA milliampere

fF femto farad ms millisecond
Hz hertz mV millivolts
KB 1024 bytes nA nanoampere

Kbit 1024 bits ns nanosecond
kHz kilohertz nV nanovolts

kΩ kilohm W ohm

MHz megahertz pA picoampere

MΩ megaohm pF picofarad

μA microampere pp peak-to-peak
μF microfarad ppm parts per million
μH microhenry ps picosecond
μs microsecond sps s amples per second

Document 38-08036 Rev. *C Page 13 of 30

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CY7C64215

Table 5. Units of Measure (continued)

Symbol Unit of Measure Symbol Unit of Measure

μV microvolts s sigma: one standard deviation

μVrms microvolts root-mean-square V volts

Absolute Maximum Ratings

Table 6. Absolute Maximum Ratings

Parameter Description Min Typ Max Unit Notes

T

T

STG

A

Storage Temperature –55 – +100 °C Higher storage temperatures

reduces data retention time.

Ambient Temperature with Power Applied 0 – +70 °C
Vdd Supply Voltage on Vdd Relative to Vss –0.5 – +6.0 V
V

IO

V

IO2

I

MIO

I

MAIO

DC Input Voltage Vss – 0.5 – Vdd + 0.5 V

DC Voltage Applied to Tri-state Vss – 0.5 – Vdd + 0.5 V

Maximum Current into any Port Pin –25 – +50 mA

Maximum Current into any Port Pin

–50 – +50 mA

Configured as Analog Driver
ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD.
LU Latch Up Current – – 200 mA

Operating Temperature

Table 7. Operating Temperature

Parameter Description Min Typ Max Unit Notes

T

A

T

J

Ambient Temperature 0 – +70 °C
Junction Temperature 0 – +88 °C The temperature rise from

ambient to junction is
package specific. See

“Thermal Impedance” on

page 28. The user must limit
the power consumption to
comply with this
requirement.

Document 38-08036 Rev. *C Page 14 of 30

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CY7C64215

DC Electrical Characteristics

Note

2. Standby current incl udes all functions (POR , L VD, WDT, Sleep Time) needed for reliable system ope ration. This should be compared with devices that have similar
functions enabled.

DC Chip-Level Specifications

The following table lists guaranteed maximum and min imum specific ations for the voltage and tem perature ranges: 4.75V to 5.25 V
and 0°C <
for design guidance only.

Table 8. DC Chip-Level Specifications

Parameter Description Min Typ Max Unit Notes

Vdd Supply Voltage 3.0 – 5.25 V See DC POR and LVD specifications, Table

I

DD5

I

DD3

I

SB

I

SBH

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are

16 on page 19. USB hardware is not

functional when Vdd is between 3.6V - 4.35V.

Supply Current, IMO = 24 MHz (5V) – 14 27 mA Conditions are Vdd = 5.0V, TA = 25°C, CPU

= 3 MHz, SYSCLK doubler disabled, VC1 =

1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz,
analog power = off.

Supply Current, IMO = 24 MHz (3.3V) – 8 14 mA Conditions are Vdd = 3.3V, TA = 25°C, CPU

= 3 MHz, SYSCLK doubler disabled, VC1 =

1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz,
analog power = off.

Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT.

[2]

– 3 6.5 μA Conditions are with internal slow speed oscil-

lator, Vdd = 3.3V, 0°C <

TA < 55°C, analog

power = off.

Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT at high temperature.

[2]

– 4 25 μA Conditions are with internal slow speed oscil-

lator, Vdd = 3.3V, 55°C < T
power = off.

< 70°C, analog

A

DC General Purpose IO Specifications

The following table lists guaranteed maximum and min imum specific ations for the voltage and tem perature ranges: 4.75V to 5.25 V
and 0°C <

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are

for design guidance only.

Table 9. DC GPIO Specifications

Parameter Description Min Typ Max Unit Notes

R

PU

R

PD

V

OH

Pull-Up Resistor 4 5.6 8 kΩ
Pull-Down Resistor 4 5.6 8 kΩ
High Output Level Vdd – 1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4

on even port pins (for example, P0[2], P1[4]), 4 on
odd port pins (for example, P0[3], P1[5])). 80 mA
maximum combined IOH budget.

V

OL

Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4

on even port pins (for example, P0[2], P1[4]), 4 on
odd port pins (for example, P0[3], P1[5])). 150 mA

maximum combined IOL budget.
V
V
V
I
C
C

IL
IH
H

IL

IN
OUT

Input Low Level – – 0.8 V Vdd = 3.0 to 5.2 5.
Input High Level 2.1 – V Vdd = 3.0 to 5.25.
Input Hysteresis – 60 – mV
Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA.
Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent. Temp = 25°C.
Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dependent. Temp = 25°C.

Document 38-08036 Rev. *C Page 15 of 30

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CY7C64215

DC Full-Speed USB Specifications

The following table lists guaranteed maximum and min imum specific ations for the voltage and tem perature ranges: 4.75V to 5.25 V
and 0°C <

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are

for design guidance only.

Table 10. DC Full-Speed (12 Mbps) USB Specifications

Parameter Description Min Typ Max Unit Notes

USB Interface

V
V
V
C
I

IO

R
V

V

V

Z
V

DI
CM
SE

IN

EXT

UOH

UOHI

UOL

O
CRS

Differential Input Sensitivity 0.2 – – V | (D+) – (D–) |
Differential Input Common Mode Range 0.8 – 2.5 V
Single Ended Receiver Threshold 0.8 – 2.0 V
Transceiver Capacitance – – 20 pF
High-Z State Data Line Leakage –10 – 10 μA0V < VIN < 3.3V.
External USB Series Resistor 23 – 25 Ω In series with each USB pin.
Static Output High, Driven 2.8 – 3.6 V 15 k Ω ± 5% to Ground . Internal pull-up

enabled.

Static Output High, Idle 2.7 – 3.6 V 15 kΩ ± 5% to Ground. Internal pull-up

enabled.

Static Output Low – – 0.3 V 15 kΩ ± 5% to Ground . Internal pull-up

enabled.

USB Driver Output Impedance 28 – 44 Ω Includi ng R

Resistor.

EXT

D+/D– Crossover Voltage 1.3 – 2.0 V

DC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25 V
and 0°C <

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are

for design guidance only.

Ta ble 11. 5V DC Analog Output Buffer Specifications

Parameter Description Min Typ Max Unit Notes

V

OSOB

TCV

OSOB

V

CMOB

R

OUTOB

V

OHIGHOB

V

OLOWOB

I

SOB

PSRR

Input Offset Voltage (Absolute Value) – 3 12 mV
Average Input Offset Voltage Drift – +6 – μV/°C
Common-Mode Input Voltage Range 0.5 – Vdd - 1.0 V
Output Resistance

Power = Low
Power = High

–
–

0.6

0.6

–
–

W
W

High Output Voltage Swing
(Load = 32 ohms to Vdd/2)
Power = Low
Power = High

0.5 x Vdd + 1.1

0.5 x Vdd

+ 1.1

–
–

–
–

V
V

Low Output Voltage Swing
(Load = 32 ohms to Vdd/2)
Power = Low
Power = High

–
–

––0.5 x Vdd – 1.3

0.5 x Vdd

– 1.3

V
V

Supply Current Including Bias Cell (No Load)
Power = Low
Power = High

Supply Voltage Rejection Ratio 53 64 – dB (0.5 x Vdd – 1.3) <

OB

–
–

1.1

2.6

5.1

8.8

mA
mA

V

< (Vdd – 2.3).

OUT

Document 38-08036 Rev. *C Page 16 of 30

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Table 12. 3.3V DC Analog Output Buffer Specifications

Parameter Description Min Typ Max Unit Notes

V

OSOB

TCV

OSOB

V

CMOB

R

OUTOB

V

OHIGHOB

V

OLOWOB

I

SOB

PSRR

Input Offset Voltage (Absolute Value) – 3 12 mV
Average Input Offset Voltage Drift – +6 – μV/°C
Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 V
Output Resistance

Power = Low
Power = High

–
–

1
1

–
–

W
W

High Output Voltage Swing
(Load = 1K ohms to Vdd/2)
Power = Low
Power = High

0.5 x Vdd + 1.0

0.5 x Vdd

+ 1.0

–
–

–
–

V
V

Low Output Voltage Swing
(Load = 1K ohms to Vdd/2)
Power = Low
Power = High

–
–

––0.5 x Vdd – 1.0

0.5 x Vdd

– 1.0

V
V

Supply Current Including Bias Cell (No Load)
Power = Low
Power = High –

Supply Voltage Rejection Ratio 34 64 – dB (0.5 x Vdd – 1.0) < V

OB

0.8

2.0

2.0

4.3

mA
mA

(0.5 x Vdd + 0.9).

<

OUT

DC Analog Reference Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25 V
and 0°C <

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are

for design guidance only.

Table 13. 5V DC Analog Reference Specifications

Parameter Description Min Typ Max Unit

BG Bandgap Voltage Reference 1.28 1.30 1.32 V
–AGND = Vdd/2
– AGND = 2 x BandGap

[3]

[3]

– AGND = P2[4] (P2[4] = Vdd/2)
– AGND = BandGap
– AGND = 1.6 x BandGap
– AGND Block to Block Variation

(AGND = Vdd/2)

[3]

[3]

[3]

[3]

Vdd/2 – 0.04 Vdd/2 – 0.01 Vdd/2 + 0.007 V

2 x BG – 0.048 2 x BG – 0.030 2 x BG + 0.024 V

P2[4] – 0.011 P2[4] P2[4] + 0.011 V

BG – 0.009 BG + 0.008 BG + 0.016 V

1.6 x BG – 0.022 1.6 x BG – 0.010 1.6 x BG + 0.018 V
–0.034 0.000 0.034 V

– RefHi = Vdd/2 + BandGap Vdd/2 + BG – 0.10 Vdd/2 + BG Vdd/2 + BG + 0.10 V
– RefHi = 3 x BandGap 3 x BG – 0.06 3 x BG 3 x BG + 0.06 V
– RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] – 0.1 13 2 x BG + P2[6] – 0.018 2 x BG + P2[6] + 0.077 V
– RefHi = P2[4] + BandGap (P2[4] = Vdd/2) P2[4] + BG – 0.130 P2[4] + BG – 0.016 P2[4] + BG + 0.098 V
– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6]

P2[4] + P2[6] – 0.133 P2[4] + P2[6] – 0.016 P2[4] + P2[6]+ 0.100 V

= 1.3V)

– RefHi = 3.2 x BandGap 3.2 x BG – 0.112 3.2 x BG 3.2 x BG + 0.076 V

+

– RefLo = Vdd/2 – BandGap Vdd/2 – BG – 0.04 Vdd/2 – BG

0.024 Vdd/2 – BG + 0.04 V
– RefLo = BandGap BG – 0.06 BG BG + 0.06 V
– RefLo = 2 x BandGap – P2[6] (P2[6] = 1.3V) 2 x BG – P2[6] – 0.084 2 x BG – P2[6] + 0.025 2 x BG – P2[6] + 0.134 V
– RefLo = P2[4] – BandGap (P2[4] = Vdd/2) P2[4] – BG – 0.056 P2[4] – BG + 0.026 P2[4] – BG + 0.107 V
– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] =

P2[4] – P2[6] – 0.057 P2[4] – P2[6] + 0.026 P2[4] – P2[6] + 0.110 V

1.3V)

Note

3. AGND tolerance includes the offsets of the local buffer in the enCoRe III block. Bandgap voltage is 1.3V ± 0.02V.

Document 38-08036 Rev. *C Page 17 of 30

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Table 14. 3.3V DC Analog Reference Specifications

Parameter Description Min Typ Max Unit

BG Bandgap Voltage Reference 1.28 1.30 1.32 V
– AGND = Vdd/2
– AGND = 2 x BandGap

[3]

[3]

Vdd/2 – 0.03 Vdd/2 – 0.01 Vdd/2 + 0.005 V

Not Allowed
– AGND = P2[4] (P2[4] = Vdd/2) P2[4] – 0.008 P2[4] + 0.001 P2[4] + 0.009 V
– AGND = BandGap
– AGND = 1.6 x BandGap
– AGND Column to Column Variation (AGND =

Vdd/2)

[3]

[3]

[3]

1.6 x BG – 0.027 1.6 x BG – 0.010 1.6 x BG + 0.018 V
–0.034 0.000 0.034 V

BG – 0.009 BG + 0.005 BG + 0.015 V

– RefHi = Vdd/2 + BandGap Not Allowed
– RefHi = 3 x BandGap Not Allowed
– RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) Not Allowed
– RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Not Allowed
– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] – 0.075 P2[4] + P2[6] – 0.009 P2[4] + P2[6] + 0.057 V
– RefHi = 3.2 x BandGap Not Allowed
– RefLo = Vdd/2 – BandGap Not Allowed
– RefLo = BandGap Not Allowed
– RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed
– RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed
– RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] – P2[6] – 0.048 P2[4] – P2[6] + 0.022 P2[4] – P2[6] + 0.092 V

DC Analog enCoRe III Block Specifications

The following table lists guaranteed maximum and min imum specific ations for the voltage and tem perature ranges: 4.75V to 5.25 V
and 0°C <

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are

for design guidance only.

Table 15. DC Analog enCoRe III Block Specifications

Parameter Description Min Typ Max Unit Notes

R

CT

C

SC

Resistor Unit Value (Continuous Time) – 12.2 – kΩ
Capacitor Unit Value (Switched Capacitor) – 80 – fF

Document 38-08036 Rev. *C Page 18 of 30

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DC POR and LVD Specifications

Notes

4. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply

5. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply

The following table lists guaranteed maximum and min imum specific ations for the voltage and tem perature ranges: 4.75V to 5.25 V
and 0°C <

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typica l parameters apply to 5V or 3.3V at 2 5°C and are for

design guidance only.

Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Mixed-Signal Array Technical
Reference Manual for more information on the VLT_CR register.

Table 16. DC POR and LVD Specifications

Parameter Description Min Typ Max Unit Notes

Vdd Value for PPOR Trip (positive ramp)

V

PPOR0R

V

PPOR1R

V

PPOR2R

PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b

2.91

–

4.39

–

4.55

V
V
V

Vdd Value for PPOR Trip (negative ramp)

V

PPOR0

V

PPOR1

V

PPOR2

PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b

2.82

–

4.39

–

4.55

V
V
V

PPOR Hysteresis
V
V
V

V
V
V
V
V
V
V
V

PH0
PH1
PH2

LVD0
LVD1
LVD2
LVD3
LVD4
LVD5
LVD6
LVD7

PORLEV[1:0] = 00b

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

Vdd Value for LVD Trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

–
–
–

2.86

2.96

3.07

3.92

4.39

4.55

4.63

4.72

92

0
0

2.92

3.02

3.13

4.00

4.48

4.64

4.73

4.81

2.98

3.08

3.20

4.08

4.57

4.74

4.82

4.91

–
–
–

mV
mV
mV

[4]

V
V
V
V
V

[5]

V
V
V

Document 38-08036 Rev. *C Page 19 of 30

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DC Programming Specifications

Note

6. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each,
36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no
single block ever sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before
writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

The following table lists guaranteed maximum and min imum specific ations for the voltage and tem perature ranges: 4.75V to 5.25 V
and 0°C <

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are

for design guidance only.

Table 17. DC Programming Specifications

Parameter Description Min Typ Max Unit Notes

I

DDP

V

ILP

V

IHP

I

ILP

I

IHP

V

OLV

V

OHV

Flash
Flash
Flash

Supply Current During Programming or

– 15 30 mA

Verify
Input Low Voltage During Programming or

– – 0.8 V

Verify
Input High Voltage During Programming or

2.1 – – V

Verify
Input Current when Applying Vilp to P1[0]

– – 0.2 mA Driving internal pull-down resistor.

or P1[1] During Programming or Verify
Input Current when Applying Vihp to P1[0]

– – 1.5 mA Driving internal pull-down resistor.

or P1[1] During Programming or Verify
Output Low Voltage During Programming

– – Vss + 0.75 V

or Verify
Output High Voltage During Programming

Vdd – 1.0 – Vdd V

or Verify
Flash Endurance (per block) 50,000 – – – Erase/write cycles per block.

ENPB

Flash Endurance (total)

ENT

Flash Data Retention 10 – – Years

DR

[6]

1,800,000 – – – Erase/write cycles.

Document 38-08036 Rev. *C Page 20 of 30

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AC Electrical Characteristics

Jitter24M1

F

24M

Notes

7. 4.75V < Vdd < 5.25V.

8. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.

9. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSo C Microcontroller T rims for Dual V oltage-Rang e Operation” for information on t rimming for operation
at 3.3V.

10.See the individual user module data sheets for information on maximum frequencies for user modules.

AC Chip-Level Specifications

The following table lists guaranteed maximum and min imum specific ations for the voltage and tem perature ranges: 4.75V to 5.25 V
and 0°C <
for design guidance only.

Table 18. AC Chip-Level Specifications

Parameter Description Min Typ Max Unit Notes

F

IMO245V

F

IMO243V

F

IMOUSB

F

CPU1

F

CPU2

F

BLK5

F

BLK3

F

32K1

Jitter32k 32 kHz Period Jitter – 100 ns
Step24M 24 MHz Trim Step Size – 50 – kHz
Fout48M 48 MHz Output Frequency 46.08 48.0 49.92

Jitter24M1 24 MHz Period Jitter (IMO) Peak-to-Peak – 300 ps
F

MAX

T

RAMP

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are

Internal Main Oscillator Frequency for 24 MHz
(5V)

Internal Main Oscillator Frequency for 24 MHz
(3.3V)

Internal Main Oscillator Frequency with USB

23.04 24 24.96

22.08 24 25.92

23.94 24 24.06

[7, 8]

MHz Trimmed for 5V operation using

factory trim values.

[7,9]

MHz Trimmed for 3.3V operation

using factory trim values.

[8]

MHz 0°C < TA < 70°C
Frequency locking enabled and USB traffic
present.

10]

[7,8]

MHz

[8, 9]

MHz

[7, 8,

MHz Refer to the AC Digital Block

Specifications.

[8, 10]

MHz

CPU Frequency (5V Nominal) 0.93 24 24.96
CPU Frequency (3.3V Nominal) 0.93 12 12.96
Digital PSoC Block Frequency (5V Nominal) 0 48 49.92

Digital PSoC Block Frequency (3.3V Nominal) 0 24 25.92
Internal Low Speed Oscillator Frequency 15 32 64 kHz

[7, 9]

MHz Trimmed. Utilizing factory trim

values.

Maximum frequency of signal on row input or

– – 12.96 MHz

row output.
Supply Ramp Time 0 – – μs

Figure 6. 24 MHz Period Jitter (IMO) Timing Diagram

Document 38-08036 Rev. *C Page 21 of 30

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AC General Purpose IO Specifications

TFallF
TFallS

TRiseF
TRiseS

90%

10%

GPIO

Pin

Output

Voltage

The following table lists guaranteed maximum and min imum specific ations for the voltage and tem perature ranges: 4.75V to 5.25 V
and 0°C <

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are

for design guidance only.

Table 19. AC GPIO Specifications

Parameter Description Min Typ Max Unit Notes

F

GPIO

GPIO Operating Frequency 0 – 12 MHz Normal Strong Mode
TRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.5 to 5.25V, 10%–90%
TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.5 to 5.25V, 10%–90%
TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10%–90%
TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10%–90%

Figure 7. GPIO Timing Diagram

AC Full-Speed USB Specifications

The following table lists guaranteed maximum and min imum specific ations for the voltage and tem perature ranges: 4.75V to 5.25 V
and 0°C < TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are
for design guidance only.

Table 20. AC Full-Speed (12 Mbps) USB Specifications

Parameter Description Min Typ Max Unit Notes

T

RFS

T

FSS

T

RFMFS

T

DRATEFS

Transition Rise Time 4 – 20 ns For 50 pF load.
Transition Fall Time 4 – 20 ns For 50 pF load.
Rise/Fall Time Matching: (TR/TF)90– 111 % For 50 pF load.
Full-S p eed Data Rate 12 – 0.25% 12 12 + 0.25% Mbps

Document 38-08036 Rev. *C Page 22 of 30

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AC Digital Block Specifications

The following table lists guaranteed maximum and min imum specific ations for the voltage and tem perature ranges: 4.75V to 5.25 V
and 0°C <

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are

for design guidance only.

Table 21. AC Digital Block Specifications

Function Description Min Typ Max Unit Notes

Timer Capture Pulse Width 50

[11]

– – ns
Maximum Frequency, No Capture – – 49.92 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, With Capture – – 25.92 MHz

Counter En able Pulse Width 50

[11]

– – ns
Maximum Frequency, No Enable Input – – 49.92 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, Enable Input – – 25.92 MHz

Dead
Band

Kill Pulse Width:

Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 50
Disable Mode 50

[11]
[12]

– – ns

– – ns
Maximum Frequency – – 49.92 MHz 4.75V < Vdd < 5.25V.

CRCPRS

Maximum Input Clock Frequency – – 49.92 MHz 4.75V < Vdd < 5.25V.

(PRS
Mode)

CRCPRS

Maximum Input Clock Frequency – – 24.6 MHz

(CRC
Mode)

SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due to

2 x over clocking.

SPIS Maximum Input Clock Frequency – – 4.1 MHz

Width of SS_ Negated Between Trans-

50

[11]

– – ns
missions

Trans­mitter

Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz due to

8 x over clocking.

Receiver Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz due to

8 x over clocking.

AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25 V
and 0°C <

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are

for design guidance only.

Table 22. AC External Clock Specifications

Parameter Description Min Typ Max Unit Notes

F

OSCEXT

Frequency for USB Applications 23.94 24 24.06 MHz
– Duty Cycle 47
– Power - up to IMO Switch 150

Note

11.50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

Document 38-08036 Rev. *C Page 23 of 30

50 53 %

– – μs

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AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25 V
and 0°C <

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are

for design guidance only.

Table 23. 5V AC Analog Output Buffer Specifications

Parameter Description Min Typ Max Unit Notes

T

ROB

T

SOB

SR

SR

BW

BW

ROB

FOB

OBSS

OBLS

Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High

Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High

Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High

Small Signal Bandwidth, 20mVpp, 3-dB BW, 100 pF Load
Power = Low
Power = High

Large Signal Bandwidth, 1Vpp, 3-dB BW, 100 pF Load
Power = Low
Power = High

–
–

–
–

0.65

0.65

0.65

0.65

0.8

0.8

300
300

–
–

–
–

–
–

–
–

–
–

–
–

2.5

2.5

2.2

2.2

–
–

–
–

–
–

–
–

μs
μs

μs
μs

V/μs
V/μs

V/μs
V/μs

MHz
MHz

kHz
kHz

Table 24. 3.3V AC Analog Output Buffer Specifications

Parameter Description Min Typ Max Unit Notes

T

ROB

T

SOB

SR

SR

BW

BW

ROB

FOB

OBSS

OBLS

Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High

Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High

Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High

Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High

Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load
Power = Low
Power = High

Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load
Power = Low
Power = High

–
–

–
–

0.5

0.5

0.5

0.5

0.7

0.7

200
200

–
–

–
–

–
–

–
–

–
–

–
–

3.8

3.8

2.6

2.6

–
–

–
–

–
–

–
–

μs
μs

μs
μs

V/μs
V/μs

V/μs
V/μs

MHz
MHz

kHz
kHz

Document 38-08036 Rev. *C Page 24 of 30

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AC Programming Specifications

Note

12.A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT Š 250 ns must then be met. This automatically
be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the
next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standar d-Mode I2C-bus specification) before the SCL line is released.

The following table lists guaranteed maximum and min imum specific ations for the voltage and tem perature ranges: 4.75V to 5.25 V
and 0°C <

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are

for design guidance only.

Table 25. AC Programming Specifications

Parameter Description Min Typ Max Unit Notes

T

RSCLK

T

FSCLK

T

SSCLK

T

HSCLK

F

SCLK

T

ERASEB

T

WRITE

T

DSCLK

T

DSCLK3

2

C Specifications

AC I

Rise Time of SCLK 1 – 20 ns
Fall Time of SCLK 1 – 20 ns
Data Set up Time to Falling Edge of SCLK 40 – – ns
Data Hold Time from Falling Edge of SCLK 40 – – ns
Frequency of SCLK 0 – 8 MHz
Flash Erase Time (Block) – 10 – ms
Flash Block Write Time – 30 – ms
Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6
Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 < Vdd < 3.6

The following table lists guaranteed maximum and min imum specific ations for the voltage and tem perature ranges: 4.75V to 5.25 V
and 0°C <

TA < 70°C, or 3.0V to 3.6V and 0°C < TA < 70°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are

for design guidance only.

Table 26. AC Characteristics of the I2C SDA and SCL Pins for Vdd

Parameter Description

F

SCLI2C

T

HDSTAI2C

T

LOWI2C

T

HIGHI2C

T

SUSTAI2C

T

HDDATI2C

T

SUDATI2C

T

SUSTOI2C

T

BUFI2C

T

SPI2C

SCL Clock Frequency 0 100 0 400 kHz
Hold Time (repeated) START Condition. After

this period, the first clock pulse is generated.
LOW Period of the SCL Clock 4.7 –1.3– μs
HIGH Period of the SCL Clock 4.0 –0.6– μs
Setup Time for a Repeated START Condition 4.7 –0.6– μs
Data Hold Time 0 –0– μs
Data Setup Time 250 – 100
Setup Time for STOP Condition 4.0 –0.6– μs
Bus Free Time Between a STOP and START

Condition
Pulse Width of spikes are suppressed by the

input filter.

Standard Mode Fast Mode

Min Max Min Max

4.0 –0.6– μs

[12]

–ns

4.7 –1.3– μs

– – 0 50 ns

Unit Notes

Document 38-08036 Rev. *C Page 25 of 30

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Figure 8. Definition for Timing for Fast/Standard Mode on the I2C Bus

SDA

SCL

S

Sr SP

T

BUFI2C

T

SPI2C

T

HDSTAI2C

T

SUSTOI2C

T

SUSTAI2C

T

LOWI2C

T

HIGHI2C

T

HDDATI2C

T

HDSTAI2C

T

SUDATI2C

Document 38-08036 Rev. *C Page 26 of 30

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Packaging Information

001-12921**

This section illustrates the package specification for the CY7C64215 enCoRe III, along with the thermal impedance for the package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of

the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

http://www.cypress.com/design/MR10161.

Package Diagrams

Figure 9. 56-Pin (8x8 mm) QFN

Document 38-08036 Rev. *C Page 27 of 30

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CY7C64215

Figure 10. 28-Pin Shrunk Small Outline Package

51-85079-*C

Thermal Impedance

Table 27. Thermal Impedance for the Package

Package Typical θ

56 Pin MLF 20

28 Pin SSOP 96

* TJ = TA + POWER x θ

JA

o

C/W

o

C/W

JA

*

Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 28. Solder Reflow Peak Tempera ture

Package Minimum Peak Temperature* Maximum Peak Temperature

56 Pin MLF 240°C 260°C

28 Pin SSOP 240°C 260°C

*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220±5°C with
Sn-Pb or 245±5°C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.

Document 38-08036 Rev. *C Page 28 of 30

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CY7C64215

Package Handling

Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving
the factory. A label on the packaging has details about actual bake temperat ure and the mi nimum ba ke time to r emove thi s moistu re.
The maximum bake time is the aggregate time that the parts are exposed to the bake temperature. Exceeding this exposure time may
degrade device reliability.

Parameter Description Min Typical Max Unit

T

BAKETEMP

T

BAKETIME

Bake Temperature 125 See package label °C
Bake Time See package label 72 hours

Ordering Information

Package Ordering Code Flash Size SRAM (Bytes)

56-Pin MLF CY7C64215-56LFXC 16K 1K

28-Pin SSOP CY7C64215-28PVXC 16K 1K

Document 38-08036 Rev. *C Page 29 of 30

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CY7C64215

Document History Page

Description Title: CY7C64215, enCoRe™ III Full Speed USB Controller
Document Number: 38-08036

Rev. ECN No.

Submission

Date

Orig. of

Change

Description of Change

** 131325 See ECN XGR New data sheet

*A 3852 56 See ECN BHA Ch anged from Advance Information to Preliminary.

Added standard data sheet items.
Changed Part number from CY7C642xx to CY7C64215.

*B 2547630 08/04/08 AZIEL/PYRS Operational voltage range for USB specified under "Full-Speed USB

(12Mbps)". CMP_GO_EN1 register removed as it has no functionality on
Radon.
Figure "CPU Frequency" adjusted to show invalid operating region for USB
with footnote describing reason.
DC electrical characteristic, Vdd. Note added describing where USB
hardware is non-functional.

*C 2620679 12/12/08 CMCC/PYRS Added Package Handling information

Deleted note regarding link to amkor.com for MLF package dimensions

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. T o find the office
closest to you, visit us at cypress.com/sales.

Products

PSoC psoc.cypress.com
Clocks & Buffers clocks.cypress.com
Wireless wireless.cypress.com
Memories memory.cypress.com
Image Sensors image.cypress.com

PSoC Solutions

General psoc.cypress.com/solutions
Low Power/Low Voltage psoc.cypress.com/low-power
Precision Analog psoc.cypress.com/precision-analog
LCD Drive psoc.cypress.com/lcd-drive
CAN 2.0b psoc.cypress.com/can
USB psoc.cypress.com/usb

© Cypress Semiconductor Corporation, 2007- 2008. The in formation cont ain ed herein i s subject to change w ithout noti ce. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted no r inte nd ed to be used fo r
medical, life support, life saving, critica l contr o l o r saf ety applications, unless pursuant to an express written ag re em en t wi t h C ypr ess. Fu rth er mor e, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or fa ilure may reasonably be expe cted to result in significa nt injury to the u ser . The inclu sion of Cypress p roducts in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyrigh t laws and interna tional tr eaty pr ovision s. Cypr ess here by gra nt s to lic ensee a p erson al, no n-excl usive , non- tran sferabl e license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conju nction with a Cypress
integrated circuit as specified in the ap plicable agr eement. Any reprod uction, modificati on, translation, co mpilation, or re presentatio n of this Source Code except as spe cified above is prohibited wi thout
the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the app licati on or us e of an y product or circ uit de scrib ed herei n. Cypr ess does n ot auth orize it s product s for use a s critical component s in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document 38-08036 Rev. *C Revised December 08, 2008 Page 30 of 30

enCoRe, PSoC, and Programmable Sy stem-on-Chip are trademarks of Cypress Se miconductor Corporation. Purchase of I2C comp onents from Cypress or one of its sublicensed Associated
Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C S tandar d S pecificat ion as defined b y Philips.
All products and company names mention ed in this document may be the trademarks of their respective holders.

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