Cypress Semiconductor CY7C4425-25ASC, CY7C4425-25ACT, CY7C4425-15ASC, CY7C4425-15ACT, CY7C4425-15AC Datasheet
...
64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
fax id: 5410
CY7C4425/4205/4215
CY7C4225/4235/4245
Cypress Semiconductor Corporation • 3901North First Street • San Jose • CA 95134 • 408-943- 2600
April 1995 - Revised August 18, 1997
1CY7C42 25
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
• 64 x 18 (CY7C4425)
• 256 x 18 (CY7C4205)
• 512 x 18 (CY7C4215)
• 1K x 18 (CY7C4225)
• 2K x 18 (CY7C4235)
• 4K x 18 (CY7C4245)
• High-speed 100-MHz operation (10 ns read/write cycle
time)
• Low power (I
CC
=45 mA)
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and Programmable Almost
Empty/Almost Full status flags
• TTL-compatible
• Retransmit function
• Output Enable (OE
) pin
• Independent read and write enable pins
• Center power and ground for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• Space saving 64-pin 10x10 TQFP, and 14x14 TQFP
• 68-pin PLCC
Functional Description
T
he CY7C42X5 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide and are pin/functionally compatible to
IDT722x5. The CY7C42 X5 c an be c ascaded to increase FIFO
depth. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety
of data buffering needs, including high-speed data acquisition,
multiprocessor interf a ces, and communi catio ns buffering.
These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN
).
When WEN
is asserted, data is written into the FIFO on the
rising edge of the WCLK signal. While WEN
is held active, data
is continually writt en into t he FIFO on each cycle. The output
port is controlled in a similar manner by a free-running read
clock (RCLK) and a read enable pin (REN
). In addition, the
CY7C42X5 have an output enable pin (OE
). The read and
write clocks may be tied together for single-clock operation or
the two clocks may be run independently for asynchronous
read/write appli cations. Clock frequencies up to 100 MHz are
achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI
,
RXI
), cascade output (WXO, RXO), and First Load (FL) pins.
The WXO
and RXO pins are connected to the WXI and RXI
pins of the next device, and the WXO and RXO pins of the last
device should be connected to the WXI
and RXI pins of the
first device. The FL
pin of the first device is tied to VSS and the
FL
pin of all the remaining devices should be tied to VCC.
The CY7C42X5 provides five status pins. These pins are decoded to determine one of five states: Empty, Almost Empty,
Half Full, Almost Full, and Full (see
T able 2
). The Half Full flag
shares the WXO
pin. This flag is valid in the stan dalone and
width-expansion configurations. In the depth expansion, this
pin provides the expansion out ( WXO
) information that is used
to signal the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags will remain valid from one
clock cycle to the next. As mentioned previously, the Almost
Empty/Almost Full flags become synchronous if the
V
CC
/SMODE is tied to VSS. All configurations are fabricated
using an advanced 0.65µ N-Well CMOS technology. Input
ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings.
CY7C4425/4205/4215
CY7C4225/4235/4245
2
Logic Block Diagram
42X5–1
THREE–STATE
OUTPUT REGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
EXPANSION
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D
0–17
RENRCLK
FF
EF
PAE
Q
0–17
WENWCLK
RS
FL/RT
WXI
OE
DUAL PORT
RAM ARRAY
64 x 18
256 x 18
512 x 18
1K x 18
2K x 18
4K x 18
PAF
WXO/HF
RXI
RXO
SMODE
Pin Configurations
EF
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
67
Top View
60
59
58
57
56
55
54
53
52
51
50
49
48
3132 33 34 35 36 37 38 3940 4142 43
5 4 3 2 1 68 666564636261
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
V
CC
D
14
D
13
D
12
D
11
D
10
D
9
V
CC
D
8
GND
D
7
D
6
D
5
D
4
2728 2930
987 6
47
46
45
44
Q
6
Q
5
GND
Q
4
D
3
D
2
D
1
D
0
25
26
VCC/SMODE
42x5–2
TQFP
Top View
42X5–3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17641863196220612160225923582457255626552754285329523051315032
49
16
PLCC
PAE
FL/RT
WCLK
WEN
WXI
VCCPAF
RXI
FF
WXO/HF
RXO
Q0Q
1
GND
Q2Q
3
V
CC
Q15GND
Q16Q17VCCEF
GND
VCCRS
OE
LD
REN
RCLK
GND
D17D16D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
15
Q15GND
Q16Q
17
GND
VCCRS
OE
LD
REN
RCLK
GND
D17D
16
PAE
WCLK
WEN
WXI
V
CC
PAF
RXI
FF
WXO/HF
RXO
Q0Q
1
GND
Q2Q
3
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
Q
6
Q
5
GND
Q
4
V
CC
V
CC
/SMODE
FL/RT
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
CY7C4425
CY7C4205
CY7C4215
CY7C4225
CY7C4235
CY7C4245
CY7C4425/4205/4215
CY7C4225/4235/4245
3
Selectio n Guide
7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35
Maximum Frequency (MHz) 100 66.7 40 28.6
Maximum Access Time (ns) 8 10 15 20
Minimum Cycle Time (ns) 10 15 25 35
Minimum Data or Enable Set-Up (ns) 3 4 6 7
Minimum Data or Enable Hold (ns) 0.5 1 1 2
Maximum Flag Delay (ns) 8 10 15 20
Operating Current (I
CC2
)
(mA) @ freq=20MHz
Commercial 45 45 45 45
Industrial 50 50 50 50
CY7C4425 CY7C4205 CY7C4215 CY7C4225 CY7C423 5 CY7C4245
Density 64 x 18 256 x 18 512 x 18 1K x 18 2K x 18 4K x 18
Packages 68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
68-pin PLCC
64-pin TQFP
(10x10/14x14)
Pin Definitions
Signal Name Description I/O Function
D
0–17
Data Inputs I Data inputs for an 18-bit bus
Q
0–17
Data Outputs O Data outputs for an 18-bit bus
WEN Write Enable I Enables the WCLK input
REN Read Enable I Enables the RCLK input
WCLK Write Clock I T he rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD
is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK Read Clock I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD
is asserted, RCLK rea ds data out of the prog rammab le flag- off-
set register.
WXO/HF Write Expansion
Out/Half Full Flag
O Dual-Mode Pin:
Single device or width expansion - Half Full status flag.
Cascaded - Write Expansion Out signal, connected to WXI
of next device.
EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF Full Flag O When FF is LO W, the F IF O i s fu ll. F F is synchronized to WCLK.
PAE Programmable
Almost Empty
O When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE
is asyn chronous when VCC/SMODE is tied
to V
CC
; it is synchro nized to R CLK when VCC/SMODE is tied to VSS.
PAF Programm able
Almost Full
O When PAF is L O W, the F IF O is a lmost full ba s e d on the alm o st fu ll o ffse t va lu e
programmed into the FIFO. PAF
is asynchronous when VCC/SMODE is tied to
V
CC
; it is synchronized to WCLK when VCC/SMODE is tied to VSS.
LD Load I When LD is LO W, D
0 - 17
(O
0 - 17
) are written (read) into (from) the programma-
ble-flag-offset register.
FL/RT First Load/
Retransmit
I Dual-Mode Pin:
Cascaded - The first device in the daisy chain will have FL
tied to VSS; all other
devices will have FL
tied to VCC. In standard mode of width expansion, FL is tied
to V
SS
on all devices.
Not Cascaded - Tied to V
SS
. Retransmit function is also available in standalone
mode by strobing RT.
WXI Write Expansion
Input
I C ascaded - Connected to WXO of previous device.
Not Cascaded - Tied to V
SS
.
CY7C4425/4205/4215
CY7C4225/4235/4245
4
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ....................................−65
°C to +150° C
Ambient Temperature with
Power Applied.................................................−55
°C to +125° C
Supply Voltage to Ground Potential.... .............−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
DC Input Voltage.................................................−3.0V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .....................................................>200 mA
RXI Read Expansion
Input
I C ascaded - Connected to RXO of previous device.
Not Cascaded - Tied to V
SS
.
RXO Read Expansion
Output
O Cascaded - Connected to RXI of next device.
RS Reset I Re sets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are con-
nected. If OE
is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
VCC/SMODE Synchronous
Almost Empty/
Almost Full Flags
I Dual-Mode Pin
Asynchronous Almost Empty/Almost Full flags - tied to V
CC
.
Synchronous Almost Empty/Almost Full flags - tied to V
SS
.
(Almost Empty s ync hro nized to R CLK, Almos t Fu ll synchr onize d to W C LK. )
Pin Definitions (continued)
Signal Name Description I/O Function
Operating Range
Range
Ambient
Temperatur e
V
CC
Commercial 0°C to +70°C 5V ± 10%
Industrial
[1]
−40°C to +85°C 5V ± 10%
Electrical Characteristics Over the Operating Range
[2]
Parameter Description Test Conditions
7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35
Min. Max. Min. Max. Min. Max. Min. Max. Unit
V
OH
Output HIGH Voltage VCC = Min.,
I
OH
= −2.0 mA
2.4 2.4 2.4 2.4 V
V
OL
Output LOW Voltage VCC = Min.,
I
OL
= 8.0 mA
0.4 0.4 0.4 0.4 V
V
IH
[3]
Input HIGH Voltage 2.2 V
CC
2.2 V
CC
2.2 V
CC
2.2 V
CC
V
V
IL
[3]
Input LOW Voltage −3.0 0.8 −3.0 0.8 −3.0 0.8 −3.0 0.8 V
I
IX
Input Leakage
Current
V
CC
= Max. −10 +10 −10 +10 −10 +10 −10 +10 µA
I
OS
[4]
Output Short
Circuit Current
VCC = Max.,
V
OUT
= GND
−90 −90 −90 −90 mA
I
OZL
I
OZH
Output OFF,
High Z Current
OE > VIH,
V
SS
< VO < V
CC
−10 +10 −10 +10 −10 +10 −10 +10 µA
I
CC2
[5]
Operating Current VCC = Max.,
I
OUT
= 0 mA
Com’l 45 45 45 45 mA
Ind 50 50 50 50 mA
I
SB
[6]
Standby Current VCC = Max.,
I
OUT
= 0 mA
Com’l 10 10 10 10 mA
Ind 15 15 15 15 mA
Notes:
1. T
A
is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. The V
IH
and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the
previous device or VSS.
4. Test no more than one output at a time for not more than one second.
5. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz.
Outputs are unloaded.
6. All input signals are connected to V
CC
. All outputs are unloaded.
CY7C4425/4205/4215
CY7C4225/4235/4245
5
Notes:
7. Test ed initially and after any design or process changes that may affect these parameters.
8. C
L
= 30 pF for all AC parameters except for t
OHZ
.
9. CL = 5 pF for t
OHZ
.
Capacitance
[7]
Parameter Description Test Conditions Max. Unit
C
IN
Input Capacitance TA = 25°C, f = 1 MH z ,
V
CC
= 5.0 V
5 pF
C
OUT
Output Capacitance 7 pF
AC Test Loads and Waveforms
[8, 9]
3.0V
5V
OUTPUT
R11.1K
Ω
R2
680Ω
C
L
INCLUDING
JIGAND
SCOPE
GND
90%
10%
90%
10%
<3ns <3ns
OUTPUT 1.91V
Equivalen t to: THÉ EVENIN EQUIVALENT
42X5–4
410Ω
ALL INPUT PULSES
42X5–5
Switching Characteristics Over the Operating Range
Parameter Description
7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35
Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
S
Clock Cycle Frequency 100 66.7 40 28.6 MHz
t
A
Data Access Time 2 8 2 10 2 15 2 20 ns
t
CLK
Clock Cycle Time 10 15 25 35 ns
t
CLKH
Clock HIGH Time 4.5 6 10 14 ns
t
CLKL
Clock LOW Time 4.5 6 10 14 ns
t
DS
Data Set-Up Time 3 4 6 7 ns
t
DH
Data Hold Time 0.5 1 1 2 ns
t
ENS
Enable Set-Up Time 3 4 6 7 ns
t
ENH
Enable Hold Time 0.5 1 1 2 ns
t
RS
Reset Pulse Width
[10]
10 15 25 35 ns
t
RSR
Reset Recovery Time 8 10 15 20 ns
t
RSF
Reset to Flag and Output Time 10 15 25 35 ns
t
PRT
Retransmit Pulse Width 12 15 25 35 ns
t
RTR
Retransmit Recovery Time 12 15 25 35 ns
t
OLZ
Output Enable to Output in Low Z
[11]
0 0 0 0 ns
t
OE
Output Enable to Output Valid 3 7 3 8 3 12 3 15 ns
t
OHZ
Output Enable to Output in High Z
[12]
3 7 3 8 3 12 3 15 ns
t
WFF
Write Clock to Full Flag 8 10 15 20 ns
t
REF
Read Clock to Empty Flag 8 10 15 20 ns
t
PAFasynch
Clock to Programmable Almost-Full Flag
[12]
(Asynchronous mode , VCC/SMODE tied to VCC)
12 16 20 25 ns
CY7C4425/4205/4215
CY7C4225/4235/4245
6
t
P A Fsyn ch
Clock to Programmable Almost-Full Flag
(Synchronous mode, V
CC
/SMODE tied to VSS)
8 10 15 20 ns
t
P A Easyn ch
Clock to Programmable Almost-Empty Flag
[12]
(Asynchronous mode, VCC/SMODE tied to VCC)
12 16 20 25 ns
t
PAEsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, V
CC
/SMODE tied to VSS)
8 10 15 20 ns
t
HF
Clock to Half-Full Flag 12 16 20 25 ns
t
XO
Clock to Expansion Out 7 10 15 20 ns
t
XI
Expansion in Pulse Width 3 6.5 10 14 ns
t
XIS
Expansion in Set-Up Time 4.5 5 10 15 ns
t
SKEW1
Skew Time between Read Clock and Write
Clock for Full Flag
5 6 10 12 ns
t
SKEW2
Skew Time between Read Clock and Write
Clock for Empty Flag
5 6 10 12 ns
t
SKEW3
Skew Time between Read Clock and Write
Clock for Programmable Almost Empty and Programmable Almost Full Flags.
10 15 18 20 ns
Switching Characteristics Over the Oper atin g Ran ge (contin ued)
Parameter Description
7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35
Min. Max. Min. Max. Mi n. Max. Min. Max. Unit
Switching Waveforms
Notes:
10. Pulse widths less than minimum values are not allowed.
11. Values guaranteed by design, not currently tested.
12.
PAF asyn ch
, t
PAEasynch
, after program reg ister w rite will not be v alid until 5 n s + t
PAF(E)
.
13. t
SKEW1
is the mi nimum t ime bet ween a r ising RCLK edg e and a ris ing WC LK edge to guar antee tha t F F will go HIGH during the current clock cycle. If the time between the
rising edge of R CLK and the r ising edge of WCLK is less than t
SKEW1
, then FF may not c hange state un til the ne xt WCLK edge .
Write Cycle Timing
t
CLKH
t
CLKL
NO OPERATION
t
DS
t
SKEW1
t
ENS
WEN
t
CLK
t
DH
t
WFF
t
WFF
t
ENH
WCLK
D
0–D17
FF
REN
RCLK
42X5–6
[13]
CY7C4425/4205/4215
CY7C4225/4235/4245
7
Notes:
14. .t
SKEW2
is the minimum time between a rising WCLK edge and a rising RCL K edge to guarantee th at EF will go HIGH during the current clock cycle. It the time between the
rising edge of WCLK and th e risi ng ed ge of RCLK is les s than t
SKEW2
, then EF may not chan ge s tate unti l the next RC LK edge.
15. The clocks (RCLK, WCLK) can be free-running during reset.
16. After reset, the outputs will be LOW if OE
= 0 and three-st ate if OE = 1.
Switching Waveforms ( conti nued)
Read Cycle Timing
t
CLKH
t
CLKL
NO OPERATION
t
SKEW2
WEN
t
CLK
t
OHZ
t
REF
t
REF
RCLK
Q
0–Q17
EF
REN
WCLK
OE
t
OE
t
ENS
t
OLZ
t
A
t
ENH
VALID DATA
42X5–7
[14]
t
RS
t
RSR
Q0-Q
17
RS
t
RSF
t
RSF
t
RSF
OE=1
OE=0
REN
,WEN,
LD
EF,PAE
FF,PAF,
HF
42X5–8
Reset Timing
[15]
[16]
CY7C4425/4205/4215
CY7C4225/4235/4245
8
Notes:
17. When t
SKEW2
> minimum specification, t
FRL
(maximum) = t
CLK
+ t
SKEW2
. When t
SKEW2
< minimum specific ation, t
FRL
(maximum) = either 2*t
CLK
+ t
SKEW2
or t
CLK
+ t
SKEW2
.
The Latency T im ing appli es only at the Empt y Boundar y (EF = L OW) .
18. The first word is available the cycle after EF goes H IGH, alw ays.
Switching Waveforms ( conti nued)
D
0
(FIRSTVALIDWRITE)
First Data Word Latency after Reset with Simultaneous Read and Write
t
SKEW2
WEN
WCLK
Q
0–Q17
EF
REN
OE
t
OE
t
ENS
t
OLZ
t
DS
RCLK
t
REF
t
A
t
FRL
D
1
D
2
D
3
D
4
D
0
D
1
D0–D
17
42X5–9
t
A
[18]
[17]
D1D0
t
ENS
t
SKEW2
Empty Flag Timing
WEN
WCLK
Q
0–Q17
EF
REN
OE
t
DS
t
ENH
RCLK
t
REF
t
A
t
FRL
D0–D
17
D0
t
SKEW2
t
FRL
t
REF
t
DS
t
ENS
t
ENH
42X5–10
t
REF
[17]
[17]
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