CY7C4425/4205/4215
CY7C4225/4235/4245
14
Architectur e
The CY7C42X5 consists of an array of 64 to 4K words of 18
bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, control sig nals (RCLK, WCLK,
REN
, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The
CY7C42X5 also includes the control signals WXI
, RXI, WXO,
RXO
for depth expansion.
Resetting the FIFO
Upon power-up, the FIFO must b e reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition signified by EF
being LOW. All data outputs go LOW after the
falling edge of RS
only if OE is asserted. In order for the FIFO
to reset to its default state, a falli ng edge must occur on RS
and the user must not read or write while RS is LOW.
FIFO Operation
When the WEN signal is active (LOW), data present on the
D
0–17
pins is written into the FIFO on each rising ed ge of the
WCLK signal. Similarly, when the REN
signal is active LOW,
data in the FIFO memory will be presented on the Q
0–17
outputs. New data will be presented o n eac h rising edge of RCLK
while REN
is active LOW and OE is LOW. REN must set up
tENS before RCLK for it to be a valid read function. WEN
must
occur tENS before WCLK for it to be a valid write function.
An outpu t enable (OE
) pin is provided to three-state the Q
0–17
outputs when OE is deass e rted. When OE is enabled (LOW),
data in the output register will be available to the Q
0–17
outputs
after t
OE
. If devices are cascaded, the OE function will only
output data on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on i ts Q
0–17
outputs
even after additional reads occur.
Programming
The CY7C42X5 devices contain two 12-bit offset registers.
Data present on D
0– 11
during a program write wi ll determine
the distance from Empty (Full) that the Almost Empty (Almost
Full) flags become active. If the user elects not to program the
FIFO’s flags, the default offset values are used (see
Table 2
).
When the Load LD
pin is set LOW and WEN is set LOW, data
on the inputs D
0–11
is written into the Empty offset register on
the first LOW-to-H IGH transition of the writ e clock (WCLK).
When the LD
pin and WEN are held LOW then data is written
into the Full offset register on the second LOW-to-HIGH transition of the write clock (WCLK). The third transition of the write
clock (WCLK) again writes to the Empty offset register ( see
Ta ble 1
). Writing all offset registers does not have to occur at
one time. One or two offset registers can be written and then,
by bringing the LD
pin HIGH, the FIFO is r eturned to normal
read/write operation. Wh en the L D
pin is set LOW, and WEN
is LOW, the next offset register in sequence is written.
The contents of the offset registers can be read on the output
lines when the LD
pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the re ad
clock (RCLK).
Flag Operation
The CY7C42X5 devices provide five flag pins to indicate the
condition of the FIFO contents. Empty and Full are synchronous. PAE
and PAF are synchronous if VCC/SMODE is tied to
V
SS
.
Full Flag
The Full Flag (FF
) will go LOW when device is Full. Write op-
erations are inhibited whenever FF
is LOW regardless of the
state of WEN
. FF is synchronize d to WCL K, i.e., it is exclusiv e-
ly updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF
) will go LOW when the device is empty.
Read operations are inhibited whenever EF
is LOW, regard-
less of the state of REN
. EF is synchronized to RCLK, i.e., it is
exclusively updated by each rising edge of RCLK.
Programmable Almost Empty/Al most Ful l Flag
The CY7C42X5 features programmable Almost Empty and Almost Full Flags. Each flag can be programmed (described in
the Programming section) a specific distance from the corresponding bound a ry flags (Empty or Full). When the FIFO contains the number of words or fewer for which the flags have
been programmed, the P AF
or P AE will be asserted, signifying
that the FIFO is either Almost Full or Almost Empty. See
Table
2
for a description of programmable flags.
When the SMODE
pin is tied LOW, the PA F flag signal transition is caused by the rising edge of the write clock and the PAE
flag transition is caused by the rising edge of the read clock.
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmi t feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last RS
cycle. A HIGH pulse on
RT resets the internal read pointer to the first physical location
of the FIFO. WCLK and RCLK may be free running but must
be disabled during and t
RTR
after the retransmit pulse. With
Table 1. Write Offset Register
LD
WEN WCLK
[36]
Selection
0 0 Writing to offset registers:
Empty Offset
Full Offset
0 1 No Operation
1 0 Write Into FIFO
1 1 No Operation
Note:
36. The same selection sequence applies to reading from the registers. RE N
is enabled and read is p erformed on th e LOW- to-HIGH t ransition of RC LK.