Cypress Semiconductor CY7C43683AV-7AC, CY7C43683AV-15AC, CY7C43683AV-10AC, CY7C43663AV-7AC, CY7C43663AV-15AC Datasheet
...
V
CY7C43643AV
PRELIMINARY
CY7C43663AV/CY7C43683AV
3.3V 1K/4K/16K x36 Unidirectio nal
Synchronous FIFO w/ Bus Matching
Features
• High-speed, lo w-power, unidirectional, First- In Fi rstOut (FIFO) memori es w/ bus matching capabilities
• 1Kx36 (CY7C43643AV)
• 4Kx36 (CY7C43663AV)
• 16Kx36 (CY7C43683AV)
• 0.25-micr on CMOS for optimum speed/power
• High-speed 133- MHz operat ion (7.5- ns read /write c ycle
times)
• Low power
—I
= 60 mA
CC
= 10 mA
—I
SB
Logic Block Diagram
• Fully asynchronous and simultaneous read and write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost Full and
Almost Empty flags
• Ret ra n smit function
• Standard or FW FT user selectable mode
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-Pin TQFP packaging
• Easily expandable in width and depth
CLKA
CSA
W/RA
ENA
MBA
RT
MRS1
MRS2
PRS
FF/IR
AF
SPM
FS0/SD
FS1/SEN
A
0–35
MBF2
Por t A
Control
Logic
FIFO,
Mail1
Mail2
Reset
Logic
36
Input
Register
Write
Pointer
Programmable
Flag Offset
Registers
Mail1
Register
1K/4K/16K
x36
Dual Ported
Memory
Status
Flag Logic
Timing
Mode
Mail2
Register
Read
Pointer
Bus Matching
Output
MBF1
CLKB
Port B
Control
Register
Logic
36
CSB
W/RB
ENB
MBB
BE
BM
SIZE
EF/OR
AE
B
0–35
BE/FWFT
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 11, 2000
CY7C43643AV
Pin Configuration
[1]
W/RA
ENA
CLKA
GND
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
FWFT/STAN
GND
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
NC
A
12
GND
A
11
A
10
Note:
1. Pin-compatible to IDT723623/33/43 family.
PRELIMINARY
CY7C43663AV/CY7C43683AV
TQFP
Top View
MBF2NCAF
FS0/SD
FS1/SEN
GND
NC
MRS1
VCCPRS
FF/IR
CSA
NC
128
127
126
125
1
2
3
124
MBA
123
122
121
120
119
118
117
116
115
VCCMBF1
MRS2
MBB
114
113
112
111
4
5
6
7
8
9
10
11
12
13
14
15
16
CY7C43643AV
17
18
19
20
21
CY7C43663AV
CY7C43683AV
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39404142434445464748495051525354555657585960616263
5
6A7A8A9
A
GND
2
A
A3A4A
CC
V
SPM
0
0A1
B
A
GND
NC
EF/OR
NC
AE
110
109
108
107
5B4B3B2B1
B
B
GND
CSB
GND
ENB
W/RB
106
105
104
103
102
CLKB
101
NC
V
100
CC
99
B
35
98
B
34
97
B
33
96
B
32
GND
95
NC
94
93
B
31
92
B
30
91
B
29
90
B
28
B
89
27
88
B
26
RT
87
86
B
25
B
85
24
BM
84
83
GND
82
B
23
81
B
22
80
B
21
B
79
20
B
78
19
77
B
18
76
GND
B
75
17
74
B
16
SIZE
73
V
72
CC
B
71
15
B
70
14
69
B
13
B
68
12
GND
67
B
66
11
B
65
10
64
7
6
B9B8B
CC
V
2
CY7C43643AV
PRELIMINARY
Functional Description
The CY7C436X3AV is a monolithic, high-speed, low-power,
CMOS Unidirectional Synchronous FIFO memory which supports clock frequencies up to 133 MHz and has read access
times as fast as 6 ns.
The CY7C436X3AV is a synchronous (clocked) FIFO, meaning each port emplo ys a sync hron ous int erf ace . All data t ransfers th rough a port are gate d to the LO W - to-HI GH trans iti on of
a port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a
simple unidirectional interf ace between microprocessors and/
or buses with synchronous control.
Communication b etw een each port ma y b ypas s the FIF Os via
two mailbox registers. The mailbox registers’ width matches
the selected P ort B bus width. Each mailbo x register has a f lag
(MBF1
and MBF2) to signal when new mail has been stored.
T w o kinds of reset are a vailab le on th e CY7C436X3A V : Master
Reset and Partial Reset . Master Rese t init ializ es t he read and
write pointers to the fi rst location of the memory array, confi gures the FIFO for Big or Little Endian byte arrangement, and
selects serial flag programming, parallel flag programming, or
one of the three possible default flag offset settings, 8, 16, or
64. The FIFO also has two Master Reset pins, MRS1
MRS2
.
Partial Reset also sets the read and write pointers to the first
location of the memory . Unlike Master Reset, any settings existing prior to P artial Reset ( i.e., progr amming meth od and partial flag default offsets) are retained. Partial Reset is useful
since it permits fl ushing of the FI FO memory witho ut chang in g
any configuration settings. The FIFO has its own i ndependent
Partial Re s e t pin, PRS
The CY7C436X3AV have two modes of operation: In the CY
Standard Mode, the first word written to an em pty FIFO is deposited into the memory array. A read operation is required to
access that word (along with all other words residing in memory). In the First-Word Fall-Through Mode (FWFT ), the fi rst
.
and
CY7C43663AV/CY7C43683AV
long-word (36-bit wide) written to an empty FIFO appe ars automatically on the out puts, no read operation required (nevertheless, accessing subsequent words does necessitate a formal read request). The state of the FWFT
FIFO operation determines the mode in use.
The FIFO has a combined Empty/Output Ready flag (EF
and a combi ned Full/Input Ready flag (FF
functions are select ed in the CY Standard Mode. EF indicat es
whether the memory is ful l or not. The IR and OR funct ions are
selected in the First-Word Fall-Through Mode. IR indicates
whether or not the FIFO has available memory locations. OR
shows whether the FIFO has dat a av ai labl e fo r readin g or not.
It marks the presence of valid data on the outputs.
The FIFO has a programm able Almost Empty flag (AE
programmable Almost Full flag (AF
lected number of words written to FIFO memory achieve a
predetermined “almost em pty state.” AF
lected number of words written to the memory achieve a predetermined “almost full state.” (See Note #.)
IR and AF
into its array. OR and AE
that reads data fr om its ar ra y. Progr ammab l e offse t f or AE
AF
input. Three default offset settings are also provided. The AE
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AF
from the full boundary. All these choices are made using the
FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths. If at any time the FIFO i s not activ ely performing a
function, the chip will automatically power down. During the
Power Down state, supply current consumption (I
minimum. Init iating any oper ati on (b y act iv atin g contr ol inputs )
will immediately take the device out of the Power Down state.
The CY7C436X3AV are characterized for operation from 0
to 70
ESD protection is g reater than 200 1V, and latch-up is p revented by the use of guard rings.
are synchronized to the port clock that writes data
are loaded in parallel using Port A or in serial via the SD
threshold ca n be se t at 8, 1 6, or 64 locat ions
°
C commercial and from –40°C to 85°C industrial. Input
are synchronized to the port clock
). AE indicates when a se-
/STAN pin during
/OR)
/IR). The EF and FF
) and a
indicates when a se-
and
) is at a
CC
°
C
Selection Guide
CY7C43643/63/83AV -7CY7C43643/63/83AV
Maximum Frequency (MHz) 133 100 66.7
Maximum Access Time (ns) 6 8 10
Minimum Cycle Time (ns) 7.5 10 15
Minimum Data or Enable Set-Up (ns) 3 4 5
Minimum Data or Enable Hold (ns) 0 0 0
Maximum Flag Delay (ns) 6 8 10
Active Power Supply
Current (I
Density 1K x 36 4K x 36 16K x 36
Package 128 TQFP 128 TQFP 128 TQFP
CC1
) (mA)
Commercial 60 60 60
Industrial 60
CY7C43643AV CY7C43663AV CY7C43683AV
3
-10
CY7C43643/63/83AV
-15
CY7C43643AV
PRELIMINARY
CY7C43663AV/CY7C43683AV
Pin Definitions
Signal Name Description I/O Function
A
0–35
AE
AF
B
0–35
BE/FWFT
BM Bus Match
CLKA Port A Clock I CLKA is a c ontinuous clock t hat synchr onizes all data tr ansfer s through P ort A and can
CLKB Port B Clock I CLKB is a c ontinuous clock t hat synchr onizes all data tr ansfer s through P ort B and can
CSA
CSB
EF
/OR Empty/Output
ENA Port A Enable I ENA must be HIGH to enable a L O W -to- HIGH tra nsition of CLKA to rea d or write dat a
ENB Port B Enable I ENB must be HIGH to enable a L O W -to- HIGH tra nsition of CLKB to rea d or write dat a
FF
/IR Port B Fu ll/Input
FS1/SEN
FS0/SD Flag Offset
MBA Port A Mailbox
Port A Data I 36-bit unidirectional data port for side A.
Almost Empty
Flag (Port B)
Almost Full Flag O Progr am mable Almost Full f lag synchronized to CLKA. It is LOW when the n um ber of
Port B Data O 36-bit unidirectional data port for side B.
Big Endian/
First-Word FallThrough Select
Select (Port B)
Port A Chip
Select
Port B Chip
Select
Ready Flag
(Port B)
Ready Flag
Flag Offset
Select 1/Serial
Enable
Select 0/Serial
Data
Select
O Programmab le Almost Empty flag sy nchroni zed to CLKA. It is LO W when the numb er
of words in the FIFO2 is less than or equal to the value in the Almost Empty A offset
register, X. (See Note #35.)
empty locations in t he FIFO is less tha n or equal to the v alue in t he Almost Full A off set
register, Y. (See Note #35.)
I This is a dual-purpose pin. During Maste r Reset, a HIGH on BE will selec t Big Endian
operation. In thi s case, depe nding on the bus size, the most signi ficant byt e or word on
Port A is transf erred to P ort B first. A LO W on BE will select Little Endi an operat ion. In
this case, the l eas t sign ificant b yte or w ord on Port A is transf err ed to Port B first. After
Master Reset, this pin select s the tim ing mode. A HI GH on FWFT
Mode, a LO W sel ects Fi rst- Wo rd F a ll- Through M ode. Once t he ti ming m ode has bee n
selected, the level on FWFT
I A HIGH on this pin enables either b yte or wor d bus widt h on Po rt B, dependin g on the
state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to
select the bus size and endian arrangement for Port B. Th e level of BM must be static
throughout device operation.
be asynchronous or coincident t o CLKB. FF
to-HIGH transition of CLKA.
be asynchronous or coincident to CLKA. FB
nized to the LOW-to-HIGH transition of CLKB.
ICSA must be LOW to enable a LOW-to HIGH trans it ion of CLKA to read or write on
Port A. The A
ICSB must be LOW to enable a LOW-to HIGH trans it ion of CLKB to read or write on
Port B. The B
O This is a dual-function pin. In the CY Standard Mode, the EF function is selected. EF
indicates whether or not the FIFO memory is empty . In the FWFT mode, the OR function
is selected. OR indicates the presence of valid data on B
reading. FF
on Port A.
on Port B.
O This is a dual-function pin. In the CY Standard Mode, the FF fu nction is s e lected. FF
indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function
is selecte d. IR indicates whether or not there is space a vailable for writing to the F IFO
memory. FF
I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program-
ming. During Master Reset , FS1/ SEN
offset program ming method. Three offs et register prog ramming methods are a vailab le:
automatically load one of three preset v alues (8, 16, or 64), par allel load from Port A,
I
and serial load. When serial load i s selec ted f or fl ag offs et regi ster p rogr amming, FS1/
SEN
is used as an enab le synchron ous to the LO W -to-HIGH tr ansition of CLKA. When
FS1/SEN
and Y registers. The number of bi t writes r equir ed to pr ogr am the of fset re gisters i s 2 0
for the CY7C43643, 24 for the CY7C43663, and 28 for t he CY7C43683. The first bit
write stores the Y-register MSB and the last bit write sto res the X-register LSB.
I A HIGH lev el on MBA chooses a mailbox register for a Port A read or write oper ation.
is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X
outputs are in the high-impedance state when CSA is HIGH.
0–35
outputs are in the high- impedance state when CSB is HIGH.
0–35
/OR is synchronized to the LOW-to-HIGH transition of CLKB.
/IR is synchronized to the LOW-to-HIGH transition of CLKA.
must be static throughout device oper ation.
/IR and AF are all synchr onized to the LO W-
/IR, EF /OR, AF, and AE are all synchro-
and FS0/SD , toget her with SPM, sel ect the f lag
selects CY Standar d
outputs, available for
0–35
4
CY7C43643AV
PRELIMINARY
Pin Definitions
Signal Name Description I/O Function
MBB Port B Mailbox
MBF1
MBF2
MRS1
MRS2
PRS
RT
SIZE Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9- bit) size on Port B. A LOW
SPM
W/RA
W/
RB Port B Write/
(continued)
Select
Mail1 Register
Flag
Mail2 Register
Flag
Master Reset I A LOW on this pin initializes the FIFO read and write pointers to the fi rst location of
Master Reset I A LOW on this pin initializes the Mail2 Register.
Partial Reset I A LOW on this pin initializes the FIFO read and write pointers to the fi rst location of
Retransmit I A LOW strobe on this pin will retransmit the data in the FIFO. This is achieved by
Serial
Programming
Port A Write/
Read Select
Read Select
I A HIGH lev el on MBB chooses a mailbox register for a Port B read or write oper ation.
When a read operatio n is perf ormed on Port B, a HIGH lev el on MBB select s data from
the Mail1 register for output and a LOW level select s F IFO output register data for
output. Data can only be written into Mail 2 register through Port B (MBB HIGH) and
not into the FIFO memory.
OMBF1 is set LOW by a LOW-to-HIGH trans it ion of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1
HIGH by a LOW- to-HI GH transiti on of CLKB when a Po rt B read is selected and MBB
is HIGH. MBF1
OMBF2 is set LOW by a LOW-to-HIGH trans it ion of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2
HIGH by a LOW- to-HI GH transiti on of CLKA when a Po rt A read is selected and MBA
is HIGH. MBF2
memory and sets the P ort B output register to a ll zeroes. A LOW puls e on MRS1
the programmi ng method (serial or parallel ) and one of th ree programmab le flag def ault
offsets. It also configures Port B for bus size and endian arrangement. Four LOW-toHIGH transitio ns of CLKA an d f our LOW -t o-HIGH tr ansitions o f CLKB mu st occur while
MRS1
is LOW.
memory and sets the Port B output register to all zeroes. During Parti al Reset, the
currently selected bus size, endian arrangement, pro gramming method (serial or parallel), and progr am m able flag settings are al l retained.
bringing the read pointe r back t o location z er o . The user will sti ll need to preform read
operations to retransmit the data. Retransmit function appli es to CY sta ndard mode
only.
on this pin when BM is HIGH sele cts word (18-bit) bus size. SIZE works with BM and
BE to select the bus size and endian arrangement for Port B. The level of SIZE must
be static throughout device operation.
I A LOW on this pin se lects serial prog ramming o f partial flag offs ets. A HIGH on thi s pin
selects paral lel programming or default offsets (8, 1 6, or 64).
I A HIGH selects a write operation and a LOW selects a read operation on Port A for a
LOW-t o-HIGH transition of CLKA. The A
when W/RA
I A LOW selects a write operation and a HIGH selects a read operation on Port B for a
LOW-to-HIG H transition of CL KB. The B
when W
is set HIGH following either a Master or P artial Reset.
is set HIGH following either a Master or P artial Reset.
is HIGH.
/RB is LOW.
CY7C43663AV/CY7C43683AV
is LOW. MBF1 is se t
is LOW. MBF2 is se t
selects
outputs are i n the high-impedance state
0–35
outputs are in the high-impedance state
0–35
5
CY7C43643AV
PRELIMINARY
Maximum Ratings
[2]
(Abov e which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .......... .............. ...........–65
°
C to +150°C
Ambient Temperature with
Power Applied...............................................–55
°
C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
DC Input Voltage
Electrical Characteristics
[3]
......................................–0.5V to VCC+0.5V
[3]
...................................–0.5V to VCC+0.5V
Over the Operating Range
Parameter Description Tes t Condi ti ons
V
V
V
V
I
IX
I
OZL
I
OZH
I
CC1
I
SB
OH
OL
IH
IL
[5]
[6]
Output HIGH Voltage VCC = 3.0V,
I
= –2.0 mA
OH
Output LO W Voltage VCC = 3.0V,
I
= 8.0 mA
OL
Input HIGH Voltage 2.0 V
Input LOW Voltage –0.5 0.8 V
Input Leakage Curr ent V
Output OFF, High Z
= Max. –10 +10 µA
CC
VSS < VO< V
Current
Active Power Supply
Current
Average Standby
Current
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........... .. ........................... ...>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
CY7C43663AV/CY7C43683AV
Range
Temperature V
Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%
CY7C43643/63/83AV
2.4 V
0.5 V
Ambient
CC
CC
–10 +10
Com’l 60 mA
Ind 60 mA
Com’l 10 mA
Ind 10 mA
CC
[4]
UnitMin. Max.
V
µA
Capacitance
[7]
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Notes:
2. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
3. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
4. Operating V
5. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
6. All inputs = V
7. Tested initially and after any design or process changes that may affect these parameters.
Range for -7 speed is 3.3V ± 5%.
CC
– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
CC
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 3.3V
Output Capacitance 8 pF
CC
4 pF
6
CY7C43643AV
PRELIMINARY
AC Test Loads and Waveforms (-10, -15)
R1=330
3.3V
OUTPUT
CL =30 pF
INCLUDING
[8]
JIG AND
SCOPE
AC Test Loads and Waveforms (-7)
I/O
Z0=50
Ω
R2=680
Ω
VCC/2
50Ω
Ω
3.0V
GND
3.0V
GND
CY7C43663AV/CY7C43683AV
ALL INPUT PULSES
90%
90%
10%
10%
3
ns
≤
3
ns
≤
≤
≤
90%
10%
3ns
ALL INPUT PULSES
90%
10%
3ns
Switching Characteristics
Over the Operating Range
Parameter Description
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
t
ENS
t
RSTS
t
FSS
Clock Frequency, CLKA or CLKB 133 100 67 MHz
Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns
Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns
Pulse Duration, CLKA or CLKB LOW 3.5 4 6 ns
Set-Up Time, A
CLKB↑
before CLKA↑ and B
0–35
0–35
before
Set-Up Time, CSA, W/RA, ENA, and MBA before
CLKA↑; CSB
Set-Up Time, MRS1/MRS2 or PRS LOW before
CLKA↑ or CLKB↑
, W/RB, ENB, and MBB before CLKB↑
[9]
Set-Up Time, FS0 and FS1 before MRS1/MRS2
HIGH
t
BES
t
SPMS
t
SDS
t
SENS
t
FWS
t
DH
t
ENH
Note:
8. C
= 5 pF for t
L
9. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
Set-Up Time, BE/FWFT before MRS1/MRS2 HIGH 5 7 7.5 ns
Set-Up Time, SPM before MRS1/MRS2 HIGH 5 7 7.5 ns
Set-Up Time, FS0/SD before CLKA↑ 3 4 5 ns
Set-Up Time, FS1/SEN befor e CL KA↑ 3 4 5 ns
Set-Up Time, FW F T b e fore CLKA↑ 0 0 0 ns
Hold Time, A
CLKB↑
after CLKA↑ and B
0–35
0–35
after
Hold Time, CSA, W/RA , ENA, and MBA after CLKA↑;
CSB
, W/RB, ENB, and MBB after CLKB↑
.
DIS
CY7C43643/63/
83AV
-7
CY7C43643/
63/83AV
-10
CY7C43643/
63/83AV
-15
3 4 5 ns
3 4 5 ns
2.5 4 5 ns
5 7 7.5 ns
0 0 0 ns
0 0 0 ns
UnitMin. Max. Min. Max. Min. Max.
7
CY7C43643AV
PRELIMINARY
Switching Characteristics
Parameter Description
t
RSTH
t
FSH
t
BEH
t
SPMH
t
SDH
t
SENH
t
SPH
t
SKEW1
t
SKEW2
t
A
t
WFF
t
REF
t
PAE
t
PAF
t
PMF
[10]
[10]
Hold Time, MRS1/MRS2 or PRS LOW af te r C LKA↑
or CLKB↑
[9]
Hold Time, FS0 and FS1 after MRS1/MRS2 HIGH 1 1 2 ns
Hold Time, BE/FWFT after MRS1/MRS2 HIGH 1 1 2 ns
Hold Time, SPM after MRS1/MRS2 HIGH 1 1 2 ns
Hold Time, FS0/SD after CLKA↑ 0 0 0 ns
Hold Time, FS1/SEN after CLKA↑ 0 0 0 ns
Hold Time, FS1/SEN HIGH after MRS1/MRS2 HIGH 0 1 2 ns
Skew Time between CLKA↑ and CLKB↑ fo r E F/OR
and FF
/IR
Skew Time between CLKA↑ and CLKB↑ for AE and AF7 8 12 ns
Access Time, CLKA↑ to A
Propagation Delay Time, CLKA↑ to FF/IR 1 6 1 8 2 10 ns
Propagation Delay Time, CLKB↑ to EF/OR 1 6 1 8 2 10 ns
Propagation Delay Time, CLKB↑ to AE 1 6 1 8 1 10 ns
Propagation Delay Time, CLKA↑ to AF 1 6 1 8 1 10 ns
Propagation Delay Time, CLKA↑ to MBF1 LOW or
MBF2
HIGH and CLKB↑ to MBF2 LOW or MBF 1
Over the Operating Range (continued)
and CLKB↑ to B
0–35
0–35
CY7C43663AV/CY7C43683AV
CY7C43643/63/
83AV
-7
1 2 2 ns
5 5 7.5 ns
1 6 1 8 3 10 ns
0 6 0 8 0 12 ns
CY7C43643/
63/83AV
-10
CY7C43643/
63/83AV
-15
UnitMin. Max. Min. Max. Min. Max.
HIGH
t
PMR
t
MDV
t
RSF
t
EN
t
DIS
Propagation Delay Time, CLKA↑ to B
CLKB↑ to A
0–35
[12]
Propagation Delay Time, MBA to A
MBB to B
0–35
Va lid
Propagation Dela y Time , MRS1/MRS2 or PRS LOW
to AE
LOW , AF HIGH,FF/ IR LO W , E F/ OR LO W and
MBF1
/MBF2 HIGH
Enable Ti me, CSA or W/RA LOW to A
CSB
LOW and W/RB HIGH to B
0–35
Disable Time , CSA or W/RA HIGH to A
Impedance and CSB
HIGH or W/RB LOW to B
0–35
Valid and
0–35
0–35
Active
0–35
[11]
and
Active and
at High
0–35
1 7 2 11 3 12 ns
1 6 2 9 3 11 ns
1 6 1 10 1 15 ns
1 6 2 8 2 10 ns
1 5 1 6 1 8 ns
at High Impedance
t
PRT
t
RTR
Notes:
10. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
11. Writing data to the Mail1 register when the B
12. Writing data to the Mail2 register when the A
Retransmit Pulse Width 60 60 60 ns
Retransmit Recovery Time 90 90 90 ns
outputs are active and MBB is HIGH.
0–35
outputs are active and MBA is HIGH.
0–35
8
CY7C43643AV
PRELIMINARY
Switching W aveforms
Master Reset Loading X and Y with a Preset Value of Eight
CLKA
CLKB
t
,
MRS1
MRS2
BE/FWFT
SPM
FS1/SEN,
FS0/SD
FF
/IR
EF
/OR
RSTS
t
t
RSF
RSF
[13]
CY7C43663AV/CY7C43683AV
t
RSTH
t
t
t
SPMS
BES
t
FSS
t
BEH
t
SPMH
t
FSH
FWS
t
WFF
AE
AF
MBF1
Note:
13. PRS1
t
RSF
t
RSF
t
RSF
must be HIGH during Master Reset.
9
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