Cypress Semiconductor CY7C43662AV-7AC, CY7C43662AV-15AC, CY7C43662AV-10AC, CY7C43682AV-7AC, CY7C43682AV-15AC Datasheet
...
V
CY7C43642AV
PRELIMINARY
CY7C43662AV/CY7C43682A V
3.3V 1K/4K/16K x36 x2 Bidirectional
Synchronous FIFO
Features
• 3.3V high-speed, l ow-power, bidirectional, First-I n FirstOut (FIFO ) me mories
• 1K x36 x2 (CY7C43642AV)
• 4K x36 x2 (CY7C43662AV)
• 16K x36 x2 (CY7C43682AV)
• 0.25-micr on CMOS for optimum speed/power
• High-speed 133- MHz operat ion (7.5- ns read /write c ycle
times)
• Low power
= 60 mA
—I
CC
= 10 mA
—I
SB
Logic Block Diagram
• Fully asynchronous and simultaneous read and write
operation permitted
• Mailbox bypass register for each FIFO
• Par all el Programmable Al mo st Full and Almost Empty
flags
• Ret ra n smit function
• Standard or FW FT user selectable mode
• 120-pin TQFP packaging
• Easily expandable in width and depth
CLKA
CSA
W/RA
ENA
MBA
RT2
MRST1
FFA/IRA
AFA
FS0
FS1
A
0–35
EFA/ORA
AEA
Por t A
Control
Logic
FIFO1,
Mail1
Reset
Logic
Input
Register
Programmable
Flag Offset
Registers
Output
Register
Write
Pointer
Write
Pointer
Mail1
Register
1K/4K/16K
x36
Dual Ported
Memory
(FIFO1)
Status
Flag Logic
Status
Flag Logic
1K/4K/16K
x36
Dual Ported
Memory
(FIFo2)
Read
Pointer
Timing
Mode
Read
Pointer
Input
Output
Register
MBF1
CLKB
Port B
Control
Register
Logic
FIFO2,
Mail2
Reset
Logic
CSB
W/RB
ENB
MBB
RT1
EFB/ORB
AEB
B
0–35
FWFT/STAN
FFB/IRB
AFB
MRST2
MBF2
Cypress Semiconductor Corporation
Mail2
Register
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 14, 2000
CY7C43642AV
Pin Configuration
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
FWFT/STAN
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
RT2
A
12
PRELIMINARY
CY7C43662AV/CY7C43682A V
TQFP
Top View
EFB/ORB
VCCEFA/ORA
FFA/IRA
CSA
W/RA
ENA
CLKA
GND
120
119
118
117
116
115
1
114
113
AFA
112
AEA
111
MBF2
110
MBA
109
MRST1
108
FS0
107
106
GND
MBB
MRST2
FS1
105
104
103
2
3
4
5
6
7
8
9
10
11
12
CY7C43642AV
13
14
15
16
17
CY7C43662AV
CY7C43682AV
18
19
20
21
22
23
24
25
26
27
28
29
30
3132333435363738394041424344454647484950515253545556575859
AFB
AEB
VCCMBF1
999897969594939291
102
101
100
FFB/IRB
W/RB
VCCCLKB
ENB
CSB
GND
90
B
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
RT1
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
60
3
9
11
A10A
GND
5
A6A7A8A
GND
2
A
A4A
CC
V
0
A0A1A
GND
B5B4B3B2B1B
GND
8
6
B
9B7
10
B
B
CC
V
B11B
2
CY7C43642AV
PRELIMINARY
Functional Description
The CY7C436X2AV is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous FIFO memory which supports clock frequencies up to 133 MHz and has read access
times as fast as 6 ns. Two independent 1K/4K/16K x 36 dualport SRAM FIFOs on board each chip buffer data in opposite
directions.
The CY7C436X2AV is a synchronous (clocked) FIFO, meaning each port emplo ys a sync hron ous int erf ace . All data t ransfers th rough a port are gate d to the LO W - to-HI GH trans iti on of
a port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a
simple bidi rectional i nterfac e between microproces sors and/or
buses with synchronous control.
Communication b etw een each port ma y b ypas s the FIF Os via
two mailbox registers. The mailbox registers’ width matches
the selected P ort B bus width. Each mailbo x register has a f lag
(MBF1
and MBF2) to signal when new mail has been stored.
Master Reset initializes the read and write pointers to the first
location of the memory array, and selects parallel flag programming, or one of the three possible default flag offset settings, 8 , 16, o r 64. Eac h FIFO has it s ow n indep endent M aster
Reset pin, MRST1
The CY7C436X2AV have two modes of operation: In the CY
Standard Mode, the first word written to an em pty FIFO is deposited into the memory array. A read operation is required to
access that word (along with all other words residing in memory). In the First-Word Fall-Through Mode (FWFT ), the firs t
word (36-bi t wide) writ ten to an empty FIFO appe ars automatically on the output s, no read operati on required (nev ertheless,
accessing subsequent words does necessitate a formal read
request). The state of the FWFT
ation determines the mode in use.
and MRST2.
/STAN pin during FIFO oper-
CY7C43662AV/CY7C43682A V
Each FIFO has a combined Empty/Output Ready flag (EFA
ORA and EFB
(FFA
/IRA and F FB/IRB). The EF a nd FF func tions ar e select ed
in the CY Standard Mode. EF
is full or not. The IR and OR functions are sele cted in the First Word F all- Through Mode. IR indi cates whet her or not the FIFO
has ava il able memory locations. OR shows whether the FIFO
has data available for reading or not. It marks the pres ence of
valid data on the outputs.
Each FIFO has a programmable Almost Empty flag (AEA
AEB
) and a programmable Almost Full flag (AFA and AFB).
AEA
and AEB indicate when a selected number of words written to FIFO memory achieve a predetermined “almost empty
state.” AFA
words written t o the m emory achi ev e a predet ermined “almost
full sta te” (see Note 34).
IRA, IRB, AFA
writes data into its array. ORA, ORB, AEA
chronized to th e port clock that reads data from its array. Programmable offset for AEA
parallel usi ng P ort A. Three defa ult offs et settings are also pro vided. The AEA
locations from the empty boundary and AFA
old can be set at 8, 16, or 64 locations from the full boundary.
All these cho ices ar e made using the FS0 and FS1 i npu ts dur ing Master Reset.
Two or more devices may be used in parallel to create wider
data paths. If at any time the FIFO i s not activ ely performing a
function, the chip will automatically power down. During the
Power Down state, supply current consumption (I
minimum. Init iating any oper ati on (b y act iv atin g contr ol inputs )
will immediately take the device out of the Power Down state.
The CY7C436X4AV FIFOs are characterized for operation
from 0°C to 70°C commercial, and f rom –40°C to 85°C industrial. Input ESD prot ection is greater than 2001V, and latch-up
is prevented by the use of guard rings.
/ORB) and a combined Full/Input Ready flag
indicates whether the memory
and
and AFB indicate when a selected number of
, and AFB are synchro nized to the port clock tha t
, and AEB are syn-
, AEB, AFA, and AFB are loaded in
and AEB threshold can be set at 8, 16, or 64
and AFB thresh-
) is at a
CC
/
Selectio n Gu ide
CY7C43642/
62/82AV
7
Maximum Frequency (MHz) 133 100 66.7
Maximum Access Time (ns) 6 8 10
Minimum Cycle Time (ns) 7.5 10 15
Minimum Data or Enable Set-Up (ns) 3 4 5
Minimum Data or Enable Hold (ns) 0 0 0
Maximum Flag Delay (ns) 6 8 10
Active Power Supply
Current (I
Density 1K x 36 x2 4K x 36 x2 16K x 36 x2
Package 120 TQFP 120 TQFP 120 TQFP
CC1
) (mA)
Commercial 60 60 60
Industrial 60
CY7C43642AV CY7C43662AV CY7C43682AV
CY7C43642/
62/82AV
10
-
CY7C43642/
62/82AV
15
-
3
CY7C43642AV
PRELIMINARY
CY7C43662AV/CY7C43682A V
Pin Definitions
Signal Name Description I/O Function
A
0–35
AEA
AEB
AFA
AFB
B
0–35
/STAN First-Word Fall-
FWFT
CLKA Port A Clock I CLKA is a continuous clock t hat synchr onizes al l data t ransf ers thro ugh Port A a nd can
CLKB Port B Clock I CLKB is a continuous clock t hat synchr onizes al l data t ransf ers thro ugh Port B a nd can
CSA
CSB
/ORA Port A Empty/
EFA
EFB
/ORB Port B Empty/
ENA Port A Enable I ENA must be HIGH to enable a L O W -to- HIGH tra nsition of CLKA to rea d or write dat a
ENB Port B Enable I ENB must be HIGH to enable a L O W -to- HIGH tra nsition of CLKB to rea d or write dat a
FFA
/IRA Port A Full/Input
/IRB Port B Full/Input
FFB
Port A Data I/O 36-bit bidirectional data port for side A.
Port A Almost
Empty Flag
Port B Almost
Empty Flag
Port A Almost
Full Flag
Port B Almost
Full Flag
Port B Data I/O 36-bit bidirect ional data port for side B.
Through / CY
Standard Select
Port A Chip
Select
Port B Chip
Select
Output Ready
Flag
Output Ready
Flag
Ready Flag
Ready Flag
O Programmab le Almost Empty flag sy nchroni zed to CLKA. It is LO W when the numb er
of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register,
X2 (see Note 34).
O Programmab le Almost Empty flag sync hroni zed to CLKB . It is LO W when the nu mber
of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register,
X1 (see Note 34).
O Programmab le Almost Full flag synchronized t o CLKA. It is LO W when the number of
empty locations in FIFO1 is less than or equal to the value in the Almost Full A of fset
register, Y1 (see Note 34).
O Programmab le Almost Full flag synchronized t o CLKB. It is LOW when the number of
empty locations in FIFO2 is less than or equal to the value in the Almost Full B of fset
register, Y2 (see Note 34).
I D urin g M a ster Reset. A H IG H on FWFT
First -Wor d F a ll- Through m ode. Once t he timi ng mo de has be en se lecte d, the l ev el on
FWFT
/STAN must be static throughout device operation.
be asynchronous or coincident to CLKB. FFA
synchronized t o the LOW-to-HIGH transition of CLKA.
be asynchronous or coincident to CLKA. FFB
synchronized t o the LOW-to-HIGH transition of CLKB.
ICSA must be LOW to enable a LO W-to HIGH transition of CLKA to read or write on
Port A. The A
ICSB must be LOW to enable a LO W-to HIGH transition of CLKB to read or write on
Port B. The B
O This is a dual -function pin. In the CY Stand ard Mode , the EF A
indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is select ed. ORA indicates the presence of valid data on A
able for reading. EFA
O This is a dual-funct ion pin. In the CY Standard Mode, the EFB functio n is selected. EFB
indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is select ed. ORB indicates the presence of valid data on B
able for reading. EFB
on Port A.
on Port B.
O This is a dual-fu nction pi n. In the CY Stand ard Mode, the FFA function is sele cted. FF A
indicates whether or not t he FIFO1 memory is full. In the FWFT mode , the I RA function
is selected. IRA indicat es whether or not there is space av ailable fo r writing to the FIFO1
memor y. F FA
O This is a du al-functio n pin. I n the CY St andard M ode, th e FFB funct ion is selected. FFB
indicates whether or not t he FIFO2 memory is full. In the FWFT mode , the I RB function
is selected. IRB indicat es whether or not there is space av ailable fo r writing to the FIFO2
memor y. F FB
outputs are in the high-impedance state when CSA is HIGH.
0–35
outputs are in the high- impedance state when CSB is HIGH.
0–35
/ORA is synchronized to t he LOW-to-H IGH tr ansition of CLKA.
/ORB is synchronized to t he LOW-to- HIGH tr ansition of CLKB.
/IRA is syn ch r on i ze d to th e LOW-to- HIG H tra n s iti o n o f CLK A .
/IRB is syn ch r on i ze d to th e LOW-to- HIG H tra n s iti o n o f CLK B.
selects CY Standard mode , a LOW selects
/IRA, E FA/ORA, AFA, and AEA are all
/IRB, EFB /ORB, AFB, and AEB are all
function is selected. EF A
outputs avail-
0–35
outputs avail-
0–35
4
CY7C43642AV
PRELIMINARY
Pin Definitions
Signal Name Description I/O Function
FS1 Flag Offset
FS0 Flag Offset
MBA Port A Mailbox
MBB Port B Mailbox
MBF1
MBF2
MRST1
MRST2
RT1
RT2
W/RA
RB Port B Write/
W/
(continued)
Select 1
Select 0
Select
Select
Mail1 Register
Flag
Mail2 Register
Flag
FIFO1 Master
Reset
FIFO2 Master
Reset
Retransmit
FIFO1
Retransmit
FIFO2
Port A Write/
Read Select
Read Select
I The LOW-to- HIGH transition of a FIFO’s reset i nput lat ches the values of F S0 and FS 1.
If either FS0 or FS1 is HIGH when a reset input goes HIGH, one of the three preset
values (8, 16, or 64) is selected as the offset f or the FIFO’s Almost Ful l and Almost
I
Empty flags. If both FIFOs res et simultaneo usly and both FS0 and FS1 are LOW when
MRST1
both FIFOs.
I A HIGH lev el on MBA chooses a mailbox register for a Port A read or write operation.
When the A
register for output and a LOW level selects FIFO2 output register data f or output.
I A HIGH lev el on MBB chooses a mailbox register for a Port B read or write operation.
When the B
register for output and a LOW level selects FIFO1 output register data f or output.
OMBF1 is set LOW by a LOW-to-HIGH trans it ion of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1
HIGH by a LOW- to-HI GH transi tion of CLKB when a P ort B read is selected and MBB
is HIGH. MBF1
OMBF2 is set LOW by a LOW-to-HIGH trans it ion of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2
HIGH by a LOW- to-HI GH transi tion of CLKA when a P ort A read is selected and MBA
is HIGH. MBF2
I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. A LOW pulse on M
selects the prog ramming method (serial or paral lel) and one of three program m able
flag default of fsets for FIFO1. Four LOW-to-HIGH transition s of CLKA and f our LOWto-HIGH transitions of CLKB must occu r w h ile M
I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of
memory and sets the Port A output register to al l zeroes. A LOW pulse on MRST2
selects one of th ree programmable f lag default off sets for FIFO2. Four LOW-to-HIGH
transitions of CLKA and four LOW -to-HIGH transitions of CLKB must occur while
MRST2
I A LOW strobe on this pin will retransmit the data on FIFO1. This is achie ved by bringi ng
the read pointer back to location zero. The user will still need to perform read operations
to retransmit the data. Retransmit function applies to CY standard mode only.
I A LOW strobe on this pin will retransmit the data on FIFO2. This is achie ved by bringi ng
the read pointer back to location zero. The user will still need to perform read operations
to retransmit the data. Retransmit function applies to CY standard mode only.
I A HIGH selects a write operation and a LOW selects a read operat ion on Port A for a
LOW-t o-HIGH transition of CLKA. The A
when W/RA
I A LOW selects a write operation and a HIGH selects a read operation on Port B for a
LOW-to-HIGH transition of C L K B. The B
when W
and MRST2 go HIGH, the first four writes to FIFO1 Almost Empty offsets for
outputs are active, a HIGH lev el on MBA selects data from the Mail2
0–35
outputs are active, a HIGH lev el on MBB selects data from the Mail1
0–35
is set HIGH followi ng either a Master or Partial Reset of FIFO1.
is set HIGH followi ng either a Master or Partial Reset of FIFO2.
is LOW.
is HIGH.
/RB is LOW.
CY7C43662AV/CY7C43682A V
0–35
0–35
is LOW. MBF1 is set
is LOW. MBF2 is set
RST1
RST1 is LOW.
outputs are i n the high-impedance st ate
outputs are in the high-impedance state
5
CY7C43642AV
PRELIMINARY
Maximum Ratings
[1]
(Abov e which the useful life m ay be impaired. F or user guidelines, not tested.)
Storage Temperature .................... .............. .–65
°
C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125
°
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
DC Input Voltage
Electrical Characteristics
[2]
......................................–0.5V to VCC+0.5V
[2]
...................................–0.5V to VCC+0.5V
Over the Operating Range
Parameter Description Tes t Condi ti ons
V
V
V
V
I
IX
I
OZL
I
OZH
I
CC1
I
SB
OH
OL
IH
IL
[4]
[5]
Output HIGH Voltage VCC = 3.0V,
I
= –2.0 mA
OH
Output LO W Voltage VCC = 3.0V,
I
= 8.0 mA
OL
Input HIGH Voltage 2.0 V
Input LOW Voltage –0.5 0.8 V
Input Leakage Curr ent V
Output OFF, High Z
= Max. –10 +10 µA
CC
VSS < VO< V
Current
Active Power Supply
Current
Average Standby
Current
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......... ............. .. .. ............. ...>2001V
(per MIL-STD-883, Method 3015)
Latch -U p Cu rre n t.............. .......... ......... .......... .......... . >200mA
Operating Range
C
CY7C43662AV/CY7C43682A V
Range
Temperature V
Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%
CY7C43642/62/82AV
2.4 V
0.5 V
Ambient
CC
CC
–10 +10
Com’l 60 mA
Ind 60 mA
Com’l 10 mA
Ind 10 mA
CC
[3]
UnitMin. Max.
V
µA
[6]
Capacitance
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
3. Operating V
4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
5. All inputs = V
6. Tested initially and after any design or process changes that may affect these parameters
Range for -7 speed is 3.3V ± 5%.
CC
– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
CC
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 3.3V
Outp u t C a pacit a nce 8 pF
CC
4 pF
6
CY7C43642AV
PRELIMINARY
CY7C43662AV/CY7C43682A V
AC Test Loads and Waveforms (-10 & -15)
3.3V
OUTPUT
CL=30 pF
INCLUDING
JIG AND
SCOPE
Ω
[8]
R2=680
Ω
3.0V
GND
≤
3ns
ALL INPUT PULSES
90%
10%
90%
10%
3 ns
≤
R1=330
AC Test Loads and Waveforms (-7)
VCC/2
3.0V
GND
≤
3ns
I/O
Z0=50
Ω
Switching Characteristics
50Ω
Over the Operating Range
Parameter Description
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
t
ENS
t
RSTS
t
FSS
Clock Fr equency, CLKA or CLKB 133 100 67 MHz
Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns
Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns
Pulse Duration, CLKA or CLKB LOW 3.5 4 6 ns
Set-Up Time, A
CLKB↑
before CLK A↑ and B
0–35
0–35
before
Set-Up Ti me , CSA , W/RA, ENA, and MBA before CLKA↑;
CSB
, W/RB, ENB, and MBB before CLKB↑
Set-Up Time, MRST1 or MRST2 LOW bef ore CLKA↑ or
[7]
CLKB↑
Set-Up Time, FS0 and FS1 before MRST1 and MRST2
HIGH
t
FWS
t
DH
t
ENH
t
RSTH
t
FSH
t
SPH
t
SKEW1
Notes:
7. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
8. C
L
9. Ske w time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
Set-Up Time, FWFT bef ore CLKA↑ 0 0 0 ns
Hold Time, A
after CLKA↑ and B
0–35
after CLKB↑ 0 0 0 ns
0–35
Hold Time, CSA, W /RA, ENA, and MBA after CLKA↑;
CSB
, W/RB, ENB, and MBB after CLKB↑
Hold Time, MRST1 or MRST2 LOW after CLKA↑ or
[7]
CLKB↑
Hold Time, FS0 and FS1 after MRST1 and MRST2 HIGH 1 1 2 ns
Hold Time, FS1 HIGH after MRST1 and MRST2 HIGH 0 1 2 ns
[9]
Skew Time between CLKA↑ and CLKB↑ for EFA/ORA,
EFB
/ORB, FFA/IRA, and FFB/IRB
= 5 pF for t
DIS
.
ALL INPUT PULSES
-10
90%
10%
≤
CY7C43642/
62/82AV
3
ns
-15
90%
10%
CY7C43642/
62/82AV
-7
CY7C43642/
62/82AV
3 4 5 ns
3 4 5 ns
2.5 4 5 ns
5 7 7.5 ns
0 0 0 ns
1 2 2 ns
5 5 7.5 ns
UnitMin. Max. Min. Max. Min. Max.
7
CY7C43642AV
PRELIMINARY
Switching Characteristics
Parameter Description
[9]
t
SKEW2
t
A
t
WFF
t
REF
t
PAE
t
PAF
t
PMF
t
PMR
t
MDV
t
RSF
t
EN
t
DIS
t
PRT
t
RTR
Notes:
10. Writing data to the Mail1 register when the B
11. Writing data to the Mail2 register when the A
Skew Time between CLKA↑ and CLKB↑ for AEA, AEB,
AFA
, AFB
Access Time, CLKA↑ to A
Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑
to FFB
/IRB
Propagation Dela y Time, CLKA↑ to EF A/ORA and CLKB↑
to EFB
/ORB
Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to
AEB
Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to
AFB
Propagation Dela y Time , CLKA↑ to MBF 1 LO W or MBF2
HIGH and CLKB↑ to MBF2
Propagation Delay Time, CL KA↑ to B
to A
0–35
[11]
Propagation Delay Time, MBA to A
B
Valid
0–35
Propagation Delay Time, MRS1 or PRS1 LOW to AEB
LOW, AFA
MBF1
HIGH, FFB
HIGH, FFA/IRA LOW, EFB /ORB LOW and
HIGH and MRS2 or PRS2 LOW to AEA LOW, AFB
/IRB LOW, EFA /ORA LOW and MBF2 HIGH
Enable Time, CSA or W/RA LOW to A
LOW and W
/RB HIGH to B
Disable Time, CSA or W/RA HIGH to A
Impedance and CSB
High-Impedance
Retransmit Pulse Width 60 60 60 ns
Retransmit Recovery Time 90 90 90 ns
Over the Operating Range (continued)
0–35
LOW or MBF1 HIGH
0–35
HIGH or W/RB LOW to B
outputs are active and MBB is HIGH.
0–35
outputs are active and MBA is HIGH.
0–35
and CLKB↑ to B
[10]
and CLKB↑
0–35
Vali d and MBB to
0–35
Active a nd CSB
0–35
Active
at High-
0–35
0–35
0–35
at
CY7C43662AV/CY7C43682A V
CY7C43642/
62/82AV
-7
7 8 12 ns
1 6 1 8 3 10 ns
1 6 1 8 2 10 ns
1 6 1 8 2 10 ns
1 6 1 8 1 10 ns
1 6 1 8 1 10 ns
0 6 0 8 0 12 ns
1 7 2 11 3 12 ns
1 6 2 9 3 11 ns
1 6 1 10 1 15 ns
1 6 2 8 2 10 ns
1 5 1 6 1 8 ns
CY7C43642/
62/82AV
-10
CY7C43642/
62/82AV
-15
UnitMin. Max. Min. Max. Min. Max.
8
CY7C43642AV
PRELIMINARY
Switching W aveforms
FIFO1 Reset Loading X1 and Y1 with a Preset Value of Eight
CLKA
CLKB
t
M
RST1
FWFT/STAN
FS1, FS0
FFA
/IRA
EFB
/ORB
AEB
AFA
RSTS
t
t
RSF
RSF
t
RSF
t
RSF
t
FSS
[12]
CY7C43662AV/CY7C43682A V
t
RSTH
t
FWS
t
FSH
t
WFF
t
RSF
MBF1
Note:
12. Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value.
9
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