Cypress Semiconductor CY7C4291V-25JC, CY7C4291V-15JC, CY7C4261V-25JC, CY7C4261V-15JC, CY7C4261V-10JC Datasheet

Y7C

CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V

16K/32K/64K/128 Kx9 Low Voltage Deep Sync™ FIFOs

Features

• 3.3V operation for low power consumption and easy
integration into low voltage systems

• High-speed, low-power, first-in first-out (FIFO)
memories

• 16K x 9 (CY7C4261V)

• 32K x 9 (CY7C4271V)

• 64K x 9 (CY7C4281V)

• 128K x 9 (CY7C4291V)

• 0.35-micr on CMOS for optimum speed/power

• High-speed 100-MHz operation (10 ns read/write c ycle
times)

• Low power

I

= 25 mA

—

CC

I

= 4 mA

—

SB

• Fully asynchronous and simultaneous read and write
operation

• Empty, Full, and programmable Almost Empty and
Almost Full status flags

• Output Enable (OE

• Independent read and write enable pins

• Supports free-running 50% duty cycle cloc k input s

• Width Expansion capability

• 32-pin PLCC

• Pin-compatible density upgrade to CY7C42X1V
family

• Pin-compatible 3.3V solutions for CY7C42 61/71/81/91

pin

)

Functional Description

The CY7C4261/71/81/91V are high-speed, low-power, first-in
first-out ( FIFO) memori es wit h cl oc ked r ead and write int erf ac­es. All are 9 bit s wide. The CY7C4261/ 71/81/91V ar e pin-com­patible to the CY7C42 x1V Synchronous FIFO f amily . Progr am­mable f eat ures i nclud e Alm ost Fu ll/A lmost Empty flags . Th ese
FIFOs provide solutions for a wide variety of data buffering
needs, including high-speed data acquisition, multiprocessor
interfaces, and communications buffering.

These FIFOs have 9-bit input and output ports that are con­trolled b y separate clock an d enable signals . The i nput port is
controlled by a free-running clock (WCLK) and two write­enable pins (WEN1

When WEN1
into the FIFO on the rising edge of the WCLK signal. While
WEN1

and WEN2/LD are held active, data is continually writ­ten into the FIFO on each WCLK cycle. The output port is
controlled in a similar manner by a free-running read clock
(RCLK) and two read enab le pi ns (REN1
the CY7C4261/71/81/ 91V has an outpu t enabl e pin (OE
read (RCLK) and write (WCLK) cloc ks may be t ied together f or
single-clock operation or the two clocks may be run indepen­dently for asynchronous read/write applications. Clock fre­quencies up to 100 MHz are achievable. Depth expansion is
possible using one enable input for system control, while the
other enable is controlled b y expansion logic to direct t he flow
of data.

, WEN2/ L D).

is LOW and WEN2/LD is HIGH, dat a is w rit ten

, REN2). In addition,

). The

D

LogicBlock Diagram

WCLK

WEN1

WEN2/LD

WRITE

CONTROL

WRITE

POINTER

RS

Deep Sync is a trademark of Cypress Semiconductor.

RESET
LOGIC

THREE-STATE

OUTPUT

0−8

INPUT

REGISTER

Dual Port

RAM Array

16K/32K

64K/128K

x 9

REGISTER

Q

0−8

OE

RCLK

FLAG
PROGRAM
REGISTER

FLAG
LOGIC

READ

POINTER

READ

CONTROL

REN1 REN2

EF
PAE
PAF
FF

4281V–1

PinConfiguration

PLCC

Top View

3

2

D

4 3 2 1 31 3032

D

1

5

D

0

6
7
8
9
10
11
12

OE

13

14 15 16 17 1819 20

CY7C4261V
CY7C4271V
CY7C4281V
CY7C4291V

FF

Q0Q1Q2Q3Q

EF

PAF

PAE

GND
REN1
RCLK
REN2

D8D7D6D5D4D

RS

29
28

WEN1
WCLK

27

WEN2/LD

26

V

CC

25

Q

24

8

Q

23

7

Q

22

6

Q

21

5

4

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 4, 1999

CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V

Functional Description

The CY7C4261/71/81/91V provides four status pins: Empty,
Full, Progra mmable Almo st Empty , an d Programma ble Almost
Full. The Almost Empt y/Al most Ful l f lags are prog ram mable t o
single word granularity. The programmable flags default to
Empty +7 and Full −7.

The flags are synchronous, i.e., they change state relative to
either the read cl ock (RCLK) or t he write cloc k ( WCLK). When

(continued)

entering or exiting the Empty and Almost Empty states, the
flags are u pdated e xclus iv ely by th e RCLK. T he f lags deno ting
Almost Full, and Ful l st ates ar e upd ated e x clusi vel y b y WCL K.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle

All configurations are fabricated using an advanced 0.35µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.

Selectio n Guide

7C4261/71/81/91V-10 7C4261/71/81/91V-15 7C4261/71/81/91V-25

Maximum Frequency (MHz) 100 66.7 40
Maximum Access Time (ns) 8 10 15
Minimum Cycle Time (ns) 10 15 25
Minimum Data or Enable Set-Up (ns) 3.5 4 6
Minimum Data or Enable Hold (ns) 0 0 1
Maximum Flag Delay (ns) 8 10 15
Active Power Supply

Current (I

Density 16k x 9 32k x 9 64k x 9 128k x 9
Package 32-pin PLCC 32-pin PLCC 32-pin PLCC 32-pin PLCC

CC1

) (mA)

Commercial 25 25 25
Industrial 30

CY7C4261V CY7C4271V CY7C4281V CY7C4291V

Maximum Ratings

(Abov e which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .......................................−65

Ambient Temperature with

Po wer Applied....................................................−55

Supply Voltage to Ground Potential..................−0.5V to +3.6V

DC Voltage Applied to Outputs

in High Z State..............................................−0.5V to V

DC Input Voltage...........................................−0.5V to V

°

C to +150°C

°

C to +125°C

+0.5V

CC

+0.5V

CC

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage .......... ............. ....................>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Operating Range

Ambient

Range

Commercial 0°C to +70°C 3.3V ±300 m V
Industrial

Temperature

−40°

C to +85°C 3.3V ±300 mV

[1]

V

CC

2

CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V

Pin Definitions

Signal Name Description I/O Description

D

0−8

Q

0−8

WEN1 Wr ite Enable 1 I The only write enable when device is configured to have programmable flags . Data is

WEN2/LD
Dual Mode Pin

REN1, REN2 Read Enable

WCLK Write Clock I The rising edge clocks data into the FIFO when WEN1 is LO W and WEN2/LD is HIGH

RCLK Read Clock I The rising edge clocks data out of the FIFO when REN 1 and REN2 are LOW and the FIFO

EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF Full Flag O When FF is L OW, the FIFO is full . FF is synchronized to WCLK.
PAE Programmable

PAF Programmable

RS Reset I Resets device to empty condition. A reset is re quired before an init ial read or write

OE Output Enable I When OE is LOW , t he FIFO’s data outputs drive the bus to which they are connected. If OE is

Data Inputs I Data Inputs for 9-bit bus
Data Outputs O Data Outputs for 9-bit bus

written on a LOW-to-HIGH transition of WCLK when WEN1
If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition

of WCLK when WEN1
Wr ite Enable 2 I If HIGH at reset, thi s pin operates as a second write enable. If LOW at reset, this pin
Load

Inputs

Almost Empty

Almost Full

operates as a contro l to write or read the programmable flag offsets. WEN1

LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO

if the FF

is LOW . If the FIFO is configured to have programmable flags, WEN2/LD is held LOW

to write or read the programmable flag offsets.

I Enables the devi ce for Read operation. Both REN1 and REN2 must be asserted to

allow a read operation.

and the FIFO is not Full. When LD

offset register.

is not Empty. When WEN2/LD

register.

O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro-

grammed into the FIFO. P AE

O When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed

into the FIFO . P AF

operation after power-up.

HIGH , t he FI FO ’s outputs are in High Z (high-impedance) state.

is LOW and WEN2/LD and FF are HIGH.

is asserted, WCLK writes data into the programmable flag-

is LOW , RCLK reads data out of the programmable flag-offset

is synchronized to RCLK.

is synchronized to WCLK.

is asserted and FF is HIGH.

must be

3

CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V

Electrical Characteristics

Over the Operating Range

Parameter Description T est Conditions

V

OH

V

OL

V

IH

Output HIGH
Voltage

Output LOW
Voltage

Input HIG H

VCC = Min., IOH = −1.0 mA
V

= 3.0V , IOH = −2.0 mA

CC

VCC = Min., IOL = 4.0 mA
V

= 3.0V , IOL = 8.0 mA

CC

Voltage

V

IL

I

IX

I

OZL

I

OZH

[2]

I

CC1

[3]

I

SB

Capacitance

Input LOW
Voltage

Input Leakage
Current

Output OFF,
High Z Current

Active Power
Supply Current

Average Stand­by Current

[4]

V

= Max.

CC

OE > VIH,
V

< VO< V

SS

CC

Com’l 25 25 25 mA
Ind 30 mA
Com’l 4 4 4 mA
Ind 4 mA

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 7 pF

AC Test Loads and Waveforms (-15 & -25)

7C4261/71/81/91V

-10

7C4261/71/81/91V

-15

7C4261/71/81/91V

-25

2.4 2.4 2.4 V

.04 0.4 0.4 V

2.0 V

−0.5

−10

−10

CC

0.8

+10

+10

2.0 V

−0.5

−10

−10

CC

0.8

+10

+10

2.0 V

−0.5

−10

−10

5 pF

V

= 3.3V

CC

[5, 6]

UnitMin. Max. Min. Max. Min. Max.

CC

0.8 V

+10

+10

V

µA

µA

C

L

R1=330Ω

200

Ω

R2=510

4281V–4

ALL INPUT PULSES

3.0V

Ω

GND

≤

3ns

90%

10%

90%

10%

≤

3

ns

4281V–5

3.3V

OUTPUT

INCLUDING

JIGA ND

SCOPE

Equivalent to: THÉ VENIN EQUIVALENT

OUTPUT 2.0V

AC Test Loads and Waveforms (-10)

VCC/2

50Ω

3.0V

I/O

Notes:

1. V

Range for commercial -10 ns is 3.3V ±150mV.

CC

2. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency of 20 MHz, while data inputs
switch a t 10 M Hz. Outputs a re unloaded.)

3. All inputs = V

4. Tested initially and after any design or process changes that may affect these parameters.

= 30 pF for all AC parameters except for t

5. C

L

6. C

= 5 pF f or t

L

Z0=50

Ω

− 0.2V, except WCLK and RCLK ( which ar e at frequenc y = 0 MHz). All o utputs are u nl oaded.

CC

.

OHZ

.

OHZ

GND

≤

3ns

ALL INPUT PULSES

90%

10%

90%

10%

4282V–5

3 ns

≤

4

CY7C4261V/CY7C4271V
CY7C4281V/CY7C4291V

Switching Characteristics

Over the Operating Range

Parameter Description

t

S

t

A

t

CLK

t

CLKH

t

CLKL

t

DS

t

DH

t

ENS

t

ENH

t

RS

t

RSS

t

RSR

t

RSF

t

OLZ

t

OE

t

OHZ

t

WFF

t

REF

t

PAF

t

PAE

t

SKEW1

Clock Cycle Frequency 100 66.7 40 MHz
Data Access Time 2 8 2 10 2 15 ns
Clock Cycle Time 10 15 25 ns
Clock HIGH Time 4.5 6 10 ns
Clo ck L OW Ti m e 4.5 6 10 ns
Data Set-Up Time 3.5 4 6 ns
Data Hold Time 0 0 1 ns
Enable Set-Up Time 3.5 4 6 ns
Enable Ho ld Time 0 0 1 ns
Reset Pulse Width

[7]

Reset Set-Up Time 8 10 15 ns
Reset Recovery Time 8 10 15 ns
Reset to Flag and Output Time 10 15 25 ns
Output En a ble to Output in L o w Z
Output En a ble to Output Valid 3 7 3 10 3 12 ns
Output Enable to Output in High Z
Write Clock to Full Flag 8 10 15 ns
Read Clock to Empty Flag 8 10 15 ns
Clo ck to Progra m m able Alm ost-Full Fl a g 8 10 15 ns
Clo ck to Progra m m able Alm ost-Full Fl a g 8 10 15 ns
Skew Time between Read Clock and

Write Clock for Empty Flag and Full Flag

t

SKEW2

Skew Time between Read Clock and
Write Clock for Almost-Empty Flag and
Almost-Full Flag

Notes:

7. Pulse widths less than minimum values are not allowed.

8. Values guaranteed by design, not currently tested.

7C4261/71/81/91V

-10

7C4261/71/81/91V

-15

7C4261/71/81/91V

-25
UnitMin. Max. Min. Max. Min. Max.

10 15 25 ns

[8]

[8]

0 0 0 ns

3 7 3 8 3 12 ns

5 6 10 ns

10 15 18 ns

5