Cypress Semiconductor CY7C4265-25AC, CY7C4265-15AC, CY7C4265-10AC, CY7C4255-25AC, CY7C4255-15AC Datasheet
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8K/16K x 18 Deep Sync FIFOs
CY7C4255
CY7C4265
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
April 21, 2000
Features
• High-speed, low-power, first-in fir st-out (FIFO)
memories
• 8K x 18 (CY7C4255)
• 16K x 18 (CY7C4265)
• 0.5 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10 ns read/writ e cycle
times)
• Low power — I
CC
= 45 mA
• Fully asynchr onous and simultaneous read and write
operation
• Empty , Full, Half Full, and pr ogrammable Almost Empty
and Almost Full status flags
• TTL compatible
• Retransmit function
• Output Enable (OE
)
pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capabilit y
• Depth Expansion Capability
• 64-pin PLCC, 64-pin TQFP and 64-pin STQFP
• Pin-compatible density upgrade to CY7C42X5 family
• Pin-compatible density upgrade to
IDT72205/15/25/35/45
Functional Description
The CY7C4255/65 are high-speed, low-power, f irst-in firs t-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO fami ly. The CY7C4255/65 can
be cascaded to inc rease FIFO depth. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are controlled by separate clock and enabl e signals. The input port is
controlled by a Free-Running Clock (WCLK) and a Write Enable pin (WEN
).
When WEN
is asserted, data is written into the FIFO on the r isi ng
edge of the WCLK signal. While WEN
is held active, data is continually written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running Read Clock (RCLK) and a Read
Enable pin (REN
). In addition, the C Y 7 C 4255/65 have an Output
Enable pin (OE
). The read and write clocks may be tied together for
single-clock operation or the two clocks may be run independently for
asynchronous read/wr ite applications. Clock frequencies up to 100
MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these de vices.
Depth expansion is possibl e using the Cascade Input (WXI
,
RXI
), Cascade Output (WXO, RXO), and First Load (FL) pins. The
WXO
and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO
and RXO pins of the last device should be
connected to the WXI
and RXI pins of the first de vice. The FL pin of
the first device is tied to V
SS
and the FL pin of all the remaining devic-
es should be ti ed to V
CC
.
Q
0– 17
4255–1
THREE–STATE
OUTPUTREGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
EXPANSION
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D
0– 17
REN
RCLK
FF
EF
PAE
WENWCLK
RS
FL/RT
WXI
OE
RAM
ARRAY
8Kx 18
16K x
18
PAF
WXO/HF
RXI
RXO
SMODE
Logic Block Diagram
CY7C4255
CY7C4265
2
Functional Description
(continued)
The CY7C4255/65 provides five status pins. These pins are decoded
to determine one of five states: Empty, Almost Empty, Half Full, Almost Full, and Full. The Half Full flag shares the WXO
pin. This flag
is valid in the stand-alone and width-expansion configurations. In
the depth expansion, this pin provides the expansion out
(WXO
) information that is used to signal the next FIFO
when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the Read Clock (RCLK) or the Write
Clock (WCLK). When ent ering or exi ting the Empty st ates , the
flag is updated e xclusiv ely b y the RCLK. The flag de noting Full
states is updated excl us iv ely by WCLK . The synchrono us flag
architecture guarantees that the flags will remain valid from
one clock cycle to the next. The Almost Empty/Almost Full
flags become synchronous i f the V
CC
/SMODE is tied to VSS.
All configurations are fabricated using an advanced 0.5µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is pr evented by the use of guard rings .
Pin Configurations
EF
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
67
Top View
60
59
58
57
56
55
54
53
52
51
50
49
48
3132 3334 353637383940 4142 43
5 4 3 2 1 68 66 65 64 63 62 61
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
V
CC
D
14
D
13
D
12
D
11
D
10
D
9
V
CC
D
8
GND
D
7
D
6
D
5
D
4
2728 2930
987 6
47
46
45
44
Q
6
Q
5
GND
Q
4
D
3
D
2
D
1
D
0
25
26
VCC/SMODE
TQFP/STQFP
Top View
4255–2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17641863196220612160225923582457255626552754285329523051315032
49
16
PLCC
PAE
FL/RT
WCLK
WEN
WXI
VCCPAF
RXI
FF
WXO/HF
RXO
Q0Q
1
GND
Q2Q
3
V
CC
Q15GND
Q16Q17VCCEF
GND
VCCRS
OE
LD
REN
RCLK
GND
D17D16D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
15
Q15GND
Q16Q
17
GND
V
CC
RS
OE
LD
REN
RCLK
GND
D17D
16
PAE
WCLK
WEN
WXI
V
CC
PAF
RXI
FF
WXO/HF
RXO
Q0Q
1
GND
Q2Q
3
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
Q
6
Q
5
GND
Q
4
V
CC
V
CC
/SMODE
FL/RT
4255–3
CY7C4255
CY7C4265
CY7C4255
CY7C4265
Selection Guide
7C4255/65–10 7C4255/65–15 7C4255/65–25 7C4255/65–35
Maximum Frequency (MHz) 100 66.7 40 28.6
Maximum Access Time (ns) 8 10 15 20
Minimum Cycle Time (ns) 10 15 25 35
Minimum Data or Enable Set-Up (ns) 3 4 6 7
Minimum Data or Enable Hold (ns) 0.5 1 1 2
Maximum Flag Delay (ns) 8 10 15 20
Active Power Supply
Current (I
CC1
) (mA)
Commercial 45 45 45 45
Industrial 50 50 50 50
CY7C4255 CY7C4265
Density 8K x 18 16K x18
Package 64-pin
PLCC, TQFP,
STQFP
64-pin
PLCC, TQFP,
STQFP
CY7C4255
CY7C4265
3
Pin Definitions
Signal Name Description I/O Function
D
0 –17
Data Inputs I Data inputs for an 18-bit bus.
Q
0–17
Data Outputs O Data outputs for an 18-bit bus.
WEN Wr ite Enabl e I Enables the WCLK inpu.t
REN Read Enable I Enables the RCLK input.
WCLK Write Clock I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD
is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK Read Clock I The rising edge cloc k s data out of the F IFO when REN is LOW and the FIFO is not
Empty. When LD
is asserted, RCLK r eads data out of the programmable flag- off-
set register.
WXO/HF Write Expansion
Out/Half Full Flag
O Dual-Mode Pin:
Single devi ce or width expansion – Half Full st atus flag.
Cascaded – Write Expansion Out signal, connected to WXI
of next device.
EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF Full Flag O When FF is LOW, the FIFO is fu ll . F F i s synchronized to WCLK.
PAE Programmable
Almost Empty
O When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value pr ogram med into t he FIFO . PAE
is asynchr onous whe n VCC/SMODE is tied
to V
CC
; it is synchronized to RCLK when VCC/SMODE is tied to VSS.
PAF Programmable
Almost Full
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF
is asynchronous when VCC/SMODE is tied to
V
CC
; it is synchronized to WCLK when VCC/SMODE is tied to VSS.
LD Load I When LD is LOW, D
0–17
(Q
0–17
) are written (read) into (from) the programma-
ble-flag- offset register.
FL/RT First Load/
Retransmit
I Dual-Mode Pin:
Cascaded – The first device in the daisy chain will have FL
tied to VSS; all other
devices will have FL
tied to VCC. In st andard mode or width expansion, FL is tied
to V
SS
on all devi ce s.
Not Cascaded – Tied to V
SS
. Retransmit funct ion is also available in stand-alone
mode by strobing RT.
WXI Write Expansion
Input
I Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to V
SS
.
RXI Read Expansion
Input
I Cascaded – Connected to RXO of p r ev i o us device.
Not Cascaded – Tied to V
SS
.
RXO Read Expansion
Output
O Cascaded – Connected to RXI of next device.
RS Reset I Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are con-
nected. If OE
is HIGH, th e F IFO ’s outputs are in High Z (high-impedance) state.
VCC/SMODE Synchronous
Almost Empty/
Almost Full Flags
I Dual-Mode Pin:
Asynchronous Almost Empty/Almost Full flags – ti e d to V
CC
.
Synchronous Almost Empty/Almost Full flags – tied to V
SS
.
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
CY7C4255
CY7C4265
4
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................–65°C to +150 °C
Ambient Temperature with Power Applied .–55°C to +12 5 °C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC V oltage Applied to Outputs
in High Z State............................................... –0.5V to +7.0V
DC Input Voltage..........................................−0.5V to V
CC
+0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage .................... .......................>2001V
(per MIL–STD–883, Method 3015)
Latch-Up Current .....................................................>200 mA
Notes:
1. T
A
is the “Instant On” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the
previous dev ice or V
SS
.
4. The VIH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the
previous dev ice or V
SS.
5. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded. ICC1(typ i c al) = (25mA+(freq –20 MHz)*(1.0 mA/MHz ))
6. All inputs = VCC – 0.2V, except RCLK and WCLK (which are switching at frequency = 20 MHz), and FL/RT which is at Vss. All outputs are unloaded.
7. Tested initially and after any design changes that may affect these parameters.
8. Tested initially and after any process changes that may affect these parameters.
Operating Range
Range
Ambient
Temperature
V
CC
Commercial 0°C to +70°C 5V ± 10%
Industrial
[1]
–40°C to +85°C 5V ± 10%
Electrical Characteristics
Over the Operating Range
[2]
7C42X5–10 7C42X5–15 7C42X5–25 7C42X5– 35
Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
V
OH
Output HIGH Voltage VCC = Min. ,
I
OH
= –2.0 mA
2.4 2.4 2.4 2.4 V
V
OL
Output LOW Voltage VCC = Min. ,
I
OL
= 8.0 mA
0.4 0.4 0.4 0.4 V
V
IH
[3]
Input HIGH Voltage 2.0 V
CC
2.0 V
CC
2.0 V
CC
2.0 V
CC
V
V
IL
[4]
Input LOW Voltage –0.5 0.8 –0.5 0.8 –0.5 0.8 –0.5 0.8 V
I
IX
Input Leakage
Current
V
CC
= Max. –10 +10 –10 +10 –10 +10 –10 +10
µA
I
OZL
I
OZH
Output OFF,
High Z Current
OE > VIH,
V
SS
< VO < V
CC
–10 +10 –10 +10 –10 +10 –10 +10
µA
I
CC1
[5]
Active Power Supply
Current
Com’l 45 45 45 45 mA
Ind 50 50 50 50 mA
I
CC2
[6]
Average Standby
Current
Com’l 10 10 10 10 mA
Ind 15 15 15 15 mA
Capacitance
[7, 8]
Parameter Description Test Conditions Max. Unit
C
IN
Input Capacitance TA = 25°C, f = 1 M Hz,
V
CC
= 5.0V
5 pF
C
OUT
Output Capacitance 7 pF
CY7C4255
CY7C4265
5
AC Test Loads and Waveforms
[9, 10]
3.0V
5V
OUTPUT
R1 1.1 K
Ω
R2
680
Ω
C
L
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤
3ns
≤
3
ns
OUTPUT 1.91V
Equivalentto: THÉ VENIN EQUIVALENT
4255–4
410
Ω
ALL INPUT PULSES
4255–5
Switching Characteristics
Over the Operating Range
7C42X5–10 7C42X5–15 7C42X5–25 7C42X5–35
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
S
Clock Cycle Frequency 100 66.7 40 28.6 MHz
t
A
Data Access Time 2 8 2 10 2 15 2 20 ns
t
CLK
Clock Cycle Time 10 15 25 35 ns
t
CLKH
Clock HIGH Time 4.5 6 10 14 ns
t
CLKL
Clock LOW Time 4.5 6 10 14 ns
t
DS
Data Set-Up Time 3 4 6 7 ns
t
DH
Data Hold Time 0.5 1 1 2 ns
t
ENS
Enable Set-Up Time 3 4 6 7 ns
t
ENH
Enable Hold Time 0.5 1 1 2 ns
t
RS
Reset Pulse Width
[11]
10 15 25 35 ns
t
RSR
Reset Recovery Time 8 10 15 20 ns
t
RSF
Reset to Flag and Output Time 10 15 25 35 ns
t
PRT
Retransmit Pulse Width 30 35 45 55 ns
t
RTR
Retransmit Recov ery Time 60 65 75 85 ns
t
OLZ
Output Enable to Output in Low Z
[12]
0 0 0 0 ns
t
OE
Output Enable to Output Valid 3 7 3 8 3 12 3 15 ns
t
OHZ
Output Enable to Output in High Z
[12]
3 7 3 8 3 12 3 15 ns
t
WFF
Write Clock to Full Flag 8 10 15 20 ns
t
REF
Read Clock to Empty Flag 8 10 15 20 ns
t
PAFasynch
Clock to Programm able Almost-Full Flag
[13]
(Asynchronous mode, VCC/SMODE tied to VCC)
12 16 20 25 ns
t
PAFsynch
Clock to Programm able Almost-Full Flag
(Synchronous mode, V
CC
/SMODE tied to VSS)
8 10 15 20 ns
t
PAEasynch
Clock to Programm able Almost-Empty Flag
[13]
(Asynchronous mode, VCC/SMODE tied to VCC)
12 16 20 25 ns
Notes:
9. C
L
= 30 pF for all AC parameters except for t
OHZ
.
10. CL = 5 pF for t
OHZ
.
11. Pulse widths less than minimum values are not allowed.
12. Values guaranteed by design, not currently tested.
13. t
PAFasynch
, t
PAE asynch
, after program register write will not be valid until 5 ns + t
PAF(E)
.
CY7C4255
CY7C4265
6
t
P AEsynch
Clock to Programm able Almost-Full Flag
(Synchronous mode, V
CC
/SMODE tied to VSS)
8 10 15 20 ns
t
HF
Clock to Half-Full Flag 12 16 20 25 ns
t
XO
Clock to Expansi on Out 6 10 15 20 ns
t
XI
Expansion in Pulse Width 4.5 6.5 10 14 ns
t
XIS
Expansion in Set-Up Time 4 5 10 15 ns
t
SKEW1
Skew Time between Read Clock and Write
Clock for Full Flag
5 6 10 12 ns
t
SKEW2
Skew Time between Read Clock and Write
Clock for Empty Flag
5 6 10 12 ns
t
SKEW3
Skew Time between Read Clock and Write
Clock f or Progr ammable Almost Empty and Programmabl e Almost Full Flags (Synch ronous
Mode only)
10 15 18 20 ns
Switching Characteristics
Over the Operating Range (continued)
7C42X5–10 7C42X5–15 7C42X5–25 7C42X5–35
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
CY7C4255
CY7C4265
7
Switching Waveforms
Notes:
14. t
SKEW1
is the minimum t ime betw een a risin g RCLK edge a nd a r ising WC LK edge t o guar an tee that F F w ill g o HIGH during the c urrent cloc k c ycle. If the time betw een
the rising edge of R CLK and the ri sing edge of W CLK is l ess than t
SKEW1
, then FF ma y not ch ange stat e until th e ne x t WCLK rising edge .
15. t
SKEW2
is the minimum t ime betw een a risin g WCLK ed ge and a rising RC LK edge t o guar an tee that E F will go HIGH during the current clock cycle. It the time between
the rising edge of WC LK and t he ris ing edge of R CLK is l ess than t
SKEW2
, then EF ma y no t change state un ti l the ne xt RCLK r ising edge.
Write Cycle Timing
t
CLKH
t
CLKL
NO OPERATION
t
DS
t
SKEW1
t
ENS
WEN
t
CLK
t
DH
t
WFF
t
WFF
t
ENH
WCLK
D
0–D17
FF
REN
RCLK
4255–6
[14]
Read CycleTiming
t
CLKH
t
CLKL
NO OPERATION
t
SKEW2
WEN
t
CLK
t
OHZ
t
REF
t
REF
RCLK
Q
0–Q17
EF
REN
WCLK
OE
t
OE
t
ENS
t
OLZ
t
A
t
ENH
VALID DATA
4255–7
[15]
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