Cypress Semiconductor CY7C199L-8ZC, CY7C199L-8VC, CY7C199L-25ZI, CY7C199L-20ZC, CY7C199L-12ZC Datasheet
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Features
• High speed
—10 ns
•Fast t
DOE
• CMOS for optimum speed/power
• Low active po wer
—467 mW (max, 12 ns “L” version)
• Low standby power
—0.275 mW (max, “L” version)
• 2V data retention ( “L” version only)
• Easy memory expansion with CE
and OE featu res
• TTL-compatible inputs and outputs
• Automat ic power-down w hen deselected
Functional Description
ax id: 1030
CY7C199
32K x 8 Static RAM
provided by an active LOW chip enable (CE
output enab l e (OE
) and three-state dri vers . This dev ice has an
automatic power-down feature, r educing the power consumption by 81 % when desel ected. Th e CY7C199 is i n the st andard
300-mil-wide DIP, SOJ, and LCC packages.
An active LOW write enable signal (WE
ing/reading o peration of t he memory. When CE
are both LOW, data on the eight data input/output pins (I/O
through I/O7) is written into the memory locat ion a ddre ssed b y
the address present on the address pins (A
Reading the device is accomplished by selecting the device
and enabling the outputs, CE
and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/out put pins rem ain in a high- impedance state unle ss
the chip is selected, outputs are enabled, and write enable
(WE
) is HIGH. A die coat is used to improve alpha immuni ty.
) and active LOW
) controls the writ-
and WE inputs
through A14).
0
0
The CY7C199 is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
CE
WE
OE
4
A
5
A
6
A
A
A
ROW DECODER
7
8
9
1024 x 32 x 8
ARRAY
COLUMN
DECODER
11A13A12
10
A
A
14
A
SENSE AMPS
POWER
DOWN
C199–1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DIP / SOJ / SOIC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
0
A
13
A
14
1
I/O
0
I/O
1
2
I/O
2
GND
3
OE
A
1
4
A
2
A
3
5
A
4
WE
V
CC
6
A
5
A
6
7
A
7
A
8
A
9
A
10
A
11
Pin Configurations
Top View
V
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
22
23
24
25
26
27
28
1
2
3
4
5
6
7
CC
WE
27
26
A
4
A
25
3
24
A
2
23
A
1
22
OE
21
A
0
20
CE
19
I/O
7
18
I/O
6
17
I/O
5
16
I/O
4
15
I/O
3
C199–2
Top View
(not to scale)
A
A
A
A
A
I/O
I/O
TSOP I
A
8
A
9
10
11
12
13
14
0
1
LCC
Top View
7
A
A6A
321 27
4
5
6
7
8
9
10
11
12
1314151617
2
I/O
5
CC
V
WE
28
26
A
4
25
A
3
24
A
2
23
A
1
22
OE
21
A
0
20
CE
19
I/O
18
I/O
C199–3
5
3
I/O
I/O4I/O
GND
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Selectio n Guide
7C199-8 7C199-10 7C199-12 7C199-15 7C199-20 7C199-25 7C199-35 7C199-45
Maximum Access Time (ns) 81012 15 20 25 35 45
Maximum Operating
Current (mA)
L 90 90 90 90 80 70
Maximum CMOS
Standby Current (mA)
Shaded area contains preliminary information.
L 0.05 0.05 0.05 0.05 0.05 0.05
120 110 160 155 150 150 140 140
0.5 0.5 10 10 10 10 10 10
7
6
A
0
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
14
A
13
A
12
C199–4
7
6
5
4
3
2
1
0
Cypress Semiconductor Corporatio n
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Februar
1988 – Revised April 22, 1998
CY7C199
Maximum Ratings
(Abov e which the useful life may be impair ed. For user guidelines, not tested.)
Storag e Temperature ...... ... ......... .......... ... .. – 6 5°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)........................................... –0.5V to +7.0V
DC V oltage Applied to Outputs
in High Z State
DC Input Voltage
Electrical Characteristics
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Shaded area contains preliminary information.
Notes:
1. V
IL
2. T
is the “instant on” case temperature.
A
3. See the la st page of th is s p ec if i c at ion for Gr ou p A sub gr o up te st in g i nfo r ma ti o n .
[1]
....................................–0.5V to VCC + 0.5V
[1]
.................................–0.5V to VCC + 0.5V
Over the Operating Range
Output HIGH
VCC=Min., IOH=–4.0 mA 2.4 2.4 2.4 2.4 V
Voltage
Output LOW
VCC=Min., IOL=8.0 mA 0.4 0.4 0.4 0.4 V
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Load
GND < VI < V
Current
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power-Down
Current— TTL
Inputs
Automatic CE
Power-Down
Current— CMOS
Inputs
(min. ) = –2.0V for pul se du ra tions of l ess tha n 20 ns.
GND < VO < VCC,
Outp ut Disabled
VCC = Max.,
I
= 0 mA,
OUT
f = f
Max. V
V
V
V
Max. V
CE
V
or V
= 1/t
MAX
CC
,
IH
> VIH or
IN
< VIL, f = f
IN
CC
> VCC – 0.3V
> VCC – 0.3V
IN
< 0.3V, f = 0
IN
CC
RC
, CE >
MAX
,
[3]
7C199-8 7C199-10 7C199-12 7C199-15
Min. Max. Min. Max. Min. Max. Min. Max. Unit
2.2 V
–0.5 0.8 –0.5 0.8 –0.5 0.8 –0.5 0.8 V
–5 +5 –5 +5 –5 +5 –5 +5 µA
–5 +5 –5 +5 –5 +5 –5 +5 µA
Com’l 120 110 160 155 mA
L
Mil
Com’l 5 5 30 30 mA
L
Com’l
L
Mil
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current........... ........... ........................... .. . >200 mA
Operating Range
CC
[2]
2.2 V
V
CC
CC
+0.3V
180 mA
15 mA
V
Range Ambient Tem perature
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Military –55°C to +125°C 5V ± 10%
CC
+0.3V
2.2 V
+0.3V
CC
2.2 V
+0.3V
85 85 100 mA
555mA
0.5 0.5 10 10 mA
0.05 0.05 0.05 0.05 mA
2
CY7C199
Electrical Characteristics
Over the Op er ati ng Range
[3]
(continue d)
7C199-20 7C199-25 7C199-35 7C199-45
Paramet er Description Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
V
OH
V
OL
V
IH
V
IL
I
IX
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
V ol tage
Input LOW
V ol tage
Input Load
VCC=Min., IOH=–4.0 mA 2.4 2.4 2.4 2.4 V
VCC=Min., IOL=8.0 mA 0.4 0.4 0.4 0.4 V
2.2 V
+0.3V
CC
2.2 V
+0.3V
CC
2.2 V
+0.3V
CC
2.2 V
+0.3 V
CC
–0.5 0.8 -0.5 0.8 -0.5 0.8 -0.5 0.8 V
GND < VI < V
CC
–5 +5 –5 +5 –5 +5 –5 +5 µA
Current
I
OZ
I
CC
I
SB1
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power-Down
Current—
GND < VI < VCC,
Output Disabled
VCC = Max.,
I
= 0 mA,
OUT
f = f
= 1/t
MAX
Max. V
V
> V
IN
or VIN < VIL, f = f
RC
, CE > VIH,
CC
IH
–5 +5 –5 +5 –5 +5 –5 +5 µA
Com’l 150 150 140 140 mA
L90807070mA
Mil 170 150 150 150 mA
Com’l 3 0 30 25 25 mA
L5555mA
MAX
TTL Inputs
I
SB2
Automatic CE
Power-Down
Current—
CMOS Inputs
]
Capacitance
Max. V
CE
V
IN
V
IN
[4]
,
CC
> VCC – 0.3V
> VCC – 0.3V or
< 0.3V, f=0
Com’l 1 0 10 10 10 mA
L 0.05 0.05 0.05 0.05 µA
Mil 15 15 15 15 mA
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 5.0V
Output Capacitance 8 pF
CC
8pF
V
3
CY7C199
AC Test Loads and Waveforms
R1 481
5V
OUTPUT
30 pF
INCLUDING
JIGAND
SCOPE
Ω
R2
255
Ω
[5]
5V
OUTPUT
INCLUDING
5pF
JIGAND
SCOPE
R1 481
Ω
R2
255
Ω
C199–5
(a) (b)
Equivalentto: THÉ VENIN EQUIVALENT
167
Ω
OUTPUT 1.73V
Data Retention Characteristics
Over the Operating Range (L version only)
Parameter Description Conditions
V
DR
I
CCDR
t
CDR
[5]
t
R
[4]
VCC for Da ta Rete ntion 2.0 V
Data Retention Current Com’l VCC = VDR = 2.0V ,
CE
Com’l L 10
Chip Deselect to Data Retention Time 0 ns
> VCC – 0.3V ,
V
> VCC – 0.3V or
IN
V
< 0.3 V
IN
Operation Recovery Time t
3.0V
GND
[6]
ALL INPUT PULSES
10%
t
≤
r
90%
Min. Max. Unit
RC
90%
10%
t
≤
r
C199–6
µA
µA
ns
Data Retention Waveform
DAT A RETENTION MODE
V
CC
t
CDR
CE
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. t
< 3 ns for the -12 and -15 s peeds . tR < 5 ns for the - 20 and slow er speeds.
R
6. No input may exceed V
CC
+ 0.5V.
VDR> 2V
3.0V3.0V
t
R
C199–7
4
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