Cypress Semiconductor CY7C199L-8ZC, CY7C199L-8VC, CY7C199L-25ZI, CY7C199L-20ZC, CY7C199L-12ZC Datasheet

f

y

Features

• High speed
—10 ns

•Fast t

DOE

• CMOS for optimum speed/power

• Low active po wer
—467 mW (max, 12 ns “L” version)

• Low standby power
—0.275 mW (max, “L” version)

• 2V data retention ( “L” version only)

• Easy memory expansion with CE

and OE featu res

• TTL-compatible inputs and outputs

• Automat ic power-down w hen deselected

Functional Description

ax id: 1030

CY7C199

32K x 8 Static RAM

provided by an active LOW chip enable (CE
output enab l e (OE

) and three-state dri vers . This dev ice has an
automatic power-down feature, r educing the power consump­tion by 81 % when desel ected. Th e CY7C199 is i n the st andard
300-mil-wide DIP, SOJ, and LCC packages.

An active LOW write enable signal (WE
ing/reading o peration of t he memory. When CE
are both LOW, data on the eight data input/output pins (I/O
through I/O7) is written into the memory locat ion a ddre ssed b y
the address present on the address pins (A
Reading the device is accomplished by selecting the device
and enabling the outputs, CE

and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con­tents of the location addressed by the information on address
pins are present on the eight data input/output pins.

The input/out put pins rem ain in a high- impedance state unle ss
the chip is selected, outputs are enabled, and write enable
(WE

) is HIGH. A die coat is used to improve alpha immuni ty.

) and active LOW

) controls the writ-

and WE inputs

through A14).

0

0

The CY7C199 is a high-performance CMOS static RAM orga­nized as 32,768 words by 8 bits. Easy memory expansion is

Logic Block Diagram

INPUT BUFFER

A

0

A

1

A

2

A

3

A

CE
WE

OE

4

A

5

A

6

A
A
A

ROW DECODER

7
8
9

1024 x 32 x 8

ARRAY

COLUMN

DECODER

11A13A12

10

A

A

14

A

SENSE AMPS

POWER

DOWN

C199–1

I/O

I/O
I/O

I/O
I/O
I/O

I/O

I/O

DIP / SOJ / SOIC

A

5

A

6

A

7

A

8

A

9

A

10

A

11

A

12

0

A

13

A

14

1

I/O

0

I/O

1

2

I/O

2

GND

3

OE

A

1

4

A

2

A

3

5

A

4

WE

V

CC

6

A

5

A

6

7

A

7

A

8

A

9

A

10

A

11

Pin Configurations

Top View

V

28

1
2
3
4
5
6
7
8
9
10
11
12
13
14

22
23
24
25
26

27
28
1
2
3
4
5
6
7

CC

WE

27
26

A

4

A

25

3

24

A

2

23

A

1

22

OE

21

A

0

20

CE

19

I/O

7

18

I/O

6

17

I/O

5

16

I/O

4

15

I/O

3

C199–2

Top View

(not to scale)

A
A
A
A

A
I/O
I/O

TSOP I

A

8

A

9
10
11
12
13
14

0

1

LCC

Top View

7

A

A6A

321 27
4
5
6
7

8
9
10
11
12

1314151617

2

I/O

5

CC

V

WE

28

26

A

4

25

A

3

24

A

2

23

A

1

22

OE

21

A

0

20

CE

19

I/O

18

I/O

C199–3

5

3

I/O

I/O4I/O

GND

21
20
19
18
17

16
15
14
13
12

11
10

9
8

Selectio n Guide

7C199-8 7C199-10 7C199-12 7C199-15 7C199-20 7C199-25 7C199-35 7C199-45

Maximum Access Time (ns) 81012 15 20 25 35 45
Maximum Operating

Current (mA)

L 90 90 90 90 80 70

Maximum CMOS
Standby Current (mA)

Shaded area contains preliminary information.

L 0.05 0.05 0.05 0.05 0.05 0.05

120 110 160 155 150 150 140 140

0.5 0.5 10 10 10 10 10 10

7
6

A

0

CE
I/O
I/O
I/O
I/O
I/O
GND
I/O

I/O
I/O
A

14

A

13

A

12

C199–4

7
6
5
4
3

2
1

0

Cypress Semiconductor Corporatio n

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Februar

1988 – Revised April 22, 1998

CY7C199

Maximum Ratings

(Abov e which the useful life may be impair ed. For user guide­lines, not tested.)

Storag e Temperature ...... ... ......... .......... ... .. – 6 5°C to +150°C

Ambient Temperature with

Power Applied............................................. –55°C to +125°C

Supply Voltage to Ground Potential

(Pin 28 to Pin 14)........................................... –0.5V to +7.0V

DC V oltage Applied to Outputs
in High Z State

DC Input Voltage

Electrical Characteristics

Parameter Description Test Conditions

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

I

CC

I

SB1

I

SB2

Shaded area contains preliminary information.

Notes:

1. V

IL

2. T

is the “instant on” case temperature.

A

3. See the la st page of th is s p ec if i c at ion for Gr ou p A sub gr o up te st in g i nfo r ma ti o n .

[1]

....................................–0.5V to VCC + 0.5V

[1]

.................................–0.5V to VCC + 0.5V

Over the Operating Range

Output HIGH

VCC=Min., IOH=–4.0 mA 2.4 2.4 2.4 2.4 V

Voltage
Output LOW

VCC=Min., IOL=8.0 mA 0.4 0.4 0.4 0.4 V

Voltage
Input HIGH

Voltage
Input LOW

Voltage
Input Load

GND < VI < V

Current
Output Leakage

Current
VCC Operating

Supply Current

Automatic CE
Power-Down
Current— TTL
Inputs

Automatic CE
Power-Down
Current— CMOS
Inputs

(min. ) = –2.0V for pul se du ra tions of l ess tha n 20 ns.

GND < VO < VCC,
Outp ut Disabled

VCC = Max.,
I

= 0 mA,

OUT

f = f

Max. V
V
V
V

Max. V
CE
V
or V

= 1/t

MAX

CC

,

IH

> VIH or

IN

< VIL, f = f

IN

CC

> VCC – 0.3V

> VCC – 0.3V

IN

< 0.3V, f = 0

IN

CC

RC

, CE >

MAX

,

[3]

7C199-8 7C199-10 7C199-12 7C199-15

Min. Max. Min. Max. Min. Max. Min. Max. Unit

2.2 V

–0.5 0.8 –0.5 0.8 –0.5 0.8 –0.5 0.8 V

–5 +5 –5 +5 –5 +5 –5 +5 µA

–5 +5 –5 +5 –5 +5 –5 +5 µA

Com’l 120 110 160 155 mA
L
Mil
Com’l 5 5 30 30 mA
L

Com’l
L
Mil

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage .......................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current........... ........... ........................... .. . >200 mA

Operating Range

CC

[2]

2.2 V

V

CC

CC

+0.3V

180 mA

15 mA

V

Range Ambient Tem perature

Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Military –55°C to +125°C 5V ± 10%

CC

+0.3V

2.2 V
+0.3V

CC

2.2 V
+0.3V

85 85 100 mA

555mA

0.5 0.5 10 10 mA

0.05 0.05 0.05 0.05 mA

2

CY7C199

Electrical Characteristics

Over the Op er ati ng Range

[3]

(continue d)

7C199-20 7C199-25 7C199-35 7C199-45

Paramet er Description Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

V

OH

V

OL

V

IH

V

IL

I

IX

Output HIGH
Voltage

Output LOW
Voltage

Input HIGH
V ol tage

Input LOW
V ol tage

Input Load

VCC=Min., IOH=–4.0 mA 2.4 2.4 2.4 2.4 V

VCC=Min., IOL=8.0 mA 0.4 0.4 0.4 0.4 V

2.2 V
+0.3V

CC

2.2 V
+0.3V

CC

2.2 V
+0.3V

CC

2.2 V
+0.3 V

CC

–0.5 0.8 -0.5 0.8 -0.5 0.8 -0.5 0.8 V

GND < VI < V

CC

–5 +5 –5 +5 –5 +5 –5 +5 µA

Current

I

OZ

I

CC

I

SB1

Output Leakage
Current

VCC Operating
Supply Current

Automatic CE
Power-Down
Current—

GND < VI < VCC,
Output Disabled

VCC = Max.,
I

= 0 mA,

OUT

f = f

= 1/t

MAX

Max. V
V

> V

IN

or VIN < VIL, f = f

RC

, CE > VIH,

CC

IH

–5 +5 –5 +5 –5 +5 –5 +5 µA

Com’l 150 150 140 140 mA
L90807070mA
Mil 170 150 150 150 mA
Com’l 3 0 30 25 25 mA
L5555mA

MAX

TTL Inputs

I

SB2

Automatic CE
Power-Down
Current—
CMOS Inputs

]

Capacitance

Max. V
CE
V

IN

V

IN

[4]

,

CC

> VCC – 0.3V
> VCC – 0.3V or
< 0.3V, f=0

Com’l 1 0 10 10 10 mA
L 0.05 0.05 0.05 0.05 µA
Mil 15 15 15 15 mA

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Input Capacitance TA = 25°C, f = 1 MHz,

V

= 5.0V

Output Capacitance 8 pF

CC

8pF

V

3

CY7C199

AC Test Loads and Waveforms

R1 481

5V

OUTPUT

30 pF

INCLUDING

JIGAND

SCOPE

Ω

R2
255

Ω

[5]

5V

OUTPUT

INCLUDING

5pF

JIGAND

SCOPE

R1 481

Ω

R2
255

Ω

C199–5

(a) (b)

Equivalentto: THÉ VENIN EQUIVALENT

167

Ω

OUTPUT 1.73V

Data Retention Characteristics

Over the Operating Range (L version only)

Parameter Description Conditions

V

DR

I

CCDR

t

CDR

[5]

t

R

[4]

VCC for Da ta Rete ntion 2.0 V
Data Retention Current Com’l VCC = VDR = 2.0V ,

CE

Com’l L 10

Chip Deselect to Data Retention Time 0 ns

> VCC – 0.3V ,

V

> VCC – 0.3V or

IN

V

< 0.3 V

IN

Operation Recovery Time t

3.0V

GND

[6]

ALL INPUT PULSES

10%

t

≤

r

90%

Min. Max. Unit

RC

90%

10%

t

≤

r

C199–6

µA
µA

ns

Data Retention Waveform

DAT A RETENTION MODE

V

CC

t

CDR

CE

Notes:

4. Tested initially and after any design or process changes that may affect these parameters.

5. t

< 3 ns for the -12 and -15 s peeds . tR < 5 ns for the - 20 and slow er speeds.

R

6. No input may exceed V

CC

+ 0.5V.

VDR> 2V

3.0V3.0V
t

R

C199–7

4

CY7C199

Switching C h aracteristi cs

Over the Operating Range

[3, 7]

7C199-8 7C199-10 7C199-12 7C199-15

Min. Max. Min. Max. Min. Max. Min. Max.

UnitParameter Description

READ CYCLE

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

t

PU

t

PD

WRITE CYCLE

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

HZWE

t

LZWE

Shaded area contains preliminary information.

Notes:

7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified I

8. At any given temperature and voltage condition, t

9. t

10. The internal write time of the memory is defined by the overlap of CE

11. The minimum write cycle time for write cycle #3 (WE

, t

HZOE

a write by going HIGH. The d ata i nput set-up and hol d timing s hould be ref er enced to the ri sing edge of the signal that t erminates the write.

Read Cycle Time 8 10 12 15 ns
Address to Data Valid 8101215ns
Data Hold from Address Chan ge 3 333ns
CE LOW to Data Valid 8101215ns
OE LOW to Data Valid 4.5 5 5 7 ns
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z

[8]

[8]

[8, 9]

[8,9]

0 000ns

5557ns

3 333ns

4557ns
CE LOW to Power-Up 0 000ns
CE HIGH to Power-Do wn 8101215ns

[10, 11]

Write Cycle Time 8 10 12 15 ns
CE LOW to Write End 7 7910ns
Address Set-Up to Write End 7 7910ns
Address Hold from Write End 0 000ns
Address Set-Up to Write Start 0 000ns
WE Pulse Width 7 789ns
Data Set-Up to Write End 5 589ns
Data Hold from Write End 0 000ns
WE LOW to High Z
WE HIGH to Low Z

, and t

HZCE

HZWE

are specified wi th CL = 5 pF as in part (b) of A C Test Loads. Transition is measured ±500 mV from stea dy-state vol tage.

[9]
[8]

3 333ns

and 30-pF load capac itance.

is less than t

HZCE

controlled, OE LOW) is the sum of t

OL/IOH

, t

LZCE

is less than t

HZOE

LOW and WE LO W. Both signals must be LO W to ini tiate a write and e it her sign al can terminat e

5677ns

HZWE

LZOE

and tSD.

, and t

HZWE

is less than t

for any given device.

LZWE

5

CY7C199

Switching C h aracteristi cs

Over the Operating Range

[3,7]

(continued)

7C199-20 7C199-25 7C199-35 7C199-45

Parameter Description M in. Max. Min. Max. M in. Max. Min. Max. Unit

READ CYCLE

t

RC

t

AA

t

OHA

Read Cycle Time 20 25 35 45 ns
Address to Data Valid 20 25 35 45 ns
Data Hold from Address

33 3 3 ns

Change

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

t

PU

t

PD

WRIT E CYCLE

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

HZWE

t

LZWE

CE LOW to Data Valid 20 25 35 45 ns
OE LOW to Data Valid 9 10 16 16 ns
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z

[8]

[8]

[8,9]

[8,9]

00 0 0 ns

9111515ns

33 3 3 ns

9111515ns
CE LOW to Po wer-Up 0 0 0 0 ns
CE HIGH to Power-Down 20 20 20 25 ns

[10,11]

Write Cycle Time 20 25 35 45 ns
CE LOW to Write End 15 18 22 22 ns
Address Set-Up to Write End 15 20 30 40 ns
Address Hold from Write End 0 0 0 0 ns
Address Set-Up to Write Start 0 0 0 0 ns
WE Pulse Width 15 18 22 22 ns
Data Set-Up to Write End 10 10 15 15 ns
Data Hold from Write End 0 0 0 0 ns
WE LOW to High Z
WE HIGH to Low Z

[9]

[8]

10 11 15 15 ns

33 3 3 ns

Switching Waveform s

Read Cycle No. 1

ADDRESS

DATA OUT PREVIOUS DATA VALID

Notes:

12. Device is continuously selected. OE

13. WE

is HIGH f or r ead cycle .

[12, 13]

, CE = VIL.

t

OHA

t

RC

t

AA

DATA VALID

C199–8

6

CY7C199

Switching Waveform s

Read Cycle No. 2

[13, 14]

(continued)

CE

OE

DATA OUT

V

CC

SUPPLY

HIGH IMPEDANCE

t

LZCE

t

PU

CURRENT

Write Cycle No. 1 (WE Controlled)

ADDRESS

CE

t

ACE

t

t

LZOE

50%

[10, 15, 16]

DOE

t

RC

t

HZOE

t

DATA VALID

HZCE

t

PD

HIGH

IMPEDANCE

ICC

50%

ISB

C199–9

t

WC

WE

t

OE

DATA I/O

Write Cycle No. 2 (CE Controlled)

ADDRESS

CE

WE

DATA I/O

SA

t

HZOE

[10, 15, 16]

t

AW

t

PWE

t

SD

t

HA

t

HD

DAT AINVALID

C199–10

t

WC

t

SCE

t

SA

t

AW

t

SD

t

HA

t

HD

DATAINVALID

C199–11

Notes:

14. Address valid prior to or coincident with CE

15. Data I/O is high impedance if OE = VIH.

16. If CE

goes HIGH simultaneously with WE HIGH, the output r emains i n a high-impe dance state .

transition LOW.

7

CY7C199

Switching Waveform s

Write Cycle No. 3 (WE Controlled OE

(continued)

LOW)

ADDRESS

CE

t

WE

SA

DATA I/O

t

HZWE

T y pical DC and AC Characteris ti cs

NORMALIZED SUPPLY CURRENT
vs. SUPPLY

1.4

SB

1.2

,I

CC

1.0

0.8

0.6

0.4

NORMALIZED I

0.2

I

SB

0.0

4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)

VOLTAGE

I

CC

V

IN

T

A

,I

=5.0V

=25°C

NORMALIZED I

[11, 16]

t

WC

t

AW

t

SD

DA TAINVALID

NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE

SB

CC

1.4

1.2

1.0

I

CC

0.8

0.6
V

0.4

0.2

0.0

I

SB

–55 25 125

V

CC
IN

=5.0V

=5.0V

AMBIENT TEMPERATURE (°C)

t

HA

t

HD

t

LZWE

OUTPUT SOURCE CURRENT
vs. OUTPUT

VOLTAGE

120

100

80

=5.0V

V

60

T

A

CC

=25°C

40
20

0

OUTPUT SOURCE CURRENT (mA)

0.0 1.0 2.0 3.0 4.0
OUTPUT VOLTAGE (V)

C199–12

NORMALIZED ACCESS TIME
vs. SUPPLY

VOLTAGE

1.4

1.3

AA

1.2

NORMALIZED t

1.1

1.0

TA=25°C

0.9

0.8

4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)

NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE

1.6

1.4

AA

1.2

1.0

NORMALIZED t

VCC=5.0V

0.8

0.6
–55 25 125

AMBIENT TEMPERATURE (°C)

8

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

140
120

100

80
60
40
20

OUTPUT SINK CURRENT (mA)

V
T

CC

=25°C

A

=5.0V

0

0.0 1.0 2.0 3.0 4.0
OUTPUT VOLTAGE (V)

CY7C199

T y pical DC and AC Characteris ti cs

TYPICALPOWER-ON CURRENT

vs.SUPPLY

3.0

2.5

PO

2.0

1.5

1.0

NORMALIZED I

0.5

0.0

0.0 1.0 2.0 3.0 4.0

VOLTAGE

5.0

SUPPLY VOLTAGE (V)

(continued)

TYPICAL ACCESS TIMECHANGE

vs. OUTPUT LOADING

30.0

25.0

20.0

AA

15.0

DELTA t (ns)

10.0

5.0

0.0
0 200 400 600 800

CAPACITANCE (pF)

V

CC

T

A

=4.5V

=25°C

Truth Table

CE WE OE Inputs/Outputs Mode Power

H X X High Z Deselect/Power-Down Standby (ISB)
L H L Data Out Read Active (ICC)
L L X Data In Write Active (ICC)
L H H High Z Deselect, Output Disabled Active (ICC)

1000

NORMALIZED I

1.25

=5.0V

CC

1.00

0.75

NORMALIZED I

0.50

V

CC

T

=25°C

A

V

=0.5V

IN

10 20 30 40

CYCLE FREQUENCY (MHz)

vs.CYCLETIME

CC

Ordering Information

Speed

(ns) Ordering Code

8 CY7C199-8VC V21 28-Lead Molded SOJ Commercial

CY7C199-8ZC Z28 28-Lead Thi n Sma ll Outline Pac kage
CY7C199L-8VC V21 28-Lead Molded SOJ
CY7C199L-8ZC Z28 28-Lead Thin Small Outline Package

10 CY7C199-10VC V21 28-Lead Molded SOJ Commercial

CY7C199-10ZC Z28 28-Lead Thin Small Outline Package
CY7C199L-10VC V21 28-Lead Molded SOJ
CY7C199L-10ZC Z28 28-Lead Thin Small Outline Package
CY7C199-10VI V21 28-Lead Molded SOJ Industrial
CY7C199-10ZI Z28 28-Lead Thin Small Outline Pac kage
CY7C199L-10VI V21 28-Lead Molded SOJ
CY7C199L-10ZI Z28 28-Lead Thin Small Outline Package

12 CY7C199-12PC P21 28-Lead (300-Mi l) Molded DIP Commercial

CY7C199-12VC V21 28-Lead Molded SOJ
CY7C199-12ZC Z28 28-Lead Thin Small Outline Package
CY7C199L-12PC P21 28-Lead (300-Mil ) Molded DIP
CY7C199L-12VC V21 28-Lead Molded SOJ
CY7C199L-12ZC Z28 28-Lead Thin Small Outline Package
CY7C199-12VI V21 28-Lead Molded SOJ Industrial
CY7C199-12ZI Z28 28-Lead Thin Small Outline Pac kage
CY7C199L-12VI V21 28-Lead Molded SOJ
CY7C199L-12ZI Z28 28-Lead Thin Small Outline Package

Shaded area contains preliminary informati on. Contact your Cypress sales representative for availability

Package

Name Package Type

Operating

Range

9

CY7C199

Ordering Information

Speed

(ns) Ordering Code

15 CY7C199-15PC P21 28-Lead (300-Mi l) Molded DIP Commercial

CY7C199-15VC V21 28-Lead Molded SOJ
CY7C199-15ZC Z28 28-Lead Thin Small Outline Package
CY7C199L-15PC P21 28-Lead (300-Mil ) Molded DIP
CY7C199L-15VC V21 28-Lead Molded SOJ
CY7C199L-15ZC Z28 28-Lead Thin Small Outline Package
CY7C199-15VI V21 28-Lead Molded SOJ Industrial
CY7C199-15ZI Z28 28-Lead Thin Small Outline Pac kage
CY7C199-15DMB D22 28-Lead (300-Mil) CerDI P Milita ry
CY7C199-15LMB L54 28-Pin Rectangula r Leadless Chip Carrier
CY7C199L-15DMB D22 28-Lead (300-Mil) CerDIP
CY7C199L-15LMB L54 28-Pin Rectangular Leadless Chip Car rie r

20 CY7C199-20PC P21 28-Lead (300-Mi l) Molded DIP Commercial

CY7C199-20VC V21 28-Lead Molded SOJ
CY7C199-20ZC Z28 28-Lead Thin Small Outline Package
CY7C199L-20PC P21 28-Lead (300-Mil ) Molded DIP
CY7C199L-20VC V21 28-Lead Molded SOJ
CY7C199L-20ZC Z28 28-Lead Thin Small Outline Package
CY7C199-20VI V21 28-Lead Molded SOJ Industrial
CY7C199-20ZI Z28 28-Lead Thin Small Outline Pac kage
CY7C199-20DMB D22 28-Lead (300-Mil) CerDI P Milita ry
CY7C199-20LMB L54 28-Pin Rectangula r Leadless Chip Carrier
CY7C199L-20DMB D22 28-Lead (300-Mil) CerDIP
CY7C199L-20LMB L54 28-Pin Rectangular Leadless Chip Car rie r

25 CY7C199-25PC P21 28-Lead (300-Mi l) Molded DIP Commercial

CY7C199-25SC S21 28-Lead Molded SOIC
CY7C199-25VC V21 28-Lead Molded SOJ
CY7C199-25ZC Z28 28-Lead Thin Small Outline Package
CY7C199L-25ZI Z28 28-Lead Thin Small Outline Package Industrial
CY7C199-25DMB D22 28-Lead (300-Mil) CerDI P Milita ry
CY7C199-25LMB L54 28-Pin Rectangula r Leadless Chip Carrier

35 CY7C199-35PC P21 28-Lead (300-Mi l) Molded DIP Commercial

CY7C199-35SC S21 28-Lead Molded SOIC
CY7C199-35VC V21 28-Lead Molded SOJ
CY7C199-35ZC Z28 28-Lead Thin Small Outline Package
CY7C199-35DMB D22 28-Lead (300-Mil) CerDI P Milita ry
CY7C199-35LMB L54 28-Pin Rectangula r Leadless Chip Carrier

45 CY7C199-45DMB D22 28-Lead (300-Mil) CerDIP Military

CY7C199-45LMB L54 28-Pin Rectangula r Leadless Chip Carrier

Shaded area contains preliminary informati on. Contact your Cypress sales representative for availability

(continued)

Package

Name Package Type

Operating

Range

10

MILITARY SPECIFICATIONS
Group A Subgroup Testing

CY7C199

DC Characteristics

Parameter Subgroups

V

OH

V

OL

V

IH

VIL Max. 1, 2, 3
I

IX

I

OZ

I

CC

I

SB1

I

SB2

Package Diagrams

28-Lead (300-Mil) CerDIP D22

MIL–STD–1835 D–15 Config. A

1, 2, 3
1, 2, 3
1, 2, 3

1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3

Switching Characteristics

Parameter Subgroups

READ CYCLE

t

RC

t

AA

t

OHA

t

ACE

t

DOE

WRITE CYCLE

t

WC

t

AA

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

Document #: 38–00239–E

28-Pin R ect angular Leadless ChipCarrier L54

MIL–STD–1835 C–11A

7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11

7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11

11

CY7C199

Package Diagrams

(continued)

28-Lead (300-Mil) Molded DIP

28-Lead(300-Mil)Molded SOIC S21

P21

12

CY7C199

Package Diagrams

(continued)

28-Lead (300-Mil) Molded SOJ

V21

28-Lead ThinSmall Outline Pac kage

Z28

© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any l icense under patent or other rights. Cypress Semi conductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.