Cypress Semiconductor CY7C187-35VCT, CY7C187-35VC, CY7C187-35PC, CY7C187-25VCT, CY7C187-25VC Datasheet

64K x 1 Static RAM

CY7C187

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 4, 1999

Features

• High speed
—15 ns

• CMOS for optimum speed/power

• Low active power
—495 mW

• Low standb y p ow er
—220 mW

• TTL compatible inputs and outputs

• Automat ic power-down when deselected

Functional Description

The CY7C187 is a high-performance CMOS stati c RAM orga­nized as 65, 536 words x 1 bit. Eas y memory expa nsi on is pr o-

vided by an activ e LOW Chi p Enab le (CE

) and three-s tate driv­ers. The CY7C187 has an automatic power-down feature,
reducing the powe r consumption by 56% when desel ected.

Writing to the device is accomplished when the Chip Enable
(CE

) and Write Enab le (WE) input s are both LOW. Data on the

input pin (D

IN

) is written into the memory location spe cified on

the address pins (A

0

through A15).

Reading the devi ce is accompl ished by ta king the Chip Enab le
(CE

) LOW, while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci­fied on the address pin will appear on the data output (D

OUT

)

pin.
The output pin stays in high-impedance state when Chip En-

able (CE

) is HIGH or W r ite E nabl e ( WE) is LOW.

The CY7C187 utilizes a die coat to insure alpha imm unity.

Logic Block Diagram Pin Configurations

256x 256

ARRAY

C187–1

A

12

A

13

A

14

A

15

A

0

A

1

A

2

A

3

A4A

5

A10A

11

COLUMN DECODER

ROW DECODER

SENSE AMPS

INPUT BUFFER

POWER

DOWN

DI

DO

CE

WE

A7A

6

A9A

8

1
2
3
4
5
6
7
8
9
10
11 12

13

14

18
17
16
15

19

22
21
20

Top View

DIP

A

0

A

1

A

2

A

3

A

4

D

OUT

WE

GND

CE

V

CC

A

15

A

14

A

13

A

12

A

10

A

9

A

8

D

IN

A

11

C187–2

WE

1
2
3
4
5
6
7
8

9
10
11

14

15

16

20
19
18
17

21

24
23
22

Top View

SOJ

A

0

A

1

A

2

A

3

A

4

NC

CE

V

CC

A

15

A

14

A

13

A

12

A

10

A

9

A

8

D

IN

NC

GND

D

OUT

12 13

C187–3

A

5

A

6

A

7

A

11

A

5

A

6

A

7

Selection Guid e

[1]

7C187-15 7C187-20 7C187-25 7C187-35

Maximum Access Time (ns) 15 20 25 35
Maximum Operating Curr ent (mA) 90 80 70 70
Maximum Standby Current (mA) 40/20 40/20 20/20 20/20

Note:

1. For military specifications, see the CY7C187A datasheet.

CY7C187

2

Maximum Ratings

(Above which the useful life may be impaired. For use r gui de­lines, not tested.)

Storage Temperature ......................... .. ......–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential

(Pin 22 to Pi n 11 ) ........ ... .. .............................. –0.5V to +7.0V

DC V oltage Applied to Outputs
in High Z State

[2]

............................................ –0.5V to +7.0V

DC Input Voltage

[2]

.........................................–0.5V to +7. 0V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage .......... ............ ............ .........>2001V

(per MIL–STD–883, Method 3015)

Latch-Up Current .....................................................>200 mA

Operating Range

Range

Ambient

Temperature V

CC

Commercial 0°C to +70°C 5V ± 10%

Electrical Characteristics

Over the Operating Range

7C187-15 7C187-20 7C187-25, 35

Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit

V

OH

Output HIGH Voltage VCC = Min.,

I

OH

= –4.0 mA

2.4 2.4 2.4 V

V

OL

Output LOW Voltage VCC = Min.,

I

OL

=1 2.0 mA

0.4 0.4 0.4 V

V

IH

Input HIGH Voltage 2.2 V

CC

2.2 V

CC

2.2 V

CC

V

V

IL

Input LOW Voltage

[2]

–0.5 0.8 –0.5 0.8 –0.5 0.8 V

I

IX

Input Load Current GND < VI < V

CC

–5 +5 –5 +5 –5 +5

µA

I

OZ

Output Leakage
Current

GND < V

O

<

VCC,

Output Disabled

–5 +5 –5 +5 –5 +5

µA

I

OS

Output Short
Circuit Current

[3]

VCC = Max.,
V

OUT

= GND

–350 –350 –350 mA

I

CC

VCC Operating
Supply Current

VCC = Max.,
I

OUT

= 0 mA

90 80 70 mA

I

SB1

Automati c C E Power­Down Current

[4]

Max. VCC, CE ≥ V

IH

40 40 20 mA

I

SB2

Automati c C E
Po wer-Down Current

Max. VCC,
CE

≥ VCC – 0.3V,

V

IN

≥ VCC – 0.3V

or V

IN

≤ 0.3V

20 20 20 mA

Capacitance

[5]

Parameter Description Test Conditions Max. Unit

C

IN

Input Capacitance TA = 25°C, f = 1 MH z,

V

CC

= 5.0V

10 pF

C

OUT

Output Capacitance 10 pF

Notes:

2. V

IL

(min.) = –3.0V for pulse durations less than 30 ns.

3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

4. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.

5. Tested initially and after any design or process changes that may affect these parameters.

CY7C187

3

AC Test Loads and Waveforms

(R1 255ΩMIL)

(R1 255ΩMIL)

(480ΩMIL) (480

Ω

MIL)

3.0V

5V

OUTPUT

R1 329

Ω

R2 202

Ω

30 pF

GND

90%

90%

10%

≤

5ns

≤

5

ns

5V

OUTPUT

C187–4

R2 202

Ω

5

pF

C187–5

(a) (b)

OUTPUT 1.73V

INCLUDING

JIG AND

SCOPE

INCLUDING

JIG AND

SCOPE

R1 329

Ω

Equivalentto: THÉ VENIN EQUIVALENT

10%

OUTPUT 1.90V

Military Commercial

ALL INPUT PULSES

167

Ω

125

Ω

Switching Characteristics

Over the Operating Range

[6]

7C187-15 7C187-20

Parameter Description Min. Max. Min. Max. Unit

READ CYCLE

t

RC

Read Cycle Time 15 20 ns

t

AA

Address to Data Valid 15 20 ns

t

OHA

Output Hold from Address Change 3 5 ns

t

ACE

CE LOW to Data Valid 15 20 ns

t

LZCE

CE LOW to Low Z

[7]

3 5 ns

t

HZCE

CE HIGH to High Z

[7, 8]

8 8 ns

t

PU

CE LOW to Power Up 0 0 ns

t

PD

CE HIGH to Powe r Down 15 20 ns

WRITE CYCLE

[9]

t

WC

Write Cycle Time 15 20 ns

t

SCE

CE LOW to Write End 12 15 ns

t

AW

Address Set-Up to Write End 12 15 ns

t

HA

Address Hold from Write End 0 0 ns

t

SA

Address Set-Up to Write Start 0 0 ns

t

PWE

WE Pulse Width 12 15 ns

t

SD

Data Set-Up to Write End 10 10 ns

t

HD

Data Hold from Write End 0 0 ns

t

LZWE

WE HIGH to Low Z 5 5 ns

t

HZWE

WE LOW to High Z

[8]

7 7 ns

Notes:

6. Tes t conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V , input pulse levels of 0 to 3.0V , and output loading of the specified
I

OL/IOH

and 30-pF load capacitance.

7. At any given temperature and voltage condition, t

HZCE

is less than t

LZCE

for any given device.

8. t

HZCE

and t

HZWE

are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

9. The internal write time of the memory is defined by the overlap of CE

LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can

terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.