Cypress Semiconductor CY7C182-45PC, CY7C182-35VCT, CY7C182-35VC, CY7C182-35PC, CY7C182-25VC Datasheet
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8Kx9 Static RAM
CY7C182
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 4, 1999
Features
• High speed
—t
AA
= 25 ns
• x9 organizat ion is i deal f o r cache mem ory appli cation s
• CMOS for optimum speed/power
• Low active power
—770 mW
• Low standby powe r
—195 mW
• TTL-compatibl e inputs and outputs
• Automat ic power-down when deselected
• Easy memory expansion with CE
1
, CE2, OE options
Functional Description
The CY7C182 is a high-speed CMOS static RAM organized
as 8,192 by 9 bit s and it is man ufact ured using Cypr ess’ s highperformance CMO S technolog y . Access times as f ast as 25 ns
are available with maximum power consumption of only 770
mW.
The CY7C182, which is oriented toward cache mem ory appl ications, features fully static operation requiring no external
clocks or timing strobes. The automatic power-down feature
reduces the power consumption by more than 70% when the
circuit is deselected. Easy memory expansion is provided by
an active-LOW Chip Enable (CE
1
), an active HIGH Chip En-
able (CE
2
), an active-LOW Output Enable (OE), and three-
state drivers.
An active-LOW Write Enable signal (WE
) controls the writ-
ing/reading operation of the m emory. When CE
1
and WE inputs are both LOW, data on the nine data input/output pins
(I/O
0
through I/O8) is written into the memory location ad-
dressed by the address present on the address pins (A
0
through A12). Reading the de vice is a ccompli shed by sel ecting
the devic e an d enab ling the output s , (CE
1
and OE active LO W
and CE
2
active HIGH), while (WE) remains inactive or HIGH.
Under these co nditions , the contents of the location addressed
by the inf ormation on addre ss pins is present on th e nine data
input/output pins.
The input/output pins remain in a high- impedance sta te unless
the chip is selected, outputs are enabled, and write enable
(WE
) is HIGH.
A die coat is used to insure alpha immunity.
Logic Block Diagram
PinConfiguration
C182–1
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
0
A
10
A
9
A11A
12
I/O
0
C182–2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
I/O
2
I/O
3
GND
256 x 32 x 9
ARRAY
INPUT BUFFER
COLUMN
ROW DECODER
SENSE AMPS
POWER
DOWN
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
1
CE
2
WE
OE
Top View
DIP/SOJ
I/O
8
DECODER
Selectio n Gu ide
7C182-25 7C182-35 7C182-45
Maximum Access Time (ns) 25 35 45
Maximum Operating Curr ent (mA) 140 140 140
Maximum Standby Current (mA) 35 35 35
CY7C182
2
Maximum Ratings
(Above which the useful lif e m ay be impaired. For user guidelines, not tested.)
Storage Temperature .....................................−65
°
C to +150°C
Ambient Temperature with
Po wer Applied..................................................−55
°
C to +125°C
Supply Voltage to Ground Potential
[1]
..............−0.5V to +7.0V
DC V oltage Applied to Outputs
in High Z State
[1]
.................................................−0.5V to +7.0V
DC Input Voltage
[1]
..............................................−0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......... ......................... .. ..... >2001V
(per MIL-STD-883, Method 3015.2)
Latch-Up Current............. .. ............ .. ........... ............ >200 mA
Operating Range
Range
Ambient
Temperature
V
CC
Commercial 0°C to + 70°C 5V ± 10%
Electrical Characteristics
Over the Operati ng Range
Parameter Description Test Conditions
7C182-25, 35, 45
Min. Max. Unit
V
OH
Outp ut HIGH Voltage VCC Min., IOH = −4.0 mA. 2.4 V
V
OL
Output LOW Voltage VCC Min., IOL = 8.0 mA 0.4 V
V
IH
Input HIGH Voltage 2.2 V
CC
V
V
IL
Input LOW Voltage
[1]
−0.5
0.8 V
I
IX
Input Load Current GND < VIN < VCC,
GND < V
OUT
< VCC,
Output Disabled
−10
+10
µA
I
OZ
Output Leakage Current V
CC
= Max., V
OUT
= GND
−10
+10
µA
I
OS
Output Short Circuit
Current
[2]
V
CC
= Max., V
OUT
= GND
−300
mA
I
CC
VCC Operating Circui t
Current
VCC Max., Output Current = 0 mA,
f = Max., V
IN
= VCC or GND
140 mA
Auto matic Power- Down
Current — TTL Inputs
Max VCC, CE1 > VIH, CE2 < VIL,
V
IN
> VIH or VIN < VIL, f = f
MAX
35 mA
Auto matic Power- Down
Current — CMOS Inputs
Max VCC, CE1 > VCC − 0.3V, CE2 < 0.3V,
V
IN
> VCC − 0.3V or VIN < 0.3V, f = 0
20 mA
Capacitance
[3]
Parameter Description Test Conditions Max. Unit
C
OUT
Output Capacitance TA = 25°C, f = 1 MHz,
V
CC
= 5.0V
10 pF
C
IN
Input Capacitance 10 pF
Note:
1. V
IL
(min.) = −3.0V for pulse durations of less than 20 ns.
2. Duration of the short circuit should not exceed 30 seconds. Not more than one output should be shorted at one time.
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 481
Ω
R2
255
Ω
30pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
<5ns
<5ns
5V
OUTPUT
R1 481
Ω
R2
255
Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT 1.73V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
C182–3
C182–4
167
Ω
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