Cypress Semiconductor CY7C167A-45PC, CY7C167A-35VCT, CY7C167A-35VC, CY7C167A-35PC, CY7C167A-20VCT Datasheet

16K x 1 Static RAM

7C167A: 12/89
Revisio n: Febr ua ry 3, 2000

CY7C167A

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
February 3, 2000

Features

• Automat ic power-down when deselected

• CMOS for optimum speed/power

• High speed
—15 ns

• Low active power
—495 mW

• Low standb y p ow er
—220 mW

• TTL-compatibl e inputs and outputs

• Capable of wit hstanding greater than 200 1V electrostat-

ic discharge

•V

IH

of 2.2V

Functional Description

The CY7C167A is a high-performance CMOS static RAM or­ganized as 16,384 words by 1 bit. Easy memory expansion is
provided by an active LOW Chip Enable (CE

) and three-state
drivers. The CY7C167A has an automatic power-down fea­ture, reducing the power consumption by 67% when
deselected.

Writing to the device is accomplished when the Chip Select
(CE

) and Write Enab le (WE) input s are both LOW. Data on the
input pin (DI) is written into the memory location specified on
the address pins (A

0

through A13).

Reading the devi ce is accompl ished by ta king the Chip Enab le
(CE

) LOW, while (WE) remains HIGH. Under these condit ions,
the contents of the location specified on the address pins will
appear on the data output (DO) pi n.

The output pin remains in a high-impedance state when Chip
Enable is HIGH, or Write Enable (WE

) is LOW.

A die coat is used to insure alpha immunity.

Logic Block Diagram Pin Configuration

128 x128

ARRAY

C167A-1

Top View

DIP

A

1

A

2

A

3

A

4

A

0

COLUMN

DECODER

ROW DECODER

SENSE AMP

INPUTBUFFER

POWER

DOWN

WE

CE

DO

A

5

DI

A

6

A

9

A

10

A7A

8

A11A12A

13

1
2
3
4
5
6
7
8
9
10

11

12

13

14

18

17
16
15

7C167A

A

1

A

2

A

3

A

4

A

5

DO

CE

GND

WE

V

CC

A

12

A

11

A

10

C167A-2

A

0

A

9

A

8

A

7

DI

A

6

A

13

20
19

Selection Guid e

7C167A-15 7C167A-20 7C167A-25 7C167A-35 7C167A-45

Maximum Access Time (ns) 15 20 25 35 45
Maximum Operating Curr ent (mA) 90 90 90 90 90

CY7C167A

7C167A: 12/89
Revision: February 3, 2000

2

Maximum Ratings

(Above which the useful life may be impa ir ed. For user guide­lines, not tested.)

Storage Temperature

.....................................−65°

C to +150°C

Ambient Temperature with
Po wer Applied

..................................................−55°

C to +125°C

Supply Voltage to Ground Potential
(Pin 20 to Pin 10)

................................................ −

0.5V to +7.0V

DC V oltage Applied to Outputs
in High Z State

.................................................... −

0.5V to +7.0V

DC Input Voltage

.................................................−

3.0V to +7 . 0V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage .......... ............ .....................>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current .....................................................>200 mA

Operating Range

Range

Ambient

Temperature

[1]

V

CC

Commercial 0°C to +70°C 5V ± 10%

Electrical Characteristics

Over the Operating Range

7C167A-15 7C167A-20 7C167A-25

Parameter Description Te st Condi tions Min. Max. Min. Max. Min. Max. Unit

V

OH

Output High Voltage VCC = Min., IOH = −4.0 mA 2.4 2.4 2.4 V

V

OL

Output Low Voltage VCC = Min.,

I

OL

= 12.0 mA, 8.0 mA Mil

0.4 0.4 0.4 V

V

IH

Input High V oltage 2.2 V

CC

2.2 V

CC

2.2 V

CC

V

V

IL

Input Low Voltage

[2]

−

0.5

0.8

−

0.5

0.8

−

0.5

0.8 V

I

IX

Input Load Current GND < VI < V

CC

−

10

+10

−

10

+10

−

10

+10

µ

A

I

OZ

Output Leakage
Current

GND < VO < V

CC

Output Disabled

−

10

+10

−

10

+10

−

10

+10

µ

A

I

OS

Output Short
Circuit Current

[3]

VCC = Max., V

OUT

= GND

−

350

−

350

−

350

mA

I

CC

VCC Operating
Supply Current

V

CC =

Max., I

OUT

= 0 mA 90 90 90 mA

I

SB

Auto mati c CE
Power-Down Current

[4]

Max. VCC, CE > V

IH

40 40 20 mA

7C167A-35 7C167A-45

Parameter Description Te st Condi tions Min. Max. Min. Max. Unit

V

OH

Output High Voltage VCC = Min., IOH = −4.0 mA 2.4 2.4 V

V

OL

Output Low Voltage VCC = Min.,

I

OL

= 12.0 mA, 8.0 mA Mil

0.4 0.4 V

V

IH

Input High V oltage 2.2 V

CC

2.2 V

CC

V

V

IL

Input Low Voltage

[2]

−

0.5

0.8

−

0.5

0.8 V

I

IX

Input Load Current GND < VI < V

CC

−

10

+10

−

10

+10

µ

A

I

OZ

Output Leakage
Current

GND < VO < V

CC

Output Disabled

−

10

+10

−

10

+10

µ

A

I

OS

Output Short
Circuit Current

[3]

VCC = Max., V

OUT

= GND

−

350

−

350

mA

I

CC

VCC Operating
Supply Current

V

CC =

Max., I

OUT

= 0 mA 90 90 mA

I

SB

Auto mati c CE
Power-Down Current

[4]

Max. VCC, CE > V

IH

20 20 mA

Notes:

1. T

A

is the case temperature.

2. VIL min. = −3.0V for pulse durations less than 30 ns.

3. Duration of the short circuit should not exceed 30 seconds.

4. A pull-up resistor to V

CC

on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.

CY7C167A

7C167A: 12/89
Revision: February 3, 2000

3

Capacitance

[5]

Parameter Description Test Conditions Max. Unit

C

IN

Input Capacitance TA = 25°C, f = 1 MH z ,

V

CC

= 5.0V

10 pF

C

OUT

Output Capacitance 10 pF

C

CE

Chip Enable Capacitance 6 pF

AC Test Loads and Waveforms

3.0V

5V

OUTPUT

R1 329

Ω

R2
202

Ω

30pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

<5ns

<5

ns

5V

OUTPUT

C167A-3

R1 329

Ω

R2
202

Ω

5pF

INCLUDING

JIG AND

SCOPE

C167A-4

(a) (b)

OUTPUT 1.9V

Equivalent to: THÉ VENINEQUIVALENT

ALL INPUT PULSES

125

Ω

Switching Characteristics

Over the Operating Range

[6]

7C167A-15 7C167A-20 7C167A-25 7C167A-35 7C167A-45

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

READ CYCLE

t

RC

Read Cycle Time 15 20 25 30 ns

t

AA

Address to Data Valid 15 20 25 30 ns

t

OHA

Data Hold fr om Address Change 5 5 5 5 5 ns

t

ACE

CE LOW to Data Valid 15 20 25 35 45 ns

t

LZCE

CE LOW to Low Z

[7]

5 5 5 5 5 ns

t

HZCE

CE HIGH to High Z

[7, 8]

8 8 10 15 15 ns

t

PU

CE LOW to Power-Up 0 0 0 0 0 ns

t

PD

CE HIGH to Powe r-Down 15 20 20 20 25 ns

WRITE CYCLE

[9]

t

WC

Write Cycle Time 15 20 20 25 40 ns

t

SCE

CE LOW to Write End 12 15 20 25 30 ns

t

AW

Address Set-Up to Write End 12 15 20 25 30 ns

t

HA

Address Hold from Write End 0 0 0 0 0 ns

t

SA

Address Set-Up to Write Start 0 0 0 0 0 ns

t

PWE

WE Pulse Width 12 15 15 20 20 ns

t

SD

Data Set-Up to Write End 10 10 10 15 15 ns

t

HD

Data Hold from Write End 0 0 0 0 0 ns

t

HZWE

WE LOW to High Z

[7, 8]

7 7 7 10 15 ns

t

LZWE

WE HIGH to Low Z

[7]

5 5 5 5 5 ns

Notes:

5. Tested initially and after any design or process changes that may affect these parameters.

6. Tes t conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V , and output loading of the specified
I

OL/IOH

and 30-pF load capacitance.

7. At any given temperature and voltage condition, t

HZ

is less than tLZ for any given device.

8. t

HZCE

and t

HZWE

are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.

9. The internal write time of the memory is defined by the overlap of CE

LOW and WE LOW. Both signal must be LOW to initiate a write and either signal can

terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

CY7C167A

7C167A: 12/89
Revision: February 3, 2000

4

Switching Waveforms

Notes:

10. WE

is high for read cycle.

11. Device is continuously selected, CE

= VIL.

12. Address valid prior to or coincident with CE

transition LOW.

C167A-5

50%

PREVIOUS DATA VALID

DATA VALID

t

RC

t

AA

50%

DATA VALID

t

RC

t

ACE

t

LZCE

t

PU

DATA OUT

HIGH IMPEDANCE

IMPEDANCE

I

CC

I

SB

t

HZCE

t

PD

CE

HIGH

C167A-6

V

CC

SUPPLY

CURRENT

t

OHA

Read Cycle No. 1

[10, 11]

Read Cycle No. 2

[10, 12]

ADDRESS

DATA OUT

t

WC

DATA UNDEFINED

HIGH IMPEDANCE

t

SCE

t

AW

t

SA

t

PWE

t

HA

t

HD

t

HZWE

t

LZWE

t

SD

C167A-7

CE

WE

DATA IN

DATA I/O

ADDRESS

DATAINVALID

Write Cycle No. 1 (WE Controlled)

[9]

CY7C167A

7C167A: 12/89
Revision: February 3, 2000

5

Note:

13. If CE

goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.

Switching Waveforms

(continued )

t

WC

DATA UNDEFINED

HIGH IMPEDANCE

t

SCE

t

AW

t

PWE

t

HA

t

HD

t

HZWE

t

SD

ADDRESS

CE

WE

DATA IN

DATA I/O

t

SA

C167A-8

DATAINVALID

Write Cycle No. 2 (CE Controlled)

[9, 13 ]

CY7C167A

7C167A: 12/89
Revision: February 3, 2000

6

T y pical DC and AC Characteris ti cs

1.2

1.4

1.0

0.6

0.4

0.2

4.0 4.5 5.0 5.5 6.0

1.6

1.4

1.2

1.0

0.8

-55 25 125

−

55 25 125

1.2

1.0

0.8

NORMALIZED t

AA

60

50

40

30

20
10

0 1.0 2.0 3.0 4.0

OUTPUT SOURCE CURRENT (mA)

SUPPLY VOLTAGE (V)

NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE

NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C)

NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE

AMBIENT TEMPERATURE (°C)

OUTPUT VOLTAGE (V)

OUTPUT SOURCE CURRENT
vs. OUTPUT

VOLTAGE

0.0

0.8

1.4

1.1

1.0

0.9

4.0 4.5 5.0 5.5 6.0

NORMALIZED t

SUPPLY VO LTAG E (V)

NORMALIZED ACCESS TIME
vs. SUPPLY

VOLTAGE

150
125

75
50

25

0.0 1.0 2.0 3.0 4.0

OUTPUT SINK CURRENT (mA)

0

100

OUTPUT VOLTAGE (V)

OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE

0.6

0.4

0.2

0.0

NORMA LIZED I , I

CC SB

NORMA LIZED I , I

CC SB

I

SB

VCC= 5.0V
V

IN

= 5.0V

I

CC

I

CC

VCC= 5.0V

V

CC

= 5.0V

T

A

= 25°C

I

SB

TA= 25°C

0.6

0.8

0

AA

1.3

1.2

V

CC

= 5.0V

T

A

= 25°C

5.0

3.0

2.5

2.0

1.5

1.0

0.5

0.0 1.0 2.0 3.0 4.0

NORMALIZED I

PO

SUPPLY VOLTAGE (V)

TYPICAL POWER-ON CURRENT
vs. SUPPLY

VOLTAGE

30.0

20.0

10.0

0 200 400 600 800

DELTA t (ns)

AA

CAPACITANCE (pF)

TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING

1.1

1.0

0.9

10 20 30 40

NORMALIZED I

CC

CYCLE FREQUENCY (MHz)

NORMALIZED I

CC

vs. CYCLE TIME

0.0

5.0

0.0
1000

0.8

V

CC

= 4.5V

T

A

= 25°C

V

CC

= 5.0V

T

A

= 25°C

V

IH

= 0.5V

CY7C167A

7C167A: 12/89
Revision: February 3, 2000

7

Document #: 38-00093-E

Ordering Information

Speed (ns) ICC (mA) Ordering Code Package Name Package Type Operating Range

15 80 CY7C167A-15PC P5 20-Lead (300-Mil) Molded DIP Commercial

CY7C167A-15VC V5 20-Lead Molded SOJ

20 80 CY7C167A-20PC P5 20-Lead (300-Mil) Molded DIP Commercial

CY7C167A-20VC V5 20-Lead Molded SOJ

25 60 CY7C167A-25PC P5 20-Lead (300-Mil) Molded DIP Commercial

CY7C167A-25VC V5 20-Lead Molded SOJ

35 60 CY7C167A-35PC P5 20-Lead (300-Mil) Molded DIP Commercial

CY7C167A-35VC V5 20-Lead Molded SOJ

45 50 CY7C167A-45PC P5 20-Lead (300-Mil) Molded DIP Commercial

CY7C167A-45VC V5 20-Lead Molded SOJ

CY7C167A

7C167A: 12/89
Revision: February 3, 2000

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagrams

51-85011-A

20-Lead(300-Mil)Molded DIPP5

20-Lead (300-Mil) Molded SOJ V5

51-85029-A