Cypress Semiconductor CY7C1561V18, CY7C1563V18, CY7C1565V18, CY7C1576V18 User Manual

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72-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.5 Cycle Read Latency)

CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18

Features

Note

1. The QDR consortium specification for V

DDQ

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting

DDQ

= 1.4V to VDD.

Configurations

■ Separate independent read and write data ports ❐ Supports concurrent transactions

■ 400 MHz clock for high bandwidth

■ 4-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 800 MHz) at 400 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency, providing most current data

■ Core V

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

= 1.8V ± 0.1V; IO V

= 1.4V to V

DDQ

[1]

With Read Cycle Latency of 2.5 cycles:

CY7C1561V18 – 8M x 8 CY7C1576V18 – 8M x 9 CY7C1563V18 – 4M x 18 CY7C1565V18 – 2M x 36

Functional Description

The CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II+ architecture. Similar to QDR-II architecture, QDR-II+ SRAMs consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that exists with common IO devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words (CY7C1561V18), 9-bit words (CY7C1576V18), 18-bit words (CY7C1563V18), or 36-bit words (CY7C1565V18) that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks (K and K fying system design by eliminating bus “turn-arounds”.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K registers controlled by the K or K conducted with on-chip synchronous self-timed write circuitry.

), memory bandwidth is maximized while simpli-

input clocks. All data outputs pass through output

input clocks. Writes are

Selection Guide

Description 400 MHz 375 MHz 333 MHz 300 MHz Unit

Maximum Operating Frequency 400 375 333 300 MHz Maximum Operating Current x8 1400 1300 1200 1100 mA

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-05384 Rev. *F Revised March 6, 2008

x9 1400 1300 1200 1100 x18 1400 1300 1200 1100 x36 1400 1300 1200 1100

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CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18

Logic Block Diagram (CY7C1561V18)

2M x 8 Array

CLK

(20:0)

Gen.

Control

Logic

Address Register

[7:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address Register

Reg.

NWS

[1:0]

REF

Write Add. Decode

Write

Reg

(20:0)

2M x 8 Array

DOFF

[7:0]

QVLD

Write

Reg

Write

Reg

Write

Reg

2M x 9 Array

CLK

(20:0)

Gen.

Control

Logic

Address Register

[8:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address Register

Reg.

BWS

[0]

REF

Write Add. Decode

Write

Reg

(20:0)

2M x 9 Array

DOFF

[8:0]

QVLD

Write

Reg

Write

Reg

Write

Reg

Logic Block Diagram (CY7C1576V18)

Document Number: 001-05384 Rev. *F Page 2 of 28

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CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18

Logic Block Diagram (CY7C1563V18)

1M x 18 Array

CLK

(19:0)

Gen.

Control

Logic

Address Register

[17:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address

Reg.

BWS

[1:0]

REF

Write Add. Decode

Write

Reg

(19:0)

1M x 18 Array

DOFF

[17:0]

QVLD

Write

Reg

Write

Reg

Write

Reg

512K x 36 Array

CLK

(18:0)

Gen.

Control

Logic

Address Register

[35:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address Register

Reg.

144

BWS

[3:0]

REF

Write Add. Decode

Write

Reg

(18:0)

512K x 36 Array

DOFF

[35:0]

QVLD

Write

Reg

Write

Reg

Write

Reg

Logic Block Diagram (CY7C1565V18)

Document Number: 001-05384 Rev. *F Page 3 of 28

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CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18

Pin Configuration

Note

2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

The pin configuration for CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 follow.

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1561V18 (8M x 8)

1 2 3 4 5 6 7 8 9 10 11

A CQ AAWPSNWS

B NC NC NC A NC/288M K NWS C NC NC NC V D NC D4 NC V E NC NC Q4 V F NC NC NC V G NC D5 Q5 V H DOFF V

REF

DDQ

J NC NC NC V K NC NC NC V L NC Q6 D6 V M NC NC NC V N NC D7 NC V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

ANCAVSSNC NC D3

AAAVSSNC NC NC

P NC NC Q7 A A QVLD A A NC NC NC R TDOTCKAAANCAAATMSTDI

K NC/144M RPS AACQ

ANCNCQ3

DDQ

[2]

NC NC NC NC D2 Q2 NC NC NC NC NC NC

DDQ

REF

NC Q1 D1 NC NC NC NC NC Q0 NC NC D0

CY7C1576V18 (8M x 9)

1 2 3 4 5 6 7 8 9 10 11

A CQ AAWPSNC K NC/144M RPS AACQ B NC NC NC A NC/288M K BWS C NC NC NC V D NC D5 NC V E NC NC Q5 V F NC NC NC V G NC D6 Q6 V H DOFF V

REF

DDQ

J NC NC NC V K NC NC NC V L NC Q7 D7 V M NC NC NC V N NC D8 NC V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

ANCAVSSNC NC D4

AAAVSSNC NC NC

ANCNCQ4

V V V V V V V

DDQ DDQ DDQ DDQ DDQ DDQ DDQ

NC NC NC NC D3 Q3 NC NC NC NC NC NC

DDQ

REF

NC Q2 D2 NC NC NC NC NC Q1 NC NC D1

P NC NC Q8 A A QVLD A A NC D0 Q0 R TDOTCKAAANCAAATMSTDI

Document Number: 001-05384 Rev. *F Page 4 of 28

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CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18

Pin Configuration (continued)

The pin configuration for CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 follow.

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1563V18 (4M x 18)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/144M A WPS BWS

B NC Q9 D9 A NC K BWS C NC NC D10 V D NC D11 Q10 V E NC NC Q11 V F NC Q12 D12 V G NC D13 Q13 V H DOFF V

REF

DDQ

J NC NC D14 V K NC NC Q14 V L NC Q15 D15 V M NC NC D16 V N NC D17 Q16 V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

ANCAVSSNC Q7 D8

AAAVSSNC NC D1

P NC NC Q17 A A QVLD A A NC D0 Q0 R TDOTCKAAANCAAATMSTDI

K NC/288M RPS AACQ

ANCNCQ8

DDQ

[2]

NC NC D7 NC D6 Q6 NC NC Q5 NC NC D5

DDQ

REF

NC Q4 D4 NC D3 Q3 NC NC Q2 NC Q1 D2

CY7C1565V18 (2M x 36)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/288M A WPS BWS B Q27 Q18 D18 A BWS C D27 Q28 D19 V D D28 D20 Q19 V E Q29 D29 Q20 V F Q30 Q21 D21 V G D30 D22 Q22 V H DOFF V

REF

DDQ

J D31 Q31 D23 V K Q32 D32 Q23 V L Q33 Q24 D24 V M D33 Q34 D25 V N D34 D26 Q25 V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

ANCAVSSD16 Q7 D8

AAAVSSQ10 D9 D1

2 3

K BWS

RPS A NC/144M CQ

KBWS0AD17Q17Q8

V V V V V V V

DDQ DDQ DDQ DDQ DDQ DDQ DDQ

Q16 D15 D7 Q15 D6 Q6 D14 Q14 Q5 Q13 D13 D5

DDQ

REF

D12 Q4 D4 Q12 D3 Q3 D11 Q11 Q2 D10 Q1 D2

P Q35 D35 Q26 A A QVLD A A Q9 D0 Q0 R TDOTCKAAANCAAATMSTDI

Document Number: 001-05384 Rev. *F Page 5 of 28

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CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18

Pin Definitions

Pin Name IO Pin Description

[x:0]

Input-

Synchronous

WPS Input-

Synchronous

NWS NWS1,

BWS BWS BWS BWS

2 3

Input-

Synchronous

Input-

Synchronous

A Input-

Synchronous

[x:0]

Outputs-

Synchronous

RPS Input-

Synchronous

Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active. CY7C1561V18 − D CY7C1576V18 − D

CY7C1563V18 − D CY7C1565V18 − D

[7:0] [8:0] [17:0] [35:0]

Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a write operation is initiated. Deasserting deselects the Write Port. Deselecting the write port ignores D

[x:0]

Nibble Write Select 0, 1− Active LOW (CY7C1561V18 Only). Sampled on the rising edge of the K and K

clocks when write operations are active. Used to select which nibble is written into the device during the current portion of the write operations. NWS All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

controls D

and NWS1 controls D

[3:0]

[7:4]

ignores the corresponding nibble of data and it is not written into the device. Byte Write Select 0, 1, 2, and 3 − Active LOW . Sampled on the rising edge of the K and K clocks when

write operations are active. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1576V18 − BWS CY7C1563V18 − BWS0 controls D CY7C1565V18 − BWS0 controls D BWS

controls D

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

controls D

and BWS3 controls D

[26:18]

[8:0]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[35:27].

[17:9]

[17:9].

ignores the corresponding byte of data and it is not written into the device. Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These

address inputs are multiplexed for both read and write operations. Internally, the device is organized as 8M x 8 (4 arrays each of 2M x 8) for CY7C1561V18, 8M x 9 (4 arrays each of 2M x 9) for CY7C1576V18, 4M x 18 (4 arrays each of 1M x 18) for CY7C1563V18 and 2M x 36 (4 arrays each of 512K x 36) for CY7C1565V18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1561V18 and CY7C1576V18, 20 address inputs for CY7C1563V18, and 19 address inputs for CY7C1565V18. These inputs are ignored when the appropriate port is deselected.

Data Output Signals. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the K and K port, Q CY7C1561V18 − Q CY7C1576V18 − Q CY7C1563V18 − Q CY7C1565V18 − Q

are automatically tri-stated.

[x:0]

[7:0] [8:0] [17:0] [35:0]

clocks during read operations. On deselecting the read

Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the K

clock. Each read access consists of a burst of four sequential transfers.

QVLD Valid output

Valid Outp ut Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ

indicator

K Input-

Clock

InputClock

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q

Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q

CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock

(K) of the QDR-II+. The timings for the echo clocks are shown in the Switching Characteristics on page 23.

Echo Clock Synchronous Echo Clock Outputs . This is a free running clock and is synchronized to the input clock

) of the QDR-II+. The timings for the echo clocks are shown in the Switching Characteristics on page 23.

Document Number: 001-05384 Rev. *F Page 6 of 28

[x:0]

. All accesses are initiated on the risin g ed ge of K.

[x:0]

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Pin Definitions (continued)

Pin Name IO Pin Description

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

impedance. CQ, CQ between ZQ and ground. Alternately, this pin can be connected directly to V minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

DOFF Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device.The timings

in the DLL turned off operation are different from those listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR-I mode when the DLL is turned off. In this mode, the device can b e operated at a frequency o f up to 167 MHz with QDR-I timing.

TDO Output TDO for JTAG. TCK Input TCK Pin for JTAG. TDI Input TDI Pin for JTAG. TMS Input TMS Pin for JTAG. NC N/A Not Connected to the Die. Can be tied to any voltage level.

NC/144M N/A Not Connected to the Die. Can be tied to any voltage level. NC/288M N/A Not Connected to the Die. Can be tied to any voltage level.

and Q

output impedance are set to 0.2 x RQ, where RQ is a resistor connected

[x:0]

, which enables the

DDQ

V V V

REF

DD SS DDQ

Input-

Reference

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points.

Document Number: 001-05384 Rev. *F Page 7 of 28

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CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18

Functional Overview

The CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 are synchronous pipelined Burst SRAMs equipped with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the QDR-II+ completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1561V18, four 9-bit data transfers in the case of CY7C1576V18, four 18-bit data transfers in the case of CY7C1563V18, and four 36-bit data transfers in the case of CY7C1565V18, in two clock cycles.

Accesses for both ports are initiated on the positive input clock (K). All synchronous input and output timing are referenced from the rising edge of the input clocks (K and K

All synchronous data inputs (D registers controlled by the input clocks (K and K synchronous data outputs (Q registers controlled by the rising edge of the input clocks (K and

[x:0]

) outputs pass through output

[x:0]

K) as well. All synchronous control (RPS

, WPS, NWS pass through input registers controlled by the rising edge of the input clocks (K and K

CY7C1563V18 is described in the following sections. The same basic descriptions apply to CY7C1561V18, CY7C1576V18, and CY7C1565V18.

Read Operations

The CY7C1563V18 is organized internally as four arrays of 1M x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address presented to address inputs are stored in the read address register. Following the next two K sponding lowest order 18-bit word of data is driven onto the

using K as the output timing reference. On the su bse-

[17:0]

quent rising edge of K, the next 18-bit data word is driven onto the Q have been driven out onto Q

0.45 ns from the rising edge of the input clock (K or K maintain the internal logic, each read access must be allowed to complete. Each read access consists of four 18-bit data words and takes two clock cycles to complete. Therefore, read accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device ignores the second read request. Read accesses can be initiated on every other K clock rise. Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the input clocks (K and K

When the read port is deselected, the CY7C1563V18 first completes the pending read transactions. Synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the negative input clock (K

. This process continues until all four 18-bit data words

[17:0]

. The requested data is valid

[17:0]

) inputs pass through input

). All

[x:0]

, BWS

[x:0]

) inputs

clock rise, the corre-

). To

). This enables for a

seamless transition between devices without the insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the following K clock rise the data presented to D the lower 18-bit write data register, provided BWS asserted active. On the subsequent rising edge of the negative input clock (K) the information presented to D into the write data register, provided BWS active. This process continues for one more cycle until four 18-bit

is latched and stored into

[17:0]

[1:0]

is also stored

[17:0]

are both asserted

[1:0]

are both

words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, write accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device ignores the second write request. Write accesses can be initiated on every other rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K

When deselected, the write port ignores all inputs after the pending write operations have been completed.

Byte Write Operations

Byte write operations are supported by the CY7C1563V18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS

, which are sampled with each set of 18-bit data words.

BWS

Asserting the appropriate Byte Write Select input during the data

and

portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read, modify, or write operations to a Byte write operation.

Concurrent Transactions

The read and write ports on the CY7C1563V18 operates completely independently of one another. As each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a write in successive clock cycles, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise.

Read access and write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports are deselected, the read port takes priority. If a read was initiated on the previous cycle, the write port takes priority (as read operations cannot be initiated on consecutive cycles). If a write was initiated on the previous cycle, the read port takes priority (since write operations cannot be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state results in alternating read or write operations being initiated, with the first access being a read.

Document Number: 001-05384 Rev. *F Page 8 of 28

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Depth Expansion

The CY7C1563V18 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed prior to the device being deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V driver impedance. The value of RQ must be 5X the value of the

to allow the SRAM to adjust its output

intended line impedance driven by the SRAM, the allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω output impedance is adjusted every 1024 cycles upon power up

, with V

=1.5V. The

DDQ

to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the QDR-II+ to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II+. CQ is referenced with respect to K and CQ is referenced with respect to K

. These are free-running clocks and are synchronized to the input clock of the QDR-II+. The timing for the echo clocks are shown in Switching Characteristics on page 23.

Application Example

Valid Data Indicator (QVLD)

QVLD is provided on the QDR-II+ to simplify data capture on high speed systems. The QVLD is generated by the QDR-II+ device along with data output. This signal is also edge-aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives.

DLL

These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in QDR-I mode (with 1.0 cycle latency and a longer access time ). For more information, refer to the application note, “DLL Considerations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be reset by slowing or stopping the input clocks K and K minimum of 30ns. However, it is not necessary to reset the DLL to lock to the desired frequency. During Power up, when the DOFF

is tied HIGH, the DLL is locked after 2048 cycles of stable

clock.

for a

Figure 1 shows four QDR-II+ used in an application.

Figure 1. Application Example

SRAM #1

WPS

RPS

DATA OUT

BUS MASTER

(CPU or ASIC)

CLKIN/CLKIN

DATA IN

Address

RPS WPS BWS

Source K Source K

BWS

CQ/CQ

RQ = 250ohms

D A

SRAM #4

WPS

RPS

R = 50ohms, Vt = V /2

BWS

CQ/CQ

DDQ

RQ = 250ohms

Document Number: 001-05384 Rev. *F Page 9 of 28

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The truth table for CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 follows.

Notes

3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,

↑represents rising edge.

4. Device powers up deselected with the outputs in a tri-state condition.

5. “A” represents address location latched by the devices when transact i on was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.

6. “t” represents the cycle at which a read/write operation is sta rted. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.

7. Data inputs are registered at K and K

rising edges. Data outputs are delivered on K and K rising edges also.

8. It is recommended that K = K

= HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line ch arging symmetrically.

9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.

10.This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the second read or write request.

11.Is based on a write cycle was initiated per the The write cycle description table for CY7C1561V18 and CY7C1563V18 follows.

[3, 11]

table. NWS0, NWS1, BWS0, BWS1,

BWS

and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved.

[3, 4, 5, 6, 7, 8]

T ruth Table

Operation K RPS WPS DQ DQ DQ DQ

Write Cycle:

L-H H

[9]L[10]

D(A) at K(t + 1) ↑ D(A + 1) at K(t + 1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑ Load address on the rising edge of K; input write data on two consecutive K and K

rising edges.

Read Cycle:

L-H L

[10]

XQ(A) at K(t + 2)↑ Q(A + 1) at K(t + 3) ↑ Q(A + 2) at K(t + 3)↑ Q(A + 3) at K(t + 4) ↑ (2.5 cycle Latency) Load address on the rising edge of K; wait two and a half cycles; read data on two consecutive K

and K

rising edges. NOP: No Operation L-H H H D = X

Q = High-Z

D = X Q = High-Z

Standby: Clock Stopped Stopped X X Previous State Previous State Previous State Previous State

[3, 11]

The write cycle description table for CY7C1561V18 and CY7C1563V18 follows.

Write Cycle Descriptions

BWS0/

NWS

BWS1/

NWS

Comments

L L L–H – During the data portion of a write sequence:

CY7C1561V18 − both nibbles (D CY7C1563V18 − both bytes (D

) are written into the device,

[7:0]

) are written into the device.

[17:0]

L L – L-H Durin g the data portion of a write sequence:

CY7C1561V18 − both nibbles (D CY7C1563V18 − both bytes (D

) are written into the device,

[7:0]

) are written into the device.

[17:0]

L H L–H – During the data portion of a write sequence:

CY7C1561V18 − only the lower nibble (D CY7C1563V18 − only the lower byte (D

) is written into the device, D

[3:0]

) is written into the device, D

[8:0]

L H – L–H During the data portion of a write sequence:

CY7C1561V18 − only the lower nibble (D CY7C1563V18 − only the lower byte (D

) is written into the device, D

[3:0]

) is written into the device, D

[8:0]

H L L–H – During the data portion of a write sequence:

CY7C1561V18 − only the upper nibble (D CY7C1563V18 − only the upper byte (D

) is written into the device, D

[7:4]

) is written into the device, D

[17:9]

H L – L–H During the data portion of a write sequence :

CY7C1561V18 − only the upper nibble (D CY7C1563V18 − only the upper byte (D

) is written into the device, D

[7:4]

) is written into the device, D

[17:9]

H H L–H – No data is written into the devices during this portion of a write operation. H H – L–H No data is written into the devices during this portion of a write operation.

remains unaltered.

[7:4]

remains unaltered.

[17:9]

remains unaltered.

[7:4]

remains unaltered.

[17:9]

remains unaltered.

[3:0]

remains unaltered.

[8:0]

remains unaltered.

[3:0]

remains unaltered.

[8:0]

Document Number: 001-05384 Rev. *F Page 10 of 28

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The write cycle description table for CY7C1576V18 follows.

Write Cycle Descriptions

[3, 11]

BWS

L L–H – During the Data portion of a write sequence, the single byte (D L – L–H During the Data portion of a write sequence, the single byte (D

K K

) is written into the device.

[8:0]

) is written into the device.

[8:0]

H L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into the device during this portion of a write operation.

The write cycle description table for CY7C1565V18 follows.

[3, 11]

Write Cycle Descriptions

BWS0BWS1BWS2BWS3K K Comments

LLLLL–H–During the Data portion of a write sequence, all four bytes (D

the device.

LLLL–L–HDuring the Data portion of a write sequence, all four bytes (D

the device.

L H H H L–H – During the Data portion of a write sequence, only the lower byte (D

into the device. D

remains unaltered.

[35:9]

L H H H – L–H During the Data portion of a write sequence, only the lower byte (D

into the device. D

remains unaltered.

[35:9]

H L H H L–H – During the Data portion of a write sequence, only the byte (D

the device. D

[8:0]

and D

remains unaltered.

[35:18]

H L H H – L–H During the Data portion of a write sequence, only the byte (D

the device. D

[8:0]

and D

remains unaltered.

[35:18]

H H L H L–H – During the Data portion of a write sequence, only the byte (D

the device. D

[17:0]

and D

remains unaltered.

[35:27]

H H L H – L–H During the Data portion of a write sequence, only the byte (D

the device. D

[17:0]

and D

remains unaltered.

[35:27]

H H H L L–H – During the Data portion of a write sequence, only the byte (D

the device. D

remains unaltered.

[26:0]

H H H L – L–H During the Data portion of a write sequence, only the byte (D

the device. D

remains unaltered.

[26:0]

HHHHL–H–No data is written into the device during this portion of a write operation. HHHH–L–HNo data is written into the device during this portion of a write operation.

[35:0]

[17:9]

[26:18]

[35:27]

) are written into

) is written

[8:0]

) is written

[8:0]

) is written into

Document Number: 001-05384 Rev. *F Page 11 of 28

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IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA p ackage. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to V unconnected. Upon power up, the device comes up in a reset state, which does not interfere with the operation of the device.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the The state diagram for the

T AP controller follows.

and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data out from th e registers. The output is active, depending upon the current state of the TAP state machine (see Instruction Codes on page 17). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of th e SRAM and can be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK.

through a pull up resistor. TDO must be left

[12]

on page 14. TDI is internally pulled up

Instruction Register

Three-bit instructions can be serially loaded into the instructi on register. This register is loaded when it is placed between the TDI and TDO pins, as shown in TAP Controller Block Diagram on page 15. Upon power up, the instruction register i s loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section.

When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (V the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all of th e input and output pins on the SRAM. Several No Connect (NC) pins are also included in the scan register to reserve pins for higher density devices.

The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring.

Boundary Scan Order on page 18 shows the order in which the

bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions on page 17.

) when

TAP Instruction Set

Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction

Codes on page 17. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions are described in this section in detail.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state.

Document Number: 001-05384 Rev. *F Page 12 of 28

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IDCODE

The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is supplied during the Update-IR state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible.

To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (t correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK

After the data is captured, it is possible to shift out the data by putting the T AP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

and tCH). The SRAM clock input might not be captured

captured in the boundary scan register.

PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, the data captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boun dary scan path when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state.

EXTEST OUTPUT BUS TRI-ST ATE

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #108. When this scan cell, called the “extest output bus tri-state”, is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

Document Number: 001-05384 Rev. *F Page 13 of 28

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The state diagram for the TAP controller follows.

TEST-LOGIC RESET

TEST-LOGIC/ IDLE

SELECT DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDA TE-DR

SELECT IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDA TE-IR

Note

12.The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

TAP Controller State Diagram

[12]

Document Number: 001-05384 Rev. *F Page 14 of 28

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TAP Controller Block Diagram

012..293031

Boundary Scan Register

Identification Register

012....108

012

Instruction Register

Bypass Register

Selection Circuitry

TA P Controller

TDI

TDO

TCK TMS

Notes

13.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

14.Overshoot: V

(AC) < V

DDQ

+ 0.35V (Pulse width less than t

CYC

/2), Undershoot: VIL(AC) > −0.3V (Pulse width less than t

CYC

/2).

15.All Voltage referenced to Ground.

TAP Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Max Unit

OH1

OH2

OL1

OL2

Output HIGH Voltage I Output HIGH Voltage I Output LOW Voltage IOL = 2.0 mA 0.4 V Output LOW Voltage IOL = 100 μA0.2V Input HIGH Voltage 0.65VDDV Input LOW Voltage –0.3 0.35V Input and Output Load Current GND ≤ VI ≤ V

[13, 14, 15]

= −2.0 mA 1.4 V

= −100 μA1.6 V

–5 5 μA

+ 0.3 V

Document Number: 001-05384 Rev. *F Page 15 of 28

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TAP AC Switching Characteristics

(a)

TDO

= 20 pF

= 50

GND

0.9V

1.8V

ALL INPUT PULSES

0.9V

Test Clock

Test Mode Select

TCK

TMS

Test Data In TDI

Test Data Out

TCYC

TMSH

TMSS

TDIS

TDIH

TDOV

TDOX

TDO

Notes

16.t

and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

17.Test conditions are specified using the load in TAP AC Test Conditions. t

R/tF

= 1 ns.

Over the Operating Range

Parameter Description Min Max Unit

TCYC

TCK Clock Cycle Time 50 ns TCK Clock Frequency 20 MHz TCK Clock HIGH 20 ns TCK Clock LOW 20 ns

Setup Times

TMSS

TDIS

TMS Setup to TCK Clock Rise 5 ns TDI Setup to TCK Clock Rise 5 ns Capture Setup to TCK Rise 5 ns

Hold Times

TMSH

TDIH

TMS Hold after TCK Clock Rise 5 ns TDI Hold after Clock Rise 5 ns Capture Hold after Clock Rise 5 ns

Output Times

TDOV

TDOX

TCK Clock LOW to TDO Valid 10 ns TCK Clock LOW to TDO Invalid 0 ns

[16, 17]

TAP Timing and Test Conditions

Figure 2 shows the TAP timing and test conditions.

Figure 2. TAP Timing and Test Conditions

[17]

Document Number: 001-05384 Rev. *F Page 16 of 28

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Identification Register Definitions

Instruction Field

Revision Number (31:29)

Cypress Device ID (28:12)

Cypress JEDEC ID (11:1)

ID Register Presence (0)

CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18

000 000 000 000 Version number.

11010010001000100 11010010001001100 11010010001010100 11010010001 100100 Defines the type of

00000110100 00000110100 00000110100 0000 0110100 Allows unique

1111Indicates the

Value

Description

SRAM.

identification of SRAM vendor.

presence of an ID register.

Scan Register Sizes

Instruction 3 Bypass 1 ID 32 Boundary Scan 109

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the input and output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register between TDI

RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

and TDO. Does not affect the SRAM operation.

operation.

Document Number: 001-05384 Rev. *F Page 17 of 28

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Boundary Scan Order

Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID

0 6R 28 10G 56 6A 84 1J 16P299G575B852J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 47N329F605C882K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M

9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H

Document Number: 001-05384 Rev. *F Page 18 of 28

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Power Up Sequence in QDR-II+ SRAM

QDR-II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock.

Power Up Sequence

■ Apply power with DOFF tied HIGH (All other inputs can be

HIGH or LOW)

❐ Apply V ❐ Apply V

■ Provide stable power and clock (K, K) for 2048 cycles to lock

the DLL.

before V

DD DDQ

before V

DDQ

or at the same time as V

REF

Figure 3. Power Up Waveforms

Unstable Clock > 2048 Stable Clock

Clock Start (Clock Starts after VDD/V

DLL Constraints

■ DLL uses K clock as its synchronizing input. The input must

have low phase jitter, which is specified as t

■ The DLL functions at frequencies down to 120 MHz.

■ If the input clock is unstable and the DLL is enabled, then the

KC Var

DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. T o avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency.

Start Normal Operation

is Stable)

DDQ

VDD/V

DDQ

DOFF

VDD/V

DDQ

Fix HIGH (tie to V

Stable (< + 0.1V DC per 50 ns)

)

DDQ

Document Number: 001-05384 Rev. *F Page 19 of 28

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Maximum Ratings

Notes

18.Power up: Assumes a linear ramp from 0V to V

(min) within 200 ms. During this time V

< V

and V

DDQ

< VDD.

19.Output are impedance controlled. IOH = −(V

DDQ

/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

20.Output are impedance controlled. I

= (V

DDQ

/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

21.V

REF

(min) = 0.68V or 0.46V

DDQ

, whichever is larger, V

REF

(max) = 0.95V or 0.54V

DDQ

, whichever is smaller.

22.The operation current is calculated with 50% read cycle and 50% write cycle.

Exceeding maximum ratings may impair the useful life of th e device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with Power Applied..–55°C to +125°C

Supply Voltage on VDD Relative to GND........–0.5V to +2.9V

Supply Voltage on V

DC Applied to Outputs in High-Z ........–0.5V to V

DC Input Voltage

Relative to GND.......–0.5V to +V

DDQ

[14]

..............................–0.5V to VDD + 0.3V

DDQ

+ 0.3V

Electrical Characteristics

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V

Latch-up Current ........................ ... .. ....................... >200 mA

Operating Range

Range

Temperature (TA) V

Commercial 0°C to +70°C 1.8 ± 0.1V 1.4V to Industrial –40°C to +85°C

Ambient

[18]

DDQ

[18]

DC Electrical Characteristics

Over the Operating Range

[15]

Parameter Description Test Conditions Min Typ Max Unit

DDQ

OH(LOW)

OL(LOW)

REF

[22]

Power Supply Voltage 1.7 1.8 1.9 V IO Supply Voltage 1.4 1.5 V Output HIGH Voltage Note 19 V Output LOW Voltage Note 20 V Output HIGH Voltage I

= −0.1 mA, Nominal Impedance V

Output LOW Voltage IOL = 0.1mA, Nominal Impedance V Input HIGH Voltage Input LOW Voltage Input Leakage Current GND ≤ VI ≤ V Output Leakage Current GND ≤ VI ≤ V Input Reference Voltage VDD Operating Supply V

[14]

DDQ

Output Disabled −2 2 μA

= 1/t

DDQ,

CYC

400 MHz x8 1400 mA

x9 1400

x18

[21]

Typical Value = 0.75V 0.68 0.75 0.95 V

= Max,

= 0 mA,

OUT

f = f

MAX

/2 – 0.12 V

DDQ

/2 – 0.12 V

DDQ

– 0.2 V

DDQ

+ 0.1 V

REF

–0.15 V

−2 2 μA

x36

/2 + 0.12 V

DDQ

/2 + 0.12 V

DDQ

0.2 V + 0.15 V

DDQ

– 0.1 V

REF

1400 1400

375 MHz x8 1300 mA

x9 1300

x18

1300

x36 1300

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Electrical Characteristics (continued)

DC Electrical Characteristics

Over the Operating Range

[15]

Parameter Description Test Conditions Min Typ Max Unit

[22]

VDD Operating Supply V

OUT

f = f

= Max,

= 0 mA,

= 1/t

MAX

CYC

333 MHz x8 1200 mA

x9 1200 x18 1200 x36

1200

300 MHz x8 1100 mA

x9 1100

SB1

Automatic Power down Current

Max VDD, Both Ports Deselected, VIN ≥ VIH or VIN ≤ VIL f = f Static

MAX

= 1/t

CYC,

Inputs

x18 x36

1100

400 MHz x8 550 mA

x9 550 x18 x36 550

1100

550

375 MHz x8 525 mA

x9 525 x18 525 x36

525

333 MHz x8 500 mA

x9 500 x18 x36

500 500

300 MHz x8 450 mA

x9 450 x18

450

x36 450

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AC Electrical Characteristics

1.25V

0.25V

R = 50Ω

5pF

INCLUDING

JIG AND

SCOPE

ALL INPUT PULSES

Device

= 50Ω

REF

= 0.75V

REF

= 0.75V

[23]

0.75V

Under Test

0.75V

Device Under Test

OUTPUT

0.75V

REF

OUTPUT

(a)

Slew Rate = 2 V/ns

RQ = 250

(b)

RQ = 250

Notes

23.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V

DDQ

= 1.5V, input pulse

levels of 0.25V to 1.25V, and output loading of the specified I

OL/IOH

and load capacitance shown in (a) of AC Test Loads and Waveforms.

Over the Operating Range

Parameter Description Test Conditions Min Typ Max Unit

Input HIGH Voltage V Input LOW Voltage –0.24 – V

[14]

+ 0.2 – V

REF

+ 0.24 V

DDQ

– 0.2 V

REF

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions Max Unit

Input Capacitance TA = 25°C, f = 1 MHz, VDD = 1.8V, V

CLK

Clock Input Capacitance 6 pF Output Capacitance 7pF

= 1.5V 5 pF

DDQ

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions

Thermal Resistance

(Junction to Ambient) Thermal Resistance

(Junction to Case)

Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51.

165 FBGA

Package

11.82 °C/W

2.33 °C/W

Unit

Figure 4. AC Test Loads and Waveforms

Document Number: 001-05384 Rev. *F Page 22 of 28

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Switching Characteristics

Notes

24.When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires th e input timings of the freque ncy range in which it is being operated and outputs data with the output timings of that fre quency range.

25.This part has a voltage regulator internally; t

POWER

is the time that the power is supplied above VDD minimum initially before a read or write operation can be initiated.

26.These parameters are extrapolated from the input timing parameters (t

KHKH

- 250ps, where 250ps is the internal jitter . An input jitter of 200ps(t

KCVAR

) is already included

in the t

KHKH

). These parameters are only guaranteed by design and are not tested in production.

27.t

CHZ

, t

CLZ

, are specified with a load capacitance of 5 pF as in part (b) of “AC T est Loa ds and Waveforms” on pag e 22. Transition is measured ± 100 mV from steady-state

voltage.

28.At any given voltage and temperature t

CHZ

is less than t

CLZ

and t

CHZ

less than tCO.

29.t

QVLD

spec is applicable for both rising and falling edges of QVLD signal.

30.Hold to >V

or <VIL.

Over the Operating Range

Parameter

POWER

CYC

KHKH

Consortium

Parameter

KHKH

KHKL

KLKH

KHKH

Setup Times

SCDDR

AVKH

IVKH

DVKH

Hold Times

HCDDRtKHIX

KHAX

KHIX

KHDX

Output Times

DOH

CCQO

CQOH

CQD

CQDOHtCQHQX

CQH

CQHCQHtCQHCQH

CHZ

CLZ

QVLD

CHQV

CHQX

CHCQV

CHCQX

CQHQV

CQHCQL

CHQZ

CHQX1

CQHQVLD

DLL Timing

KC Var

KC lock

KC ResettKC Reset

KC Var

KC lock

[23, 24]

VDD(Typical) to the First Access K Clock Cycle Time 2.50 8.40 2.66 8.40 3.0 8.40 3.3 8.40 ns

Input Clock (K/K) HIGH Input Clock (K/K) LOW K Clock Rise to K Clock Rise

(rising edge to rising edge)

Address Setup to K Clock Rise 0.4 – 0.4 – 0.4 – 0.4 – ns Control Setup to K Clock Rise (RPS, WPS) 0.4 – 0.4 – 0.4 – 0.4 – ns Double Data Rate Control Setup to Clock (K/K)

Rise (BWS D

Setup to Clock (K/K) Rise 0.28–0.28–0.28–0.28– ns

[X:0]

Address Hold after K Clock Rise 0.4 – 0.4 – 0.4 – 0.4 – ns Control Hold after K Clock Rise (RPS, WPS) 0.4 – 0.4 – 0.4 – 0.4 – ns Double Data Rate Control Hold after Clock (K/K)

Rise (BWS D

Hold after Clock (K/K) Rise

[X:0]

K/K Clock Rise to Data Valid Data Output Hold after Output K/K Clock Rise

(Active to Active) K/K Clock Rise to Echo Clock Valid 0.45–0.45–0.45–0.45ns Echo Clock Hold after K/K Clock Rise –0.45 – –0.45 – –0.45 – –0.45 – ns Echo Clock High to Data Valid 0.2 0.2 0.2 0.2 ns Echo Clock High to Data Invalid –0.2 – –0.2 – –0.2 – –0.2 – ns Output Clock (CQ/CQ) HIGH CQ Clock Rise to CQ Clock Rise

(rising edge to rising edge) Clock (K/K) Rise to High-Z

(Active to High-Z) Clock (K/K) Rise to Low-Z

Echo Clock High to QVLD Valid

Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 ns DLL Lock Time (K) 2048 – 2048 – 2048 – 2048 – cycles K Static to DLL Reset

Description

, BWS1, BWS2, BWS3)

[26]

[26, 27]

[30]

[25]

[29]

[26]

400 MHz 375 MHz 333 MHz 300 MHz

Min Max Min Max Min Max Min Max

Unit

1111ms

0.4 – 0.4 – 0.4 0.4 – t

CYC CYC

1.06 – 1.13 – 1.28 – 1.40 – ns

0.28 – 0.28 – 0.28 – 0.28 – ns

0.45–0.45–0.45–0.45ns

–0.45 – –0.45 – –0.45 – –0.45 – ns

0.81–0.88–1.03 1.15– ns

0.81 – 0.88 – 1.03 – 1.15 – ns

0.45–0.45–0.45–0.45ns

–0.45 – –0.45 – –0.45 – –0.45 – ns –0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20 ns

30–30–30–30–ns

Document Number: 001-05384 Rev. *F Page 23 of 28

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Switching Waveforms

CYC

KHKH

SA HA

SC HC

tSCt

A0 A1

D11

D10

D12

D13

D30

D31

D32 D33

WPS

RPS

NOPREAD

NOP

WRITE

READ

WRITE

23 4

567

CQOH

CCQO

CLZ

DOH

CQDOH

CQD

CHZ

CQOH

CCQO

QVLD

DON’T CARE UNDEFINED

(Read Latency = 2.5 Cycles)

Q00

Q01

Q20Q02 Q21

Q03

Q22 Q23

CQH

CQHCQH

Notes

31.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.

32.Outputs are disabled (High-Z) one clock cycle after a NOP.

33.In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwar ded immediately as read results. This note applies to the whole diagram.

Read/Write/Deselect Sequence

[31, 32, 33]

Figure 5. Waveform for 2.5 Cycle Read Latency

Document Number: 001-05384 Rev. *F Page 24 of 28

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Ordering Information

Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed

(MHz)

400 CY7C1561V18-400BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1576V18-400BZC CY7C1563V18-400BZC CY7C1565V18-400BZC CY7C1561V18-400BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1576V18-400BZXC CY7C1563V18-400BZXC CY7C1565V18-400BZXC CY7C1561V18-400BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial CY7C1576V18-400BZI CY7C1563V18-400BZI CY7C1565V18-400BZI CY7C1561V18-400BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1576V18-400BZXI CY7C1563V18-400BZXI CY7C1565V18-400BZXI

375 CY7C1561V18-375BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1576V18-375BZC CY7C1563V18-375BZC CY7C1565V18-375BZC CY7C1561V18-375BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1576V18-375BZXC CY7C1563V18-375BZXC CY7C1565V18-375BZXC CY7C1561V18-375BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial CY7C1576V18-375BZI CY7C1563V18-375BZI CY7C1565V18-375BZI CY7C1561V18-375BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1576V18-375BZXI CY7C1563V18-375BZXI CY7C1565V18-375BZXI

Ordering Code

Package Diagram

Package Type

Operating

Range

Document Number: 001-05384 Rev. *F Page 25 of 28

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Ordering Information (continued)

Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed

(MHz)

333 CY7C1561V18-333BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1576V18-333BZC CY7C1563V18-333BZC CY7C1565V18-333BZC CY7C1561V18-333BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1576V18-333BZXC CY7C1563V18-333BZXC CY7C1565V18-333BZXC CY7C1561V18-333BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial CY7C1576V18-333BZI CY7C1563V18-333BZI CY7C1565V18-333BZI CY7C1561V18-333BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1576V18-333BZXI CY7C1563V18-333BZXI CY7C1565V18-333BZXI

300 CY7C1561V18-300BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1576V18-300BZC CY7C1563V18-300BZC CY7C1565V18-300BZC CY7C1561V18-300BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1576V18-300BZXC CY7C1563V18-300BZXC CY7C1565V18-300BZXC CY7C1561V18-300BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial CY7C1576V18-300BZI CY7C1563V18-300BZI CY7C1565V18-300BZI CY7C1561V18-300BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1576V18-300BZXI CY7C1563V18-300BZXI CY7C1565V18-300BZXI

Ordering Code

Package Diagram

Package Type

Operating

Range

Document Number: 001-05384 Rev. *F Page 26 of 28

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Package Diagram



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

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*%$%#2%&%2%.#%-/$%3)'.#

0!#+!'%#/$%""!$

51-85195-*A

Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-85195

Document Number: 001-05384 Rev. *F Page 27 of 28

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Document History Page

Document Title: CY7C1561V18/CY7C1576V18/CY7C1563V18/CY7C1565V18, 72-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Document Number: 001-05384

REV. ECN NO.

ISSUE

DATE

** 402911 See ECN VEE New Data Sheet

*A 425251 See ECN VEE Updated the switching waveform

*B 437000 See ECN IGS ECN for Show on web *C 461934 See ECN NXR Moved the Selection Guide table from page# 3 to page# 1.

*D 497567 See ECN NXR Changed the V

*E 1351243 See ECN VKN/FSU Converted from preliminary to final

*F 2181046 See ECN VKN/AESA Added footnote# 22 related to I

© Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life sa vin g, critical control or safety applications, unless pursuant to an exp re ss w ritten agreement with Cypress. Furthermore, Cypress does not authori ze i ts products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States co pyright la ws and inte rnatio na l tre aty prov isi ons. Cyp ress he reby g rant s to lice nsee a p erson al, no n-ex clusi ve, non-tra nsferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpo se of creating custom sof tware and or firm ware in support of licen see product to be use d only in conjunction with a Cypress integrated circuit as specified in th e applicable agreement. Any reproductio n, modification, translation, co mpilation, o r representati on of this Sour ce Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the ap plicati on or u se o f any pr oduct o r circui t descri bed h erein. Cypr ess does not aut horize it s product s for use a s critical compo nent s in life-support systems whe re a malfunction or failure may reasonab ly be expected to resu lt in significant injury t o the user. The inclusion of Cypress’ prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

ORIG. OF CHANGE

DESCRIPTION OF CHANGE

Corrected the typos in DC parameters Updated the DLL section Added additional notes in the AC parameter section Updated the Power up sequence Added additional parameters in the AC timing

Modified Application Diagram. Changed t from 10 ns to 5 ns and changed t Characteristics table

and t

from 40 ns to 20 ns, changed t

TDOV

, t

TDIS

, tCS, t

from 20 ns to 10 ns in TAP AC Switching

TMSS

TMSH

, t

TDIH

, t

Modified Power Up waveform. Included Maximum ratings for Supply Voltage on V Changed the Maximum Ratings for DC Input Voltage from V Changed the Pin Definition of I page#18.

operating voltage to 1.4V to VDD in the Features section, in

Operating Range table and in the DC Electrical Characteristics table

DDQ

from Input Load current to Input Leakage current on

Relative to GND.

DDQ

to VDD.

Added foot note in page# 1 Changed the Maximum rating of Ambient T emperature with Power Applied from –10°C to +85°C to –55°C to +125°C Changed V table and in the note below the table

(Max) spec from 0.85V to 0.95V in the DC Electrical Characteristics

REF

Updated footnote #21 to specify Overshoot and Undershoot Spec Updated I Updated Θ Removed x9 part and its related information

and ISB values

and Θ

values

Updated footnote #25

Added x8 and x9 parts Changed t Updated footnote# 23

max spec to 8.4 ns for all speed bins

CYC

Updated Ordering Information table

Document Number: 001-05384 Rev. *F Revised March 6, 2008 Page 28 of 28

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.

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