Cypress Semiconductor CY7C1480V25, CY7C1482V25, CY7C1486V25 Specification Sheet

CY7C1480V25
CY7C1482V25
CY7C1486V25

72-Mbit (2M x 36/4M x 18/1M x 72)

Pipelined Sync SRAM

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200, and 167 MHz

• Registered inputs and outputs for pipelined operation

• 2.5V core power supply

• 2.5V/1.8V IO operation

• Fast clock-to-output time

— 3.0 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User selectable burst counter supporting Intel
Pentium

• Separate processor and controller address strobes

• Synchronous self timed writes

• Asynchronous output enable

• Single cycle chip deselect

• CY7C1480V25, CY7C1482V25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1486V25
available in Pb-free and non-Pb-free 209-ball FBGA
package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode option

®

interleaved or linear burst sequences

®

Functional Description

The CY7C1480V25/CY7C1482V25/CY7C1486V25 SRAM
integrates 2M x 36/4M x 18/1M × 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

), depth-expansion Chip Enables (CE2 and CE3), Burst

1

Control inputs (ADSC
and BWE
include the Output Enable (OE

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC
addresses can be internally generated as controlled by the
Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. This part supports Byte
Write operations (see “Pin Definitions” on page 7 and “Truth

Table” on page 10 for further details). Write cycles can be one

to two or four bytes wide, as controlled by the byte write control
inputs. When it is active LOW, GW
written.

The CY7C1480V25/CY7C1482V25/CY7C1486V25 operates
from a +2.5V core power supply while all outputs may operate
with either a +2.5 or +1.8V supply. All inputs and outputs are
JEDEC-standard JESD8-5-compatible.

), and Global Write (GW). Asynchronous inputs

, ADSP, and ADV), Write Enables (BWX,

[1]

) and the ZZ pin.

) or

) is active. Subsequent burst

causes all bytes to be

Selection Guide

250 MHz 200 MHz 167 MHz Unit

Maximum Access Time 3.0 3.0 3.4 ns

Maximum Operating Current 450 450 400 mA

Maximum CMOS Standby Current 120 120 120 mA

Note

1. For best practices recommendations, refer to the Cypress application note System Design Guidelines at www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05282 Rev. *H Revised April 23, 2007

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Logic Block Diagram – CY7C1480V25 (2M x 36)

CY7C1480V25
CY7C1482V25
CY7C1486V25

A0, A1, A

MODE

ADV

CLK

ADSC

ADSP

BW

BW

BW

BW

BWE

GW

CE
CE
CE

ADDRESS
REGISTER

D,

D

DQP

DQ

D

C

B

A

1

2

3

OE

ZZ

BYTE

WRITE REGISTER

C,DQP

DQ

BYTE

WRITE REGISTER

B,DQP

DQ

BYTE

WRITE REGISTER

DQ A,DQP

BYTE

WRITE REGISTER

SLEEP

CONTROL

C

B

A

ENABLE

REGISTER

2

BURST

COUNTER

AND

CLR

LOGIC

PIPELINED

ENABLE

A

[1:0]

Q1

Q0

D ,DQP

DQ

D

BYTE

WRITE DRIVER

C,DQP

C

DQ

BYTE

WRITE DRIVER

B,DQP

B

DQ

BYTE

WRITE DRIVER

A,DQP

A

DQ

BYTE

WRITE DRIVER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQs
DQP
DQP
DQP
DQP

A

B

C

D

Logic Block Diagram – CY7C1482V25 (4M x 18)

A0, A1, A

MODE

ADV

CLK

ADSC

ADSP

BW

BW

BWE

GW

CE

CE2
CE3

OE

B

A

1

ZZ

ADDRESS
REGISTER

DQB,DQP

B

WRITE REGISTER

DQA,DQP

A

WRITE REGISTER

ENABLE

REGISTER

SLEEP

CONTROL

2

BURST

COUNTER AND

LOGIC

CLR

PIPELINED

ENABLE

A[1:0]

Q1

Q0

WRITE DRIVER

WRITE DRIVER

DQB,DQP

DQA,DQP

B

MEMORY

A

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

DQs
DQP
DQP

A

B

INPUT

REGISTERS

Document #: 38-05282 Rev. *H Page 2 of 32

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Logic Block Diagram – CY7C1486V25 (1M x 72)

CY7C1480V25
CY7C1482V25
CY7C1486V25

A0, A1,A

MODE

ADV

ADSC

ADSP

BW

BW

BW

BW

BW

BW

BW

BW

BWE

ADDRESS
REGISTER

CLK

DQH, DQP

H

G

F

E

D

C

B

A

GW
CE1
CE2
CE3

OE

WRITE DRIVER

DQF, DQP

WRITE DRIVER

DQF, DQP

WRITE DRIVER

DQE, DQP

WRITE DRIVER

DQD, DQP

WRITE DRIVER

DQC, DQP

WRITE DRIVER

DQB, DQP

WRITE DRIVER

DQA, DQP

WRITE DRIVER

ENABLE

REGISTER

H

F

F

E

D

C

B

A

COUNTER

CLR

PIPELINED

ENABLE

BINARY

A[1:0]

Q1

Q0

DQH, DQP

H

WRITE DRIVER

DQG, DQP

G

WRITE DRIVER

DQF, DQP

F

WRITE DRIVER

E

DQE, DQP

BYTE

“a”

WRITE DRIVER

WRITE DRIVER

DQD, DQP

WRITE DRIVER

DQC, DQP

WRITE DRIVER

DQB, DQP

WRITE DRIVER

DQA, DQP

WRITE DRIVER

MEMORY

ARRAY

D

C

SENSE

B

A

AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQs
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP

A

B

C

D

E

F

G

H

ZZ

SLEEP

CONTROL

Document #: 38-05282 Rev. *H Page 3 of 32

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Pin Configurations

100-Pin TQFP Pinout

CY7C1480V25
CY7C1482V25
CY7C1486V25

DQP
DQC
DQc

V

DDQ

V

SSQ

DQC
DQC
DQC
DQC

V

SSQ

V

DDQ

DQC
DQC

NC

V

NC

V
DQD
DQD

V

DDQ

V

SSQ

DQD
DQD
DQD
DQD

V

SSQ

V

DDQ

DQD
DQD

DQPD

1CE2

A

A

BWD

BWC

CE

100999897969594939291908988878685848382

C

1
2
3
4
5
6
7
8
9
10
11
12
13
14

DD

15
16

SS

17
18
19
20
21
22
23
24
25
26
27
28
29
30

BWB

CY7C1480V25

31323334353637383940414243444546474849

AAA

1A0

A

A

MODE

SS

BWA

CE3VDDV

(2M x 36)

SS

A

A

DD

V

V

CLKGWBWEOEADSC

A

A

ADSP

AAAAA

ADV

A

A

81

DQPB

80

DQB

79

DQB

78

V

77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DDQ

V

SSQ

DQB
DQB
DQB
DQB
V

SSQ

V

DDQ

DQB
DQB
V

SS

NC
V

DD

ZZ
DQ
DQA
V

DDQ

V

SSQ

DQA
DQA
DQA
DQA
V

SSQ

V

DDQ

DQA
DQA
DQPA

A

NC
NC
NC

V

DDQ

V

SSQ

NC

NC
DQ
DQB

V

SSQ

V

DDQ

DQB
DQB

NC

V

NC

V
DQB
DQB

V

DDQ

V

SSQ

DQB
DQB

DQPB

NC

V

SSQ

V

DDQ

NC
NC
NC

B

DD

SS

50

A

A

1CE2

A

A

NCNCBWBBWA

CE

100999897969594939291908988878685848382

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CY7C1482V25

SS

CE3VDDV

(4M x 18)

CLKGWBWEOEADSC

ADSP

31323334353637383940414243444546474849

MODE

AAA

1A0

A

A

A

A

A

A

DD

V

AAAAA

SS

V

ADV

A

A

81

A

80

NC

79

NC

78

V

77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DDQ

V

SSQ

NC
DQP
DQA
DQA
V

SSQ

V

DDQ

DQA
DQA
V

SS

NC
V

DD

ZZ
DQ
DQA
V

DDQ

V

SSQ

DQA
DQA
NC
NC
V

SSQ

V

DDQ

NC
NC
NC

A

A

50

A

A

Document #: 38-05282 Rev. *H Page 4 of 32

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Pin Configurations (continued)

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1480V25 (2M x 36)

CY7C1480V25
CY7C1482V25
CY7C1486V25

A

B
C
D

E
F
G

H

J
K
L

M

N
P

R

A

B
C
D

E
F

G
H

J

K

L

M
N

P

R

234 5671

NC/288M

NC/144M

DQP

C

DQ

C

DQ

C

DQ

C

DQ

C

NC

DQ

D

DQ

D

DQ

D

DQ

D

DQP

D

NC

MODE

A

A

NC

DQ

DQ

DQ

DQ

NC

DQ

DQ

DQ

DQ

NC

A

A

CE

CE2

V

DDQ

V

C

C

C

C

V

V

V

DDQ

DDQ

DDQ

DDQ

NC

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

D

D

D

D

A

A

BW

1

BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

BW

BW

V

V

V

V

V
V
V

V

V

V

B

A

SS

SS

SS

SS

SS

SS

SS

SS

SS

SS

C

D

NC

TDI

TMS

CY7C1482V25 (4M x 18)

234 5671

NC

DQ

DQ

DQ

DQ

NC

NC

NC

NC

NC

NC

A

A

CE

CE2

V

DDQ

V

B

B

B

B

V

V

V

DDQ

DDQ

DDQ

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

A

A

BW

1

B

NC BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

NC/288M

NC/144M

NC

NC

NC V

NC

NC
NC

DQ

B

DQ

B

DQ

B

DQ

B

DQP

B

NC

MODE

NC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

A

891011

CE

CLK

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A

A1

A0

BWE

3

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCK

ADSC

OE ADSP

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

ADV

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

A

A

NC/1G DQP

DQ

B

DQ

B

DQ

B

DQ

B

NC

DQ

A

DQ

A

DQ

A

DQ

A

NC

A

NC

NC/576M

B

DQ

B

DQ

B

DQ

B

DQ

B

ZZ

DQ

A

DQ

A

DQ

A

DQ

A

DQP

A

A

AA

891011

CE

CLK

V

SS

V

SS

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A

A1

BWE

3

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCKA0

ADSC

OE ADSP

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

DD

V

DD

V

SS

A

A

ADV

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

A

A

NC/1G DQP

NC

NC

NC

NC
NC

DQ

A

DQ

A

DQ

A

DQ

A

NC

A

A

NC/576M

DQ

A

DQ

A

DQ

A

DQ

A

ZZ

NCV

NC

NC

NC

NC

A

AA

A

Document #: 38-05282 Rev. *H Page 5 of 32

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Pin Configurations (continued)

123456789 1110

DQ

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

DQ

DQ

DQ

DQP

DQ

DQ

DQ

DQ

NC

DQ

DQ

DQ

DQ

DQP

DQ

DQ

DQ

DQ

DQ

G

G

G

G

C

C

C

C

G

DQ

G

DQ

G

DQ

G

DQP

G

DQ

DQ

DQ

DQ

C

C

C

C

C

NC

DQ

H

H

H

H

D

D

D

D

D

DQ

DQ

DQ

DQP

DQ

DQ

DQ

DQ

H

H

H

H

H

D

D

D

D

209-Ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1486V25 (1M × 72)

A

BWS

BWS

V

SS

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

CLK

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

V

SS

A

AA

TMS

CE

BWS

C

BWS

H

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

2

G

D

ADSP

NC/288M

NC/144M

NC/1G

V

V

V

V

V

NC MODE

A

TDI TDO TCK

ADSC

BWE

CE

1

OE

DD

DD

SS

DD

SS

DD

V

NC

NC

NC

NC

V

NC

NC

NC

ZZ

V

DD

SS

DD

DD

SS

DD

SS

V

SS

V

V

V

V

V

NC

AA A

A

AA

AA

A1

A0

ADV A

A

NC/576M

GW

V

DD

V

SS

V

DD

V

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

NC

A

SS

CE

BWS

BWS

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

NC

AA

3

B

E

BWS

BWS

V

SS

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

V

SS

CY7C1480V25
CY7C1482V25
CY7C1486V25

DQ

DQ

F

DQ

A

DQ

DQP

DQ

DQ

DQ

DQ

NC

DQ

DQ

DQ

DQ

DQP

DQ

DQ

DQ

DQ

DQ

B

B

B

B

F

F

F

F

F

DQ

DQ

DQ

DQP

DQ

DQ

DQ

DQ

B

B

B

B

NC

DQ

A

DQ

A

DQ

A

DQ

A

DQP

A

DQ

E

DQ

E

DQ

E

DQ

E

B

F

F

F

F

A

A

A

A

E

E

E

E

E

Document #: 38-05282 Rev. *H Page 6 of 32

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Pin Definitions

Pin Name I/O Description

, A1, A Input-

A

0

BW

, BWB, BWC,

A

, BWE, BWF,

BW

D

BW

, BW

G

GW

H

Synchronous

Input-

Synchronous

Input-

Synchronous

BWE

Input-

Synchronous

CLK Input-

Clock

CE

CE

CE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

OE Input-

Asynchronous

ADV Input-

Synchronous

ADSP Input-

Synchronous

ADSC

Input-

Synchronous

ZZ Input-

Asynchronous

DQs, DQPs

I/O-

Synchronous

V

DD

V

SS

[2]

V

SSQ

V

DDQ

Note

2. Applicable for TQFP package. For BGA package V

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

I/O Ground Ground for the I/O circuitry.

I/O Power Supply Power supply for the I/O circuitry.

Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP

or ADSC is active LOW, and CE1, CE2, and CE3 are sampled

active. A1: A0 are fed to the two-bit counter.

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are written, regardless of the values on BW
BWE

).

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.

Clock Input. Captures all synchronous inputs to the device. Also increments the burst
counter when ADV

is asserted LOW during a burst operation.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
HIGH. CE

is sampled only when a new external address is loaded.

1

and CE3 to select/deselect the device. ADSP is ignored if CE1 is

2

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
new external address is loaded.

and CE3 to select/deselect the device. CE2 is sampled only when a

1

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
new external address is loaded.

and CE2 to select/deselect the device. CE3 is sampled only when a

1

Output Enable, asynchronous input, active LOW. Controls the direction of the IO pins.
When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when
emerging from a deselected state.

Advance Input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP

is recognized. ASDP is ignored when CE1 is deasserted HIGH.

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP
asserted, only ADSP

is recognized.

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull down.

Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
the read cycle. The direction of the pins is controlled by OE
the pins behave as outputs. When HIGH, DQs and DQP

serves as ground for the core and the IO circuitry.

SS

CY7C1480V25
CY7C1482V25
CY7C1486V25

and

X

and ADSC are both

. When OE is asserted LOW,

are placed in a tri-state condition.

X

Document #: 38-05282 Rev. *H Page 7 of 32

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CY7C1480V25
CY7C1482V25
CY7C1486V25

Pin Definitions (continued)

Pin Name I/O Description

MODE Input Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V

or left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode pin has an internal pull up.

TDO JTAG Serial

Output

Synchronous

TDI JTAG Serial Input

Synchronous

TMS JTAG Serial Input

Synchronous

TCK JTAG Clock Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be

NC - No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not used, this pin must be disconnected. This pin is not available on TQFP
packages.

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be disconnected or connected to V
TQFP packages.

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be disconnected or connected to V
TQFP packages.

connected to V

expansion pins and are not internally connected to the die.

. This pin is not available on TQFP packages.

SS

. This pin is not available on

DD

. This pin is not available on

DD

DD

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(250 MHz device).

The CY7C1480V25/CY7C1482V25/CY7C1486V25 supports
secondary cache in systems using either a linear or inter­leaved burst sequence. The interleaved burst order supports
Pentium and i486™ processors. The linear burst sequence is
suited for processors that use a linear burst sequence. The
burst order is user selectable, and is determined by sampling
the MODE input. Accesses can be initiated with either the
Processor Address Strobe (ADSP
Strobe (ADSC
sequence is controlled by the ADV
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.

Byte write operations are qualified with the Byte Write Enable
(BWE

) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
is HIGH.

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP

, CE2, CE3 are all asserted active, and (3) the write signals

CE

1

(GW

, BWE) are all deasserted HIGH. ADSP is ignored if CE
is HIGH. The address presented to the address inputs (A) is
stored into the address advancement logic and the Address
Register while being presented to the memory array. The

). Address advancement through the burst

) overrides all byte write inputs and writes data to

) or the Controller Address

input. A two-bit on-chip

, CE2, CE3) and an

1

) provide easy bank

or ADSC is asserted LOW, (2)

) is 3.0 ns

CO

is ignored if CE

corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.0 ns (250-MHz device) if OE
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported. After the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output will tri-state immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
(2) CE

, CE2, CE3 are all asserted active. The address

1

presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The write signals (GW
ADV

inputs are ignored during this first cycle.

ADSP

-triggered write accesses require two clock cycles to
complete. If GW
data presented to the DQs inputs is written into the corre­sponding address location in the memory array. If GW
then the write operation is controlled by the BWE
signals.

The CY7C1480V25/CY7C1482V25/CY7C1486V25 provides
Byte Write capability that is described in the “Truth Table for

1

Read/Write” on page 11. Asserting the Byte Write Enable input

(BWE

) with the selected Byte Write (BWX) input, will selec­tively write to only the desired bytes. Bytes not selected during
a byte write operation remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.

Because CY7C1480V25/CY7C1482V25/CY7C1486V25 is a

1

common IO device, the Output Enable (OE
deasserted HIGH before presenting data to the DQs inputs.
Doing so tri-states the output drivers. As a safety precaution,

is asserted LOW on the second clock rise, the

is asserted LOW, and

, BWE, and BWX) and

is active

is HIGH,

and BW

) must be

X

Document #: 38-05282 Rev. *H Page 8 of 32

[+] Feedback

CY7C1480V25
CY7C1482V25
CY7C1486V25

DQs are automatically tri-stated whenever a write cycle is
detected, regardless of the state of OE

.

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi­tions are satisfied: (1) ADSC
deasserted HIGH, (3) CE
and (4) the appropriate combination of the write inputs (GW
BWE

, and BWX) are asserted active to conduct a write to the

desired byte(s). ADSC

is asserted LOW, (2) ADSP is

, CE2, CE3 are all asserted active,

1

-triggered write accesses need a single
clock cycle to complete. The address presented to A is loaded
into the address register and the address advancement logic
while being delivered to the memory array. The ADV

input is
ignored during this cycle. If a global write is conducted, the
data presented to the DQs is written into the corresponding
address location in the memory core. If a byte write is
conducted, only the selected bytes are written. Bytes not
selected during a byte write operation remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations.

Because CY7C1480V25/CY7C1482V25/CY7C1486V25 is a
common IO device, the Output Enable (OE

) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so tri-states the output drivers. As a safety precaution,
DQs are automatically tri-stated whenever a write cycle is
detected, regardless of the state of OE

.

Burst Sequences

The CY7C1480V25/CY7C1482V25/CY7C1486V25 provides
a two-bit wraparound counter, fed by A1: A0, that implements
either an interleaved or linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel
Pentium applications. The linear burst sequence is designed
to support processors that follow a linear burst sequence. The
burst sequence is user selectable through the MODE input.

Asserting ADV

LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
Read and Write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation

,

guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.

, CE2, CE3, ADSP, and ADSC must

1

after the ZZ input

ZZREC

Interleaved Burst Address Table
(MODE = Floating or V

First

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Second

Address

A1: A0

DD

)

Third

Address

A1: A0

Linear Burst Address Table
(MODE = GND)

First

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

Fourth

Address

A1: A0

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Document #: 38-05282 Rev. *H Page 9 of 32

Sleep Mode Standby Current ZZ > VDD – 0.2V 120 mA

Device Operation to ZZ ZZ > VDD – 0.2V 2t

ZZ Recovery Time ZZ < 0.2V 2t

ZZ Active to Sleep Current This parameter is sampled 2t

ZZ Inactive to Exit Sleep Current This parameter is sampled 0 ns

CYC

CYC

CYC

ns

ns

ns

[+] Feedback

CY7C1480V25
CY7C1482V25
CY7C1486V25

Truth Table

The truth table for CY7C1480V25, CY7C1482V25, and CY7C1486V25 follows.

Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State

Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State

Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State

Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State

Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State

Sleep Mode, Power Down None X X X H X X X X X X Tri-State

Read Cycle, Begin Burst External L H L L L X X X L L-H Q

Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State

Write Cycle, Begin Burst External L H L L H L X L X L-H D

Read Cycle, Begin Burst External L H L L H L X H L L-H Q

Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State

Read Cycle, Continue Burst Next X X X L H H L H L L-H Q

Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State

Read Cycle, Continue Burst Next H X X L X H L H L L-H Q

Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State

Write Cycle, Continue Burst Next X X X L H H L L X L-H D

Write Cycle, Continue Burst Next H X X L X H L L X L-H D

Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q

Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State

Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q

Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State

Write Cycle, Suspend Burst Current X X X L H H H L X L-H D

Write Cycle, Suspend Burst Current H X X L X H H L X L-H D

[3, 4, 5, 6, 7]

Notes

3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

4. WRITE

5. The DQ pins are controlled by the current cycle and the OE

6. The SRAM always initiates a read cycle when ADSP

7. OE

= L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.

after the ADSP
don't care for the remainder of the write cycle

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is

inactive or when the device is deselected, and all data bits behave as output when OE

or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to enable the outputs to tri-state. OE is a

Document #: 38-05282 Rev. *H Page 10 of 32

signal. OE is asynchronous and is not sampled with the clock.

is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks

is active (LOW).

[+] Feedback

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CY7C1482V25
CY7C1486V25

Truth Table for Read/Write

The read/write truth table for the CY7C1480V25 follows.

Function GW BWE BW

Read HHXXXX

Read HLHHHH

Write Byte A – (DQ

Write Byte B – (DQ

and DQPA) HL HHHL

A

and DQPB)HLHHLH

B

Write Bytes B, A H L H H L L

Write Byte C – (DQ

and DQPC) HLHLHH

C

Write Bytes C, A H L H L H L

Write Bytes C, B H L H L L H

Write Bytes C, B, A H L H L L L

Write Byte D – (DQ

and DQPD) HL LHHH

D

Write Bytes D, A H L L H H L

Write Bytes D, B H L L H L H

Write Bytes D, B, A H L L H L L

Write Bytes D, C H L L L H H

Write Bytes D, C, A H L L L H L

Write Bytes D, C, B HLLLLH

Write All Bytes HLLLLL

Write All Bytes LXXXXX

[5]

D

BW

C

BW

B

BW

A

Truth Table for Read/Write

The read/write truth table for the CY7C1482V25 follows.

Function

Read H H X X

Read H L H H

Write Byte A – (DQ

Write Byte B – (DQ

and DQPA)HLHL

A

and DQPB)HLLH

B

Write Bytes B, A H L L L

Write All Bytes H L L L

Write All Bytes L X X X

[5]

GW

BWE BW

B

BW

A

Truth Table for Read/Write

The read/write truth table for the CY7C1486V25 follows.

Function GW BWE BW

Read HHX

Read H L All BW

Write Byte x – (DQ

x and DQPx)HLL

Write All Bytes H L All BW

Write All Bytes L X X

[8]

X

= H

= L

Note

x represents any byte write signal BW[0..7]. To enable any byte write BWx, a Logic LOW signal must be applied at clock rise. Any number of byte writes can

8. BW
be enabled at the same time for any given write.

Document #: 38-05282 Rev. *H Page 11 of 32

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CY7C1482V25
CY7C1486V25

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1480V25/CY7C1482V25/CY7C1486V25 incorpo­rates a serial boundary scan test access port (TAP). This port
operates in accordance with IEEE Standard 1149.1-1990 but
does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5V or 1.8V I/O logic levels.

The CY7C1480V25/CY7C1482V25/CY7C1486V25 contains
a TAP controller, instruction register, boundary scan register,
bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V

) to prevent device clocking. TDI and TMS are internally

SS

pulled up and may be unconnected. They may alternatively be
connected to V
unconnected. At power up, the device comes up in a reset

through a pull up resistor. TDO must be left

DD

state, which does not interfere with the operation of the device.

TAP Controller State Diagram

TEST-LOGIC

1

RESET

0

0

RUN-TEST/

IDLE

1

SELE CT

DR-SCAN

1 1

CAPTU RE-DR

SHIFT -DR

EXIT1-DR

PAU SE-DR

0 0

EXIT2-DR

UPDATE-DR

1 0

1

0

0

0 0

1

1 1

0 0

0

1

1

IR-SCAN

CAPTU RE-IR

SHIFT -IR

EXIT1-IR

PAU SE-IR

EXIT2-IR

UPDATE-IR

1

The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.

SELE CT

0

0

1

1

1

1

0

0

Test Mode Select (TMS)

The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. You can leave this ball
unconnected if the TAP is not used. The ball is pulled up inter­nally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball serially inputs information into the registers and
can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction
that is loaded into the TAP instruction register. For information
on loading the instruction register, see the TAP Controller

State Diagram. TDI is internally pulled up and can be uncon-

nected if the TAP is unused in an application. TDI is connected
to the most significant bit (MSB) of any register. (See TAP

Controller Block Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See TAP Controller State Diagram.)

TAP Controller Block Diagram

0

Bypass Register

012

TDI TDO

TCK

TMS

Sele ction

Circuitry

Instruction Register

Identication Register

Boundary Scan Register

TAP CONTROLLER

Performing a TAP Reset

Perform a RESET by forcing TMS HIGH (V
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating.

At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and
enable data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.

Sele ction

Circuitry

012293031 ...

012..x ...

) for five rising

DD

Document #: 38-05282 Rev. *H Page 12 of 32

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CY7C1482V25
CY7C1486V25

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the “TAP Controller Block

Diagram” on page 12. At power up, the instruction register is

loaded with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset state,
as described in the previous section.

When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
enable fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This enables data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V

) when the BYPASS instruction is executed.

SS

Boundary Scan Register

The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The x36 configuration has a
73-bit-long register, and the x18 configuration has a
54-bit-long register.

The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller moves to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD, and SAMPLE Z instructions can be used
to capture the contents of the IO ring.

The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in “Identification Register Defini-

tions” on page 15.

TAP Instruction Set

Overview

Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Identification

Codes” on page 16. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions
are described in detail below.

The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.

The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the IO
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of

SAMPLE/PRELOAD; rather, it performs a capture of the IO
ring when these instructions are executed.

Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction after it is shifted in, the TAP
controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction that is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.

When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and
enables the IDCODE to be shifted out of the device when the
TAP controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register
at power up or whenever the TAP controller is in a test logic
reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.

When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.

Be aware that the TAP controller clock can only operate at a
frequency up to 10 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that may be captured.
Repeatable results may not be possible.

To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (t

plus tCH).

CS

Document #: 38-05282 Rev. *H Page 13 of 32

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CY7C1480V25

T

CY7C1482V25
CY7C1486V25

The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.

Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.

TAP Ti m i n g

123456

Test Clock

(TCK)

est Mode Select

(TMS)

Test Data-In

(TDI)

Test Data-Out

(TDO)

t

TMSS

t

TDIS

t

t

TMSH

t

TDIH

TH

BYPASS

When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

t

t

TL

CYC

t

TDOX

t

TDOV

DON’T CARE UNDEFINED

TAP AC Switching Characteristics Over the Operating Range

[9, 10]

Parameter Description Min Max Unit

Clock

t

TCYC

t

TF

t

TH

t

TL

TCK Clock Cycle Time 50 ns

TCK Clock Frequency 20 MHz

TCK Clock HIGH time 20 ns

TCK Clock LOW time 20 ns

Output Times

t

TDOV

t

TDOX

TCK Clock LOW to TDO Valid 10 ns

TCK Clock LOW to TDO Invalid 0 ns

Setup Times

t

TMSS

t

TDIS

t

CS

TMS Setup to TCK Clock Rise 5 ns

TDI Setup to TCK Clock Rise 5 ns

Capture Setup to TCK Rise 5 ns

Hold Times

t

TMSH

t

TDIH

t

CH

Notes

9. t

CS

10. Test conditions are specified using the load in TAP AC Test Conditions. t

TMS Hold after TCK Clock Rise 5 ns

TDI Hold after Clock Rise 5 ns

Capture Hold after Clock Rise 5 ns

and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

R/tF

= 1 ns.

Document #: 38-05282 Rev. *H Page 14 of 32

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CY7C1480V25
CY7C1482V25
CY7C1486V25

2.5V TAP AC Test Conditions

Input pulse levels ................................................ VSS to 2.5V

Input rise and fall time..................................................... 1 ns

Input timing reference levels .........................................1.25V

Output reference levels.................................................1.25V

Test load termination supply voltage.............................1.25V

2.5V TAP AC Output Load Equivalent

1.25V

1.8V TAP AC Test Conditions

Input pulse levels..................................... 0.2V to V

Input rise and fall time .....................................................1 ns

Input timing reference levels........................................... 0.9V

Output reference levels .................................................. 0.9V

Test load termination supply voltage .............................. 0.9V

1.8V TAP AC Output Load Equivalent

0.9V

50Ω

TDO

Z = 50Ω

O

20pF

TDO

Z = 50Ω

O

20pF

TAP DC Electrical Characteristics And Operating Conditions

DDQ

[11]

= 2.5V 1.7 V

DDQ

= 2.5V 2.1 V

DDQ

= 1.8V 1.6 V

V

DDQ

= 2.5V 0.4 V

DDQ

= 2.5V 0.2 V

DDQ

= 1.8V 0.2 V

V

DDQ

= 2.5V 1.7 VDD + 0.3 V

DDQ

= 1.8V 1.26 VDD + 0.3 V

V

DDQ

= 2.5V –0.3 0.7 V

DDQ

= 1.8V –0.3 0.36 V

V

DDQ

–5 5 µA

(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)

Parameter Description Test Conditions Min Max Unit

V

V

V

V

V

V

I

X

OH1

OH2

OL1

OL2

IH

IL

Output HIGH Voltage I

Output HIGH Voltage I

Output LOW Voltage IOL = 1.0 mA V

Output LOW Voltage IOL = 100 µAV

Input HIGH Voltage V

Input LOW Voltage V

Input Load Current GND ≤ VI ≤ V

= –1.0 mA V

OH

= –100 µAV

OH

50Ω

DDQ

– 0.2

Identification Register Definitions

Instruction Field

Revision Number (31:29) 000 000 000 Describes the version number

Device Depth (28:24) 01011 01011 01011 Reserved for internal use

Architecture/Memory
Type(23:18)

Bus Width/Density(17:12) 100100 010100 110100 Defines width and density

Cypress JEDEC ID Code
(11:1)

ID Register Presence
Indicator (0)

Note

11. All voltages referenced to V

Document #: 38-05282 Rev. *H Page 15 of 32

CY7C1480V25

(2M x36)

000000 000000 000000 Defines memory type and

00000110100 00000110100 00000110100 Enables unique identification

(GND).

SS

CY7C1482V25

(4M x 18)

CY7C1486V25

(1M x72)

Description

architecture

of SRAM vendor

1 1 1 Indicates the presence of an

ID register

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CY7C1480V25
CY7C1482V25
CY7C1486V25

Scan Register Sizes

Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72)

Instruction 3 3 3

Bypass 1 1 1

ID 32 32 32

Boundary Scan Order – 165FBGA 73 54 -

Boundary Scan Order – 209BGA - - 112

Identification Codes

Instruction Code Description

EXTEST 000 Captures the IO ring contents.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

SAMPLE Z 010 Captures the IO ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures the IO ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

Forces all SRAM output drivers to a High-Z state.

Does not affect SRAM operation.

operations.

Boundary Scan Exit Order (2M x 36)

Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID

1 C1 21 R3 41 L10 61 B8

2D1 22 P2 42K11 62 A7

3E1 23 R4 43J11 63 B7

4D2 24 P6 44K10 64 B6

5 E2 25 R6 45 J10 65 A6

6F1 26 N6 46H11 66 B5

7G1 27P11 47G11 67 A5

8F2 28 R8 48F11 68 A4

9G2 29 P3 49E11 69 B4

10 J1 30 P4 50 D10 70 B3

11 K1 31 P8 51 D11 71 A3

12 L1 32 P9 52 C11 72 A2

13 J2 33 P10 53 G10 73 B2

14 M1 34 R9 54 F10

15 N1 35 R10 55 E10

16 K2 36 R11 56 A10

17 L2 37 N11 57 B10

18 M2 38 M11 58 A9

19 R1 39 L11 59 B9

20 R2 40 M10 60 A8

Document #: 38-05282 Rev. *H Page 16 of 32

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CY7C1480V25
CY7C1482V25
CY7C1486V25

Boundary Scan Exit Order (4M x 18)

Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID

1D2 19R8 37 C11

2E2 20P3 38 A11

3F2 21P4 39 A10

4G2 22P8 40 B10

5J1 23P9 41 A9

6 K1 24 P10 42 B9

7L1 25R9 43 A8

8M1 26R10 44 B8

9N1 27R11 45 A7

10 R1 28 M10 46 B7

11 R2 29 L10 47 B6

12 R3 30 K10 48 A6

13 P2 31 J10 49 B5

14 R4 32 H11 50 A4

15 P6 33 G11 51 B3

16 R6 34 F11 52 A3

17 N6 35 E11 53 A2

18 P11 36 D11 54 B2

Document #: 38-05282 Rev. *H Page 17 of 32

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CY7C1480V25
CY7C1482V25
CY7C1486V25

Boundary Scan Exit Order (1M x 72)

Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID

1 A1 29 T1 57 V10 85 C11

2A2 30T2 58U11 86C10

3 B1 31 U1 59 U10 87 B11

4B2 32U2 60T11 88B10

5 C1 33 V1 61 T10 89 A11

6C2 34V2 62R11 90A10

7 D1 35 W1 63 R10 91 A9

8D2 36W2 64P11 92U8

9 E1 37 T6 65 P10 93 A7

10 E2 38 V3 66 N11 94 A5

11 F1 39 V4 67 N10 95 A6

12 F2 40 U4 68 M11 96 D6

13 G1 41 W5 69 M10 97 B6

14 G2 42 V6 70 L11 98 D7

15 H1 43 W6 71 L10 99 K3

16 H2 44 U3 72 P6 100 A8

17 J1 45 U9 73 J11 101 B4

18 J2 46 V5 74 J10 102 B3

19 L1 47 U5 75 H11 103 C3

20 L2 48 U6 76 H10 104 C4

21 M1 49 W7 77 G11 105 C8

22 M2 50 V7 78 G10 106 C9

23 N1 51 U7 79 F11 107 B9

24 N2 52 V8 80 F10 108 B8

25 P1 53 V9 81 E10 109 A4

26 P2 54 W11 82 E11 110 C6

27 R2 55 W10 83 D11 111 B7

28 R1 56 V11 84 D10 112 A3

Document #: 38-05282 Rev. *H Page 18 of 32

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CY7C1482V25
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Maximum Ratings

Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V

Supply Voltage on V

Relative to GND........ –0.3V to +3.6V

DD

Relative to GND ...... –0.3V to +V

DDQ

DD

DC Voltage Applied to Outputs

in Tri-State........................................... –0.5V to V

DDQ

+ 0.5V

Electrical Characteristics Over the Operating Range

DC Input Voltage ................................... –0.5V to V

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage........................................... >2001V

(MIL-STD-883, Method 3015)

Latch Up Current .................................................... >200 mA

Operating Range

Range

Commercial 0°C to +70°C 2.5V –5%/+5% 1.7V to

Industrial –40°C to +85°C

[12, 13]

Ambient

Tem per atur e

V

DD

+ 0.5V

DD

V

V

DDQ

DD

Parameter Description Test Conditions Min Max Unit

V

V

DD

DDQ

Power Supply Voltage 2.375 2.625 V

IO Supply Voltage for 2.5V IO 2.375 V

DD

for 1.8V IO 1.7 1.9 V

V

OH

V

OL

V

IH

Output HIGH Voltage for 2.5V IO, I

for 1.8V IO, I

Output LOW Voltage for 2.5V IO, I

for 1.8V IO, I

Input HIGH Voltage

[12]

for 2.5V IO 1.7 VDD + 0.3V V

= –1.0 mA 2.0 V

OH

= –100 µA1.6V

OH

= 1.0 mA 0.4 V

OL

= 100 µA0.2V

OL

for 1.8V IO 1.26 VDD + 0.3V V

V

IL

Input LOW Voltage

[12]

for 2.5V IO –0.3 0.7 V

for 1.8V IO –0.3 0.36 V

I

X

I

OZ

I

DD

Input Leakage Current

GND ≤ VI ≤ V

except ZZ and MODE

Input Current of MODE Input = V

Input = V

Input Current of ZZ Input = V

Input = V

SS

DD

SS

DD

Output Leakage Current GND ≤ VI ≤ V

VDD Operating Supply
Current

V

DD

f = f

= Max., I

= 1/t

MAX

DDQ

–5 5 µA

–30 µA

–5 µA

Output Disabled –5 5 µA

DDQ,

OUT

CYC

= 0 mA,

4.0-ns cycle, 250 MHz 450 mA

5.0-ns cycle, 200 MHz 450 mA

5 µA

30 µA

6.0-ns cycle, 167 MHz 400 mA

I

SB1

Automatic CE
Power Down
Current—TTL Inputs

I

SB2

Automatic CE
Power Down
Current—CMOS Inputs

I

SB3

Automatic CE
Power Down
Current—CMOS Inputs

I

SB4

Automatic CE
Power Down
Current—TTL Inputs

Notes

12. Overshoot: V

13. Power up: Assumes a linear ramp from 0V to V

(AC) < VDD +1.5V (Pulse width less than t

IH

V

= Max, Device Deselected,

DD

V

≥ VIH or VIN ≤ V

IN

f = f

V
V
f = 0

V
V
f = f

V
V

= 1/t

MAX

= Max, Device Deselected,

DD

≤ 0.3V or VIN > V

IN

= Max, Device Deselected, or

DD

≤ 0.3V or VIN > V

IN

= 1/t

MAX

= Max, Device Deselected,

DD

≥ VIH or VIN ≤ VIL, f = 0

IN

CYC

(min.) within 200 ms. During this time VIH < VDD and V

DD

IL

CYC

– 0.3V,

DDQ

– 0.3V

DDQ

CYC

/2), undershoot: VIL(AC) > –2V (Pulse width less than t

4.0-ns cycle, 250 MHz 200 mA

5.0-ns cycle, 200 MHz 200 mA

6.0-ns cycle, 167 MHz 200 mA

All speeds 120 mA

4.0-ns cycle, 250 MHz 200 mA

5.0-ns cycle, 200 MHz 200 mA

6.0-ns cycle, 167 MHz 200 mA

All speeds 135 mA

DDQ

< VDD.

CYC

/2).

V

Document #: 38-05282 Rev. *H Page 19 of 32

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CY7C1482V25
CY7C1486V25

Capacitance

Parameter Description Test Conditions

C

ADDRESS

C

DATA

Control Input Capacitance 8 8 8 pF

C

CTRL

C

CLK

C

I/O

Thermal Resistance

Parameter Description Test Conditions

Θ

JA

Θ

JC

[14]

100 TQFP

Package

Address Input Capacitance TA = 25°C, f = 1 MHz,

V

= 2.5V

Data Input Capacitance 5 5 5 pF

V

DD

DDQ

= 2.5V

666pF

165 FBGA

Package

209 FBGA

Package

Clock Input Capacitance 6 6 6 pF

Input/Output Capacitance 5 5 5 pF

[14]

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per
EIA/JESD51.

100 TQFP

Max.

24.63 16.3 15.2 °C/W

2.28 2.1 1.7 °C/W

165 FBGA

Max.

209 FBGA

Max.

AC Test Loads and Waveforms

2.5V I/O Test Load

Unit

Unit

OUTPUT

Z

1.8V I/O Test Load

OUTPUT

Z

= 50Ω

0

= 50Ω

0

R

VL= 1.25V

(a)

R

= 0.9V

V

L

(a)

= 50Ω

L

= 50Ω

L

2.5V

OUTPUT

INCLUDING

1.8V

OUTPUT

INCLUDING

5pF

JIG AND

SCOPE

5pF

JIG AND

SCOPE

R = 1667Ω

R = 1583Ω

(b)

R = 14KΩ

R = 14KΩ

(b)

V

GND

V

DDQ

0.2

DDQ

≤ 1 ns

-0.2

≤ 1 ns

ALL INPUT PULSES

10%

10%

90%

ALL INPUT PULSES

90%

90%

10%

≤ 1 ns

(c)

90%

10%

≤ 1 ns

(c)

Note

14. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05282 Rev. *H Page 20 of 32

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CY7C1482V25
CY7C1486V25

Switching Characteristics Over the Operating Range

Parameter Description

t

POWER

Clock

t

CYC

t

CH

t

CL

Output Times

t

CO

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Setup Times

t

AS

t

ADS

t

ADVS

t

WES

t

DS

t

CES

Hold Times

t

AH

t

ADH

t

ADVH

t

WEH

t

DH

t

CEH

VDD(Typical) to the first access

Clock Cycle Time 4.0 5.0 6.0 ns

Clock HIGH 2.0 2.0 2.4 ns

Clock LOW 2.0 2.0 2.4 ns

Data Output Valid After CLK Rise 3.0 3.0 3.4 ns

Data Output Hold After CLK Rise 1.3 1.3 1.5 ns

Clock to Low-Z

Clock to High-Z

[18, 19, 20]

[18, 19, 20]

OE LOW to Output Valid 3.0 3.0 3.4 ns

OE LOW to Output Low-Z

OE HIGH to Output High-Z

Address Setup Before CLK Rise 1.4 1.4 1.5 ns

ADSC, ADSP Setup Before CLK Rise 1.4 1.4 1.5 ns

ADV Setup Before CLK Rise 1.4 1.4 1.5 ns

GW, BWE, BWX Setup Before CLK Rise 1.4 1.4 1.5 ns

Data Input Setup Before CLK Rise 1.4 1.4 1.5 ns

Chip Enable Setup Before CLK Rise 1.4 1.4 1.5 ns

Address Hold After CLK Rise 0.4 0.4 0.5 ns

ADSP, ADSC Hold After CLK Rise 0.4 0.4 0.5 ns

ADV Hold After CLK Rise 0.4 0.4 0.5 ns

GW, BWE, BWX Hold After CLK Rise 0.4 0.4 0.5 ns

Data Input Hold After CLK Rise 0.4 0.4 0.5 ns

Chip Enable Hold After CLK Rise 0.4 0.4 0.5 ns

[17]

[18, 19, 20]

[18, 19, 20]

[15, 16]

250 MHz 200 MHz 167 MHz

Min. Max. Min. Max. Min. Max.

Unit

111ms

1.3 1.3 1.5 ns

3.0 3.0 3.4 ns

000 ns

3.0 3.0 3.4 ns

Notes

15. Timing reference level is 1.25V when V

16. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 20 unless otherwise noted.

17. This part has a voltage regulator internally; t
can be initiated.

, t

, t

18. t

CHZ

CLZ

steady-state voltage.

19. At any possible voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z before Low-Z under the same system conditions.

20. This parameter is sampled and not 100% tested.

OELZ

, and t

are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms. Transition is measured ±200 mV from

OEHZ

= 2.5V and is 0.9V when V

DDQ

POWER

OEHZ

Document #: 38-05282 Rev. *H Page 21 of 32

= 1.8V.

DDQ

is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation

is less than t

OELZ

and t

is less than t

CHZ

to eliminate bus contention between SRAMs when sharing the same

CLZ

[+] Feedback

Switching Waveforms

Read Cycle Timing

[21]

t

CYC

CY7C1480V25
CY7C1482V25
CY7C1486V25

CLK

ADSP

ADSC

ADDRESS

GW, BWE,

BWx

ADV

Data Out (Q)

t

t

CL

CH

t

t

ADH

ADS

t

t

ADH

ADS

t

t

AH

AS

A1

t

WES

t

t

CEH

CES

CE

OE

High-Z

Single READ BURST READ

A2 A3

t

WEH

t

t

ADVH

ADVS

ADV
suspends
burst.

t

t

t

CLZ

t

CO

OEHZ

Q(A1)

t

OEV

OELZ

t

CO

t

DOH

Q(A2) Q(A2 + 1) Q(A2 + 2)

Burst continued with
new base address

Q(A2) Q(A2 + 1)Q(A2 + 3)

Burst wraps around
to its initial state

Deselect
cycle

t

CHZ

Note

21. On this diagram, when CE

is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05282 Rev. *H Page 22 of 32

DON’T CARE

UNDEFINED

[+] Feedback

Switching Waveforms (continued)

Write Cycle Timing

[21, 22]

t

CYC

CY7C1480V25
CY7C1482V25
CY7C1486V25

CLK

ADSP

ADSC

ADDRESS

BWE,

BW

GW

ADV

t

t

CL

CH

t

t

ADH

ADS

t

t

ADH

ADS

t

t

AH

AS

A1

Byte write signals are
ignored for rst cycle when
ADSP initiates burst

X

t

t

CEH

CES

CE

A2 A3

t

t

WEH

WES

ADV suspends burst

ADSC extends burst

t

t

ADH

ADS

t

t

WEH

WES

t

t

ADVH

ADVS

OE

t

t

DH

DS

Data In (D)

Data Out (Q)

Note

22. Full width write can be initiated by either GW

High-Z

BURST READ BURST WRITE

t

OEHZ

D(A1)

Single WRITE

LOW; or by GW HIGH, BWE LOW and BWX LOW.

D(A2) D(A2 + 1) D(A2 + 1)

DON’T CARE

UNDEFINED

D(A2 + 2)

D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

Extended BURST WRITE

Document #: 38-05282 Rev. *H Page 23 of 32

[+] Feedback

Switching Waveforms (continued)

D

Read/Write Cycle Timing

[21, 23, 24]

t

CYC

CY7C1480V25
CY7C1482V25
CY7C1486V25

CLK

ADSP

ADSC

ADDRESS

BWE,

ADV

Data In (D)

BW

CE

OE

t

t

CL

CH

t

t

ADH

ADS

t

t

AH

AS

High-Z

t

CES

A2

t

CEH

t

CO

t

CLZ

t

OEHZ

t

WES

t

DS

D(A3)

A3

t

A1

X

A4 A5 A6

t

WEH

DH

t

OELZ

D(A5) D(A6)

ata Out (Q)

Notes

23. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP

is HIGH.

24. GW

High-Z

Document #: 38-05282 Rev. *H Page 24 of 32

Q(A2)Q(A1)

Single WRITE

DON’T CARE UNDEFINED

Q(A4) Q(A4+1) Q(A4+2)

BURST READBack-to-Back READs

Q(A4+3)

Back-to-Back

WRITEs

or ADSC.

[+] Feedback

Switching Waveforms (continued)

ZZ Mode Timing

[25, 26]

CLK

t

CY7C1480V25
CY7C1482V25
CY7C1486V25

ZZ

t

ZZREC

I

SUPPLY

ALL INPUTS

(except ZZ)

Outputs (Q)

ZZ

t

ZZI

I

DDZZ

High-Z

t

RZZI

DESELECT or READ Only

DON’T CARE

Notes

25. Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.

26. DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05282 Rev. *H Page 25 of 32

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Ordering Information

CY7C1480V25
CY7C1482V25
CY7C1486V25

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

Speed

(MHz) Ordering Code

167 CY7C1480V25-167AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1482V25-167AXC

CY7C1480V25-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1482V25-167BZC

CY7C1480V25-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1482V25-167BZXC

CY7C1486V25-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1486V25-167BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free

CY7C1480V25-167AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial

CY7C1482V25-167AXI

CY7C1480V25-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1482V25-167BZI

CY7C1480V25-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1482V25-167BZXI

CY7C1486V25-167BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1486V25-167BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free

200 CY7C1480V25-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1482V25-200AXC

CY7C1480V25-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1482V25-200BZC

CY7C1480V25-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1482V25-200BZXC

CY7C1486V25-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1486V25-200BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free

CY7C1480V25-200AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial

CY7C1482V25-200AXI

CY7C1480V25-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1482V25-200BZI

CY7C1480V25-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1482V25-200BZXI

CY7C1486V25-200BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1486V25-200BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free

visit www.cypress.com for actual products offered.

Package
Diagram

Part and Package Type

Operating

Range

Document #: 38-05282 Rev. *H Page 26 of 32

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Ordering Information (continued)

CY7C1480V25
CY7C1482V25
CY7C1486V25

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

Speed

(MHz) Ordering Code

250 CY7C1480V25-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1482V25-250AXC

CY7C1480V25-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1482V25-250BZC

CY7C1480V25-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free

CY7C1482V25-250BZXC

CY7C1486V25-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1486V25-250BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

CY7C1480V25-250AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial

CY7C1482V25-250AXI

CY7C1480V25-250BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1482V25-250BZI

CY7C1480V25-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free

CY7C1482V25-250BZXI

CY7C1486V25-250BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1486V25-250BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

visit www.cypress.com for actual products offered.

Package
Diagram

Part and Package Type

Operating

Range

Document #: 38-05282 Rev. *H Page 27 of 32

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Package Diagrams

Figure 1. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050

16.00±0.20

14.00±0.10

81

80

0.30±0.08

0.65
TYP.

51

0513

12°±1°

(8X)

20.00±0.10

22.00±0.20

100

1

30

CY7C1480V25
CY7C1482V25
CY7C1486V25

1.40±0.05

SEE DETAIL

0.20 MAX.

A

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

0° MIN.

R 0.08 MIN.

0.20 MIN.

0.20 MAX.

DETAIL

1.60 MAX.

STAND-OFF

0.05 MIN.

0.15 MAX.

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

3. DIMENSIONS IN MILLIMETERS

SEATING PLANE

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

A

0.10

51-85050-*B

Document #: 38-05282 Rev. *H Page 28 of 32

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Package Diagrams (continued)

Figure 2. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165

CY7C1480V25
CY7C1482V25
CY7C1486V25

1.00

PIN 1 CORNER

1

2345678910

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

BOTTOM VIEW

TOP VIEW

PIN 1 CORNER

1110986754321

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

+0.05

0.25 C

0.53±0.05

0.35

-0.10

0.15 C

17.00±0.10

A

1.00

14.00

7.00

B

0.15(4X)

11

5.00

Ø0.05 M C

Ø0.25 M C A B

Ø0.45±0.05(165X)

10.00

15.00±0.10

0.36

SEATING PLANE

C

1.40 MAX.

51-85165-*A

Document #: 38-05282 Rev. *H Page 29 of 32

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Package Diagrams (continued)

Figure 3. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167

CY7C1480V25
CY7C1482V25
CY7C1486V25

i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation. All products and company names
mentioned in this document may be the trademarks of their respective holders.

Document #: 38-05282 Rev. *H Page 30 of 32

© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

51-85167-**

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CY7C1480V25
CY7C1482V25
CY7C1486V25

Document History Page

Document Title: CY7C1480V25/CY7C1482V25/CY7C1486V25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
Document Number: 38-05282

REV. ECN NO. Issue Date

** 114670 08/06/02 PKS New Data Sheet

*A 118281 01/21/03 HGK Changed t

*B 233368 See ECN NJY Changed timing diagrams

*C 299452 See ECN SYT Removed 225-MHz offering and included 250-MHz speed bin

*D 323039 See ECN PCI Unshaded 200 and 167 MHz speed bin in the AC/DC Table and Selection

*E 416193 See ECN NXR Converted from Preliminary to Final

*F 470723 See ECN VKN Added the Maximum Rating for Supply Voltage on V

Orig. of

Change

Description of Change

from 2.4 to 2.6 ns for 250 MHz

Updated features on page 1 for package offering

CO

Removed 300 MHz offering
Updated Ordering Information
Changed Advanced Information to Preliminary

Changed logic block diagrams
Modified Functional Description
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Included IDD and ISB values
Removed 250-MHz speed grade offering and included 225 MHz speed bin
Changed package outline for 165FBGA package and 209-ball BGA package
Removed 119-BGA package offering

Changed t
Changed Θ
TQFP Package on Page # 20

from 4.4 ns to 4.0 ns for 250-MHz Speed Bin

CYC

from 16.8 to 24.63 °C/W and Θ

JA

from 3.3 to 2.28 °C/W for 100

JC

Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA
Packages
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information

Guide
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added Address Expansion pins in the Pin Definitions Table
Added Truth Table and Note# 7 for CY7C1486V25 on page# 11
Modified V
Added Industrial temperature range

, VOH Test Conditions

OL

Removed comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Updated Ordering Information Table

Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed the description of I
Current on page# 19
Changed the I
to -30 µA and 5 µA

current values of MODE on page # 19 from -5 µA and 30 µA

X

from Input Load Current to Input Leakage

X

Changed the IX current values of ZZ on page # 19 from -30 µA and 5 µA
to -5 µA and 30 µA
Changed V
Replaced Package Name column with Package Diagram in the Ordering

IH

< V

to VIH < V

DD

on page # 19

DD

Information table
Updated the Ordering Information Table

Relative to GND
Changed t
AC Switching Characteristics table

, t

from 25 ns to 20 ns and t

TH

TL

TDOV

DDQ

from 5 ns to 10 ns in TAP

Updated the Ordering Information table

Document #: 38-05282 Rev. *H Page 31 of 32

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CY7C1480V25
CY7C1482V25
CY7C1486V25

Document Title: CY7C1480V25/CY7C1482V25/CY7C1486V25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
Document Number: 38-05282

REV. ECN NO. Issue Date

*G 486690 See ECN VKN Corrected the typo in the 209-Ball FBGA pinout.

*H 1026720 See ECN VKN/KKVTMP Added footnote #2 related to V

Orig. of

Change

Description of Change

(Corrected the ball name H9 to VSS from V

SSQ

SSQ

).

Document #: 38-05282 Rev. *H Page 32 of 32

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