72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Features
■ Pin-compatible and functionally equivalent to ZBT™
■ Supports 250 MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 167 MHz
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte Write capability
■ Single 3.3V power supply
■ 3.3V/2.5V IO power supply
■ Fast clock-to-output time
❐ 3.0 ns (for 250-MHz device)
■ Clock Enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ CY7C1470BV33, CY7C1472BV33 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1474BV33
available in Pb-free and non-Pb-free 209-ball FBGA package
■ IEEE 1149.1 JTAG Boundary Scan compatible
■ Burst capability—linear or interleaved burst order
■ “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
are 3.3V , 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back re ad
or write operations with no wait states. The CY7C1470BV33,
CY7C1472BV33, and CY7C1474BV33 are equipped with the
advanced (NoBL) logic required to enable consecutive read or
write operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data in
systems that require frequent read or write transitions. The
CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are pin
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clo ck. The clock
input is qualified by the Clock Enable (CEN
deasserted suspends operation and extends the previou s clock
cycle.
Write operations are controlled by the Byte Write Selects
–BWd for CY7C1470BV33, BWa–BW
(BW
a
CY7C1472BV33, and BW
Write Enable (WE
) input. All writes are conducted with on-chip
–BWh for CY7C1474BV33) and a
a
synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
) signal, which when
for
b
, CE2, CE3) and an
1
) provide for easy bank
Selection Guide
Description 250 MHz 200 MHz 167 MHz Unit
Maximum Access Time 3.0 3.0 3.4 ns
Maximum Operating Current 500 500 450 mA
Maximum CMOS Standby Current 120 120 120 mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-15031 Rev. *C Revised February 29, 2008
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Logic Block Diagram – CY7C1470BV33 (2M x 36)
s
P
a
P
b
Pc
Pd
C
C
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQ
s
DQ
P
a
DQ
P
b
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1D0Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
C
LK
C
EN
WRITE
DRIVERS
ZZ
Sleep
Control
A0, A1, A
MODE
C
LK
EN
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
REGISTER 0
WRITE ADDRESS
REGISTER 1
ADDRESS
READ LOGIC
SLEEP
CONTROL
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
Logic Block Diagram – CY7C1472BV33 (4M x 18)
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
I
M
S
T
P
E
S
R
S
E
E
REGISTER 0
INPUT
O
D
U
T
A
P
T
U
A
T
B
S
T
E
E
R
I
N
G
E
DQ
U
DQ
F
DQ
F
DQ
E
DQ
R
S
E
Document #: 001-15031 Rev. *C Page 2 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Logic Block Diagram – CY7C1474BV33 (1M x 72)
A0, A1, A
MODE
C
CLK
CEN
ADV/LD
a
BW
BW
b
BW
c
BW
d
BW
e
BW
f
g
BW
BW
h
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
Sleep
Control
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
U
T
P
S
U
E
T
N
S
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
E
INPUT
REGISTER 0
O
U
T
P
D
U
A
T
T
A
B
DQs
U
S
F
T
F
E
E
E
R
R
S
I
N
G
E
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
a
b
c
d
e
f
g
h
E
Document #: 001-15031 Rev. *C Page 3 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Pin Configurations
AAA
A
A
1A0
V
SS
V
DD
A
AAA
A
A
V
DDQ
V
SS
DQb
DQb
DQb
V
SS
V
DDQ
DQb
DQb
V
SS
NC
V
DD
DQa
DQa
V
DDQ
V
SS
DQa
DQa
V
SS
V
DDQ
V
DDQ
V
SS
DQc
DQc
V
SS
V
DDQ
DQc
V
DD
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
V
SS
V
DDQ
A
A
CE
1CE2
BWa
CE
3
VDDV
SS
CLKWECEN
OE
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100999897969594939291908988878685848382
81
A
A
ADV/LD
ZZ
CY7C1470BV33
A
AAA
A
1A0
V
SS
V
DD
A
A
AAA
A
A
NC
NC
V
DDQ
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
V
DD
V
SS
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DQPb
NC
V
SS
V
DDQ
NC
NC
NC
A
A
CE
1CE2
NC
NC
BW
bBWa
CE
3
VDDV
SS
CLKWECEN
OE
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100999897969594939291908988878685848382
81
A
A
ADV/LD
ZZ
MODE
CY7C1472BV33
BWd
MODE
BWc
DQc
DQc
DQc
DQc
DQPc
DQd
DQd
DQd
DQPb
DQb
DQa
DQa
DQa
DQa
DQPa
DQb
DQb
(2M x 36)
(4M x 18)
BWb
NC
NC
NC
DQc
NC
NC(288)
NC(144)
A
NC(288)
NC(144)
DQPd
A
A
A
A
A
Figure 1. 100-Pin TQFP Pinout
Document #: 001-15031 Rev. *C Page 4 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1470BV33 (2M x 36)
CY7C1472BV33 (4M x 18)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/576M
NC/1G
DQP
c
DQ
c
DQP
d
NC
DQ
d
A
CE
1
BW
b
CE
3
BW
c
CEN
A
CE2
DQ
c
DQ
d
DQ
d
MODE
NC
DQ
c
DQ
c
DQ
d
DQ
d
DQ
d
A
V
DDQ
BW
d
BW
a
CLK
WE
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
SS
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
V
DD
V
SS
V
DD
V
SS
V
SS
V
DDQ
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
SS
NC
TCKA0
V
SS
TDI
A
A
DQ
c
V
SS
DQ
c
V
SS
DQ
c
DQ
c
NC
V
SS
V
SS
V
SS
V
SS
NC
V
SS
A1
DQ
d
DQ
d
NC/144M
NC
V
DDQ
V
SS
TMS
891011
NC/288M
A
A
ADV/LD
NC
OE
A
A
NC
V
SS
V
DDQ
NC DQP
b
V
DDQ
V
DD
DQ
b
DQ
b
DQ
b
NC
DQ
b
NC
DQ
a
DQ
a
V
DD
V
DDQ
V
DD
V
DDQ
DQ
b
V
DD
NC
V
DD
DQ
a
V
DD
V
DDQ
DQ
a
V
DDQ
V
DD
V
DD
V
DDQ
V
DD
V
DDQ
DQ
a
V
DDQ
AA
V
SS
A
A
A
DQ
b
DQ
b
DQ
b
ZZ
DQ
a
DQ
a
DQP
a
DQ
a
A
V
DDQ
A
A
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/576M
NC/1G
NC
NC
DQP
b
NC
DQ
b
A
CE
1
CE
3
BW
b
CEN
A
CE2
NC
DQ
b
DQ
b
MODE
NC
DQ
b
DQ
b
NC
NC
NC
A
V
DDQ
BW
a
CLK
WE
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
SS
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
V
DD
V
SS
V
DD
V
SS
V
SS
V
DDQ
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
SS
NC
TCKA0
V
SS
TDI
A
A
DQ
b
V
SS
NC V
SS
DQ
b
NC
NC
V
SS
V
SS
V
SS
V
SS
NC
V
SS
A1
DQ
b
NC
NC/144M
NC
V
DDQ
V
SS
TMS
891011
NC/288M
A A
ADV/LD
A
OE
A
A
NC
V
SS
V
DDQ
NC DQP
a
V
DDQ
V
DD
NC
DQ
a
DQ
a
NC
NC
NC
DQ
a
NC
V
DD
V
DDQ
V
DD
V
DDQ
DQ
a
V
DD
NC
V
DD
NCV
DD
V
DDQ
DQ
a
V
DDQ
V
DD
V
DD
V
DDQ
V
DD
V
DDQ
NC
V
DDQ
AA
V
SS
A
A
A
DQ
a
NC
NC
ZZ
DQ
a
NC
NC
DQ
a
A
V
DDQ
A
A
NC
NC
Document #: 001-15031 Rev. *C Page 5 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Pin Configurations (continued)
CY7C1474BV33 (1M × 72)
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
123456789 1110
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQc
DQc
DQc
DQc
NC
DQPg
DQh
DQh
DQh
DQh
DQd
DQd
DQd
DQd
DQPd
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQf
DQf
DQf
DQf
NC
DQPf
DQa
DQa
DQa
DQa
DQe
DQe
DQe
DQe
DQPa
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
AAAA
NC
NC
NC/144M
A A NC/288M
A
AA
AA
A
A1
A0
A
AA
AA
A
NC/576M
NC
NC
NC
NC
NC
BWS
b
BWS
f
BWSeBWS
a
BWScBWS
g
BWS
d
BWS
h
TMS
TDI TDO TCK
NC
NC MODE
NC
CEN
V
SS
NC
CLK
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/1G
V
DD
NC
OE
CE
3
CE
1
CE
2
ADV/LD
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
ZZ
V
SS
V
SS
V
SS
V
SS
NC
V
DDQ
V
SS
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Document #: 001-15031 Rev. *C Page 6 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
T able 1. Pin Definitions
Pin Name IO Type Pin Description
A0
A1
Input-
Synchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge
of the CLK.
A
BW
a
BW
b
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
WE
ADV/LD Input-
Input-
Synchronous
Input-
Synchronous
Synchronous
Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
BW
controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf
c
controls DQ
and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.
f
controls DQa and DQPa, BWb controls DQb and DQPb,
a
Write Enable Input, Active LOW . Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input Used to Advance the On-chip Address Counter or Load a New
Address. When HIGH (and CEN
is asserted LOW) the internal burst counter is advanced. When
LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD
must be driven LOW to load a new address.
CLK Input-
Clock
CE
CE
CE
OE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN
is active LOW.
Chip Enable 1 Input, Active LOW . Sampled on the rising edge of CLK. Used in conjunction with
and CE3 to select or deselect the device.
CE
2
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE3 to select or deselect the device.
1
Chip Enable 3 Input, Active LOW . Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE2 to select or deselect the device.
1
Output Enable, Active LOW. Combined with the synchronous logic block inside the device to
control the direction of the IO pins. When LOW, the IO pins are enabled to behave as outputs.
When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
CEN
DQ
DQP
Input-
Synchronous
S
X
IO-
Synchronous
IO-
Synchronous
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
deselect the device, CEN
can be used to extend the previous cycle when required.
does not
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
controlled by OE
as outputs. When HIGH, DQ
ically tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE
during the previous clock rise of the read cycle. The direction of the pins is
[17:0]
and the internal control logic. When OE is asserted LOW, the pins can behave
–DQd are placed in a tri-state condition. The outputs are automat-
a
.
Bidirectional Data P arity IO Lines. Functionally , these signals are identical to DQX. During write
sequences, DQP
and DQP
is controlled by BW
is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg
d
is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,
a
, DQPh is controlled by BWh.
g
MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the inte rleaved burst order .
Pulled LOW selects the linear burst order. MODE must not change states during operation. When
left floating MODE defaults HIGH, to an interleaved burst order.
TDO JTAG Serial
Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.
Output
Synchronous
TDI JT AG Serial Input
Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.
Synchronous
Document #: 001-15031 Rev. *C Page 7 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
T able 1. Pin Definitions (continued)
Pin Name IO Type Pin Description
TMS T est Mode Select
This Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK.
Synchronous
TCK JTAG Clock Clock Input to the JTAG Circuitry.
V
V
V
DD
DDQ
SS
Power Supply Power Supply Inputs to the Core of the Device.
IO Power Supply Power Supply for the IO Circuitry.
Ground Ground for the Device. Should be connected to ground of the system.
NC – No Connects. This pin is not connected to the die.
NC(144M,
288M,
– These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and
1G densities.
576M, 1G)
ZZ Input-
Asynchronous
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin must be LOW or left floating.
ZZ pin has an internal pull-down.
Functional Overview
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during read or write transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
Clock Enable input signal (CEN
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (tCO) is 3.0 ns
(250-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE
, CE2, CE3) active at the rising edge of the clock. If CEN is
1
active LOW and ADV/LD
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the Write
Enable (WE
tions.
). BW
can be used to conduct Byte Write opera-
[x]
Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device has been deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
deasserted HIGH, and (4) ADV/LD
address presented to the address inputs is latched into the
Address Register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
are ALL asserted active, (3) the input signal WE is
3
). If CEN is HIGH, the clock signal
. All data outputs
is asserted LOW, the address
). All
, CE2, CE3) and an
1
) simplify depth expansion. All
is asserted LOW, (2) CE1, CE2,
is asserted LOW. The
register and onto the data bus within 3.0 ns (250-MHz device)
provided OE
access the output buffers are controlled by OE
control logic. OE
is active LOW. After the first clock of the read
and the internal
must be driven LOW to drive out the requested
data. During the second clock, a subsequent operation (read,
write, or deselect) can be initiated. Deselecting the device is also
pipelined. Therefore, when the SRAM is deselected at clock rise
by one of the chip enable signals, its output tri-states following
the next clock rise.
Burst Read Accesses
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
have an on-chip burst counter that enables the user to supply a
single address and conduct up to four reads without reasserting
the address inputs. ADV/LD
must be driven LOW to load a new
address into the SRAM, as described in the Single Read
Accesses section. The sequence of the burst counter is deter-
mined by the MODE input signal. A LOW input on MODE selects
a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and wraps around when incremented sufficiently. A
HIGH input on ADV/LD
regardless of the state of chip enables inputs or WE
increments the internal burst counter
. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
asserted LOW. The address presented to the address inputs is
are ALL asserted active, and (3) the signal WE is
3
loaded into the Address Register. The write signals are latched
into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
allows the external logic to present the data on DQ
(DQ
CY7C1472BV33, and DQ
a,b,c,d
/DQP
for CY7C1470BV33, DQ
a,b,c,d
CY7C1474BV33). In addition, the address for the subsequent
is asserted LOW, (2) CE1, CE2,
input signal. This
and DQP
a,b,c,d,e,f,g,h
/DQP
/DQP
a,b
a,b,c,d,e,f,g,h
a,b
for
for
Document #: 001-15031 Rev. *C Page 8 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
access (read, write, or deselect) is latched into the Address
Register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ
a,b,c,d
/DQP
(DQ
CY7C1472BV33, and DQ
CY7C1474BV33) (or a subset for byte write operations, see
for CY7C1470BV33, DQ
a,b,c,d
a,b,c,d,e,f,g,h
/DQP
and DQP
/DQP
a,b
a,b,c,d,e,f,g,h
a,b
for
for
“Partial Write Cycle Description” on page 11 for details) input s is
latched into the device and the write is complete.
The data written during the Write operation is controlled by BW
(BW
BW
CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
for CY7C1470BV33, BW
a,b,c,d
a,b,c,d,e,f,g,h
for CY7C1474BV33) signals. The
for CY7C1472BV33, and
a,b
provides Byte Write capability that is described in “Partial Write
Cycle Description” on page 11. Asserting the Write Enable input
(WE
) with the selected BW input selectively writes to only the
desired bytes. Bytes not selected during a Byte Write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte Write
capability has been included to greatly simplify read, modify, or
write sequences, which can be reduced to simple Byte Write
operations.
Because the CY7C1470BV33, CY7C1472BV33, and
CY7C1474BV33 are common IO devices, data must not be
driven into the device while the outputs are active. The OE
be deasserted HIGH before presenting data to the DQ
(DQ
CY7C1472BV33, and DQ
CY7C1474BV33) inputs. Doing so tri-states the output drivers.
As a safety precaution, DQ
CY7C1470BV33, DQ
DQ
automatically tri-stated during the data portion of a write cycle,
/DQP
a,b,c,d
a,b,c,d,e,f,g,h
for CY7C1470BV33, DQ
a,b,c,d
a,b,c,d,e,f,g,h
and DQP (DQ
/DQP
/DQP
a,b
a,b,c,d,e,f,g,h
for CY7C1472BV33, and
a,b
for CY7C1474BV33) are
/DQP
a,b,c,d
/DQP
a,b
a,b,c,d,e,f,g,h
/DQP
can
and DQP
for
a,b
for
for
a,b,c,d
regardless of the state of OE.
Burst Write Accesses
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
has an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD
load the initial address, as described in “Single Write Accesses”
on page 8. When ADV/LD
is driven HIGH on the subsequent
must be driven LOW to
clock rise, the Chip Enables (CE
are ignored and the burst counter is incremented. The corre ct
BW (BW
and BW
in each cycle of the burst wri te to write t he correct b ytes of dat a.
for CY7C1470BV33, BW
a,b,c,d
a,b,c,d,e,f,g,h
for CY7C1474BV33) inputs must be driven
, CE2, and CE3) and WE inputs
1
for CY7C1472V33,
a,b
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
, must remain inactive for the duration of t
3
ZZREC
Table 2. Interleaved Burst Address Table
(MODE = Floating or V
First
Address
)
DD
Second
Address
Third
Address
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Table 3. Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
after the
Fourth
Fourth
, CE2,
1
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Document #: 001-15031 Rev. *C Page 9 of 30
Sleep mode standby current ZZ > VDD − 0.2V 120 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
ZZ active to sleep current This parameter is sampled 2t
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
CYC
CYC
CYC
ns
ns
ns
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Table 4. Truth Table
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE
stands for ALL Chip Enables active. BWx = 0 signifies at least one By te Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see “Partial Write Cycle Description” on page 11 for details.
2. Write is defined by WE
and BW
[a:d]
. See “Partial Write Cycle Description” on page 11 for details.
3. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE
signal.
5. CEN
= H inserts wait states.
6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE
.
7. OE
is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle DQs and DQP
[a:d]
= tri-state when OE is
inactive or when the device is deselected, and DQ
s
= data when OE is active.
The truth table for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows.
[1, 2, 3, 4, 5, 6, 7]
Operation Address Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ
Deselect Cycle None H L L X X X L L-H Tri-State
Continue
None X L H X X X L L-H Tri-State
Deselect Cycle
Read Cycle
External L L L H X L L L-H Data Out (Q)
(Begin Burst)
Read Cycle
Next X L H X X L L L-H Data Out (Q)
(Continue Burst)
NOP/Dummy Read
External L L L H X H L L-H Tri-State
(Begin Burst)
Dummy Read
Next XL H XXH LL-H Tri-State
(Continue Burst)
Write Cycle
External L L L L L X L L-H Data In (D)
(Begin Burst)
Write Cycle
Next X L H X L X L L-H Data In (D)
(Continue Burst)
NOP/Write Abort
None L L L L H X L L-H Tri-State
(Begin Burst)
Write Abort
Next X L H X H X L L-H Tri-State
(Continue Burst)
Ignore Clock Edge
Current X L X X X X H L-H -
(Stall)
Sleep Mode None X H X X X X X X Tri-State
Document #: 001-15031 Rev. *C Page 10 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Table 5. Partial Write Cycle Description
Note
8. Ta ble lists only a partial listing of the Byte Write combinations. Any combination of BW
[a:d]
is valid. Appropriate Write is based on which Byte Write is active.
The partial write cycle description for CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 follows.
[1, 2, 3, 8]
Function (CY7C1470BV33) WE BW
d
BW
c
BW
b
BW
a
Read H X X X X
Write – No bytes written L H H H H
Write Byte a – (DQa and DQPa)LHHHL
Write Byte b – (DQ
and DQPb)LHHLH
b
Write Bytes b, a L H H L L
Write Byte c – (DQc and DQPc)LHLHH
Write Bytes c, a L H L H L
Write Bytes c, b L H L L H
Write Bytes c, b, a L H L L L
Write Byte d – (DQ
and DQPd) LLHHH
d
Write Bytes d, a L L H H L
Write Bytes d, b L L H L H
Write Bytes d, b, a L L H L L
Write Bytes d, c L L L H H
Write Bytes d, c, a L L L H L
Write Bytes d, c, b L L L L H
Write All Bytes L L L L L
Function (CY7C1472BV33) WE BW
b
BW
a
Read Hxx
Write – No Bytes Written L H H
Write Byte a – (DQ
and DQPa)LHL
a
Write Byte b – (DQb and DQPb)LLH
Write Both Bytes L L L
Function (CY7C1474BV33) WE BW
x
Read Hx
Write – No Bytes Written L H
Write Byte X − (DQ
Write All Bytes L All BW
and DQP
x
x)
LL
= L
Document #: 001-15031 Rev. *C Page 11 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
TEST-LOGIC
RESET
RUN-TEST/
IDLE
SELE CT
DR-SCAN
SELE CT
IR-SCAN
CAPTU RE-DR
SHIFT -DR
CAPTU RE-IR
SHIFT -IR
EXIT1-DR
PAU SE-DR
EXIT1-IR
PAU SE-IR
EXIT2-DR
UPDATE-DR
EXIT2-IR
UPDATE-IR
1
1
1
0
1 1
0 0
1 1
1
0
0
0
0 0
0
0
0 0
1
0
1
1
0
1
0
1
1
1
1 0
Bypass Register
0
Instruction Register
012
Identication Register
012293031 ...
Boundary Scan Register
012..x ...
Sele ction
Circuitry
TCK
TMS
TAP CONTROLLER
TDI TDO
Sele ction
Circuitry
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
incorporates a serial boundary scan test access port (TAP). This
port operates in accordance with IEEE Standard 1149.1-1990
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V IO logic levels.
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to V
unconnected. During power up, the device comes up in a reset
state, which does not interfere with the operation of the device.
Figure 2. TAP Controller State Diagram
through a pull up resistor. TDO must be left
DD
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See TAP Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP st ate machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register . (See TAP Controller State Diagram.)
Figure 3. TAP Controller Block Diagram
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Document #: 001-15031 Rev. *C Page 12 of 30
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
During power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
scans data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register .
Data is serially loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of TCK.
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the “TAP Controller Block Diagram”
on page 12. During power up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (V
BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the inp ut and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TD O balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the IO ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in “Identification Register Definitions” on
page 17.
) when the
SS
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Identification
Codes” on page 17. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the IO buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the IO ring when these instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller is moved
into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is executed
whenever the instruction register is loaded with all 0s. EXTEST
is not implemented in this SRAM TAP controller, and therefore
this device is not compliant to 1149.1. The TAP controller does
recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
during power up or whenever the TAP controller is in a test logic
reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO balls when the TAP controller is in a
Shift-DR state. It also places all SRAM outputs into a High-Z
state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output may undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
time (t
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
plus tCH).
CS
Document #: 001-15031 Rev. *C Page 13 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
possible to capture all other signals and simply ignore the value
t
TL
Test Clock
(TCK)
123456
T
est Mode Select
(TMS)
t
TH
Test Data-Out
(TDO)
t
CYC
Test Data-In
(TDI)
t
TMSH
t
TMSS
t
TDIH
t
TDIS
t
TDOX
t
TDOV
DON’T CARE UNDEFINED
of the CLK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the T AP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not implemented, putting the TA P to the Update-DR state while performing
a SAMPLE/PRELOAD instruction has the same effect as the
Pause-DR command.
Figure 4. TAP Timing
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 001-15031 Rev. *C Page 14 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
TAP AC Switching Characteristics
Notes
9. t
CS
and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10.Test conditions are specified using the load in TAP AC Test Conditions. t
R/tF
= 1 ns.
Over the Operating Range
Parameter Description Min Max Unit
Clock
t
TCYC
t
TF
t
TH
t
TL
TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH time 20 ns
TCK Clock LOW time 20 ns
Output Times
t
TDOV
t
TDOX
TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns
Setup Times
t
TMSS
t
TDIS
t
CS
TMS Setup to TCK Clock Rise 5 ns
TDI Setup to TCK Clock Rise 5 ns
Capture Setup to TCK Rise 5 ns
Hold Times
t
TMSH
t
TDIH
t
CH
TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns
[9, 10]
Document #: 001-15031 Rev. *C Page 15 of 30
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
3.3V TAP AC Test Conditions
TDO
1.25V
20pF
Z = 50Ω
O
50Ω
Note
11.All voltages refer to V
SS
(GND).
2.5V TAP AC Test Conditions
Input pulse levels.................................................VSS to 3.3V
Input rise and fall times....................................................1 ns
Input timing reference levels...........................................1.5V
Output reference levels ..................................................1.5V
Test load termination supply voltage ..............................1.5V
3.3V TAP AC Output Load Equivalent
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time.....................................................1 ns
Input timing reference levels ........................................1.25V
Output reference levels................................................1.25V
Test load termination supply voltage............................ 1.25V
2.5V TAP AC Output Load Equivalent
1.5V
50Ω
TDO
Z = 50Ω
O
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)
Parameter Description Test Conditions Min Max Unit
V
V
V
V
V
V
I
OH1
OH2
OL1
OL2
IH
IL
X
Output HIGH Voltage IOH = –4.0 mA,V
= –1.0 mA,V
I
OH
Output HIGH Voltage IOH = –100 µA V
Output LOW Voltage IOL = 8.0 mA V
= 1.0 mA V
I
OL
Output LOW Voltage IOL = 100 µA V
Input HIGH Voltage V
Input LOW Voltage V
Input Load Current GND < VIN < V
DDQ
[11]
= 3.3V 2.4 V
DDQ
= 2.5V 2.0 V
DDQ
= 3.3V 2.9 V
DDQ
= 2.5V 2.1 V
V
DDQ
= 3.3V 0.4 V
DDQ
= 2.5V 0.4 V
DDQ
= 3.3V 0.2 V
DDQ
= 2.5V 0.2 V
V
DDQ
= 3.3V 2.0 VDD + 0.3 V
DDQ
= 2.5V 1.7 VDD + 0.3 V
V
DDQ
= 3.3V –0.3 0.8 V
DDQ
= 2.5V –0.3 0.7 V
V
DDQ
–5 5 µA
Document #: 001-15031 Rev. *C Page 16 of 30
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CY7C1472BV33, CY7C1474BV33
Table 6. Identification Register Definitions
Note
12.Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Instruction Field
Revision Number (31:29) 000 000 000 Describes the version number
Device Depth (28:24)
Architecture/Memory
Type(23:18)
Bus Width/Density(17:12) 100100 010100 110100 Defines width and density
Cypress JEDEC ID Code
(11:1)
ID Register Presence
Indicator (0)
T able 7. Scan Register Sizes
Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72)
Instruction 3 3 3
Bypass 1 1 1
ID 32 32 32
Boundary Scan Order – 165 FBGA 71 52 Boundary Scan Order – 209 FBGA - - 110
[12]
CY7C1470BV33
(2M x 36)
01011 01011 01011 Reserved for internal use
001000 001000 001000 Defines memory type and archi-
00000110100 00000110100 00000110100 Enables unique identification of
1 1 1 Indicates the presence of an ID
CY7C1472BV33
(4M x 18)
CY7C1474BV33
(1M x 72)
Description
tecture
SRAM vendor
register
Table 8. Identification Codes
Instruction Code Description
EXTEST 000 Captures IO ring contents. Places the boundary scan register between TDI and TDO.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI
SAMPLE Z 010 Captures IO ring contents. Places the boundary scan register between TDI and TDO.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures IO ring contents. Places the boundary scan register between TDI and TDO.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
and TDO. This operation does not affect SRAM operations.
Forces all SRAM output drivers to a High-Z state.
Does not affect SRAM operation. This instruction does not implement 1 149.1 preload
function and is therefore not 1149.1 compliant.
Document #: 001-15031 Rev. *C Page 17 of 30
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Table 9. Boundary Scan Exit Order (2M x 36)
Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID
1C1 21 R3 41J11 61B7
2 D1 22 P2 42 K10 62 B6
3E1 23 R4 43J10 63A6
4D2 24 P6 44H11 64B5
5E2 25 R6 45G11 65A5
6F1 26 R8 46F11 66A4
7G1 27 P3 47E11 67B4
8 F2 28 P4 48 D10 68 B3
9G2 29 P8 49D11 69A3
10 J1 30 P9 50 C11 70 A2
11 K1 31 P10 51 G10 71 B2
12 L1 32 R9 52 F10
13 J2 33 R10 53 E10
14 M1 34 R11 54 A9
15 N1 35 N11 55 B9
16 K2 36 M11 56 A10
17 L2 37 L11 57 B10
18 M2 38 M10 58 A8
19 R1 39 L10 59 B8
20 R2 40 K11 60 A7
Table 10. Boundary Scan Exit Order (4M x 18)
Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID
1D2 14 R4 27L10 40B10
2 E2 15 P6 28 K10 41 A8
3 F2 16 R6 29 J10 42 B8
4G2 17 R8 30H11 43A7
5J1 18 P3 31G11 44B7
6K1 19 P4 32F11 45B6
7L1 20 P8 33E11 46A6
8M1 21 P9 34D11 47B5
9 N1 22 P10 35 C11 48 A4
10 R1 23 R9 36 A11 49 B3
11 R2 24 R10 37 A9 50 A3
12 R3 25 R11 38 B9 51 A2
13 P2 26 M10 39 A10 52 B2
Document #: 001-15031 Rev. *C Page 18 of 30
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Boundary Scan Exit Order (1M x 72)
Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID
1A1 29T1 57U10 85B11
2A2 30T2 58T11 86B10
3B1 31U1 59T10 87A11
4B2 32U2 60R11 88A10
5C1 33V1 61R10 89A7
6C2 34V2 62P11 90A5
7D1 35W1 63P10 91A9
8D2 36W2 64N11 92U8
9E1 37T6 65N10 93A6
10 E2 38 V3 66 M11 94 D6
11 F1 39 V4 67 M10 95 K6
12 F2 40 U4 68 L11 96 B6
13 G1 41 W5 69 L10 97 K3
14 G2 42 V6 70 P6 98 A8
15 H1 43 W6 71 J11 99 B4
16 H2 44 V5 72 J10 100 B3
17 J1 45 U5 73 H11 101 C3
18 J2 46 U6 74 H10 102 C4
19 L1 47 W7 75 G11 103 C8
20 L2 48 V7 76 G10 104 C9
21 M1 49 U7 77 F11 105 B9
22 M2 50 V8 78 F10 106 B8
23 N1 51 V9 79 E10 107 A4
24 N2 52 W11 80 E11 108 C6
25 P1 53 W10 81 D11 109 B7
26 P2 54 V11 82 D10 110 A3
27 R2 55 V10 83 C11
28 R1 56 U11 84 C10
Document #: 001-15031 Rev. *C Page 19 of 30
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CY7C1472BV33, CY7C1474BV33
Maximum Ratings
Notes
13.Overshoot: V
IH
(AC) < V
DD
+1.5V (pulse width less than t
CYC
/2). Undershoot: VIL(AC)> –2V (pulse width less than t
CYC
/2).
14.T
Power-up
: assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time VIH < V
DD
and V
DDQ
< V
DD
.
15.The operation current is calculated with 50% read cycle and 50% write cycle.
Exceeding maximum ratings may impair the useful life of th e
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +125°C
Supply Voltage on V
Supply Voltage on V
DC to Outputs in Tri-State....................–0.5V to V
Relative to GND........–0.5V to +4.6V
DD
Relative to GND.......–0.5V to +V
DDQ
DDQ
DD
+ 0.5V
DC Input Voltage................................... –0.5V to V
+ 0.5V
DD
Current into Outputs (LOW) ........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch Up Current................................................... > 200 mA
Operating Range
Range
Commercial 0°C to +70°C 3.3V
Industrial –40°C to +85°C
Ambient
Temperature
V
DD
–5%/+10%
V
DDQ
2.5V – 5%
to V
DD
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Max Unit
V
V
V
V
V
V
I
DD
DDQ
OH
OL
IH
IL
X
Power Supply Voltage 3.135 3.6 V
IO Supply Voltage For 3.3V IO 3.135 V
Output HIGH Voltage For 3.3V IO, I
Output LOW Voltage For 3.3V IO, IOL= 8.0 mA 0.4 V
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
except ZZ and MODE
Input Current of MODE Input = V
Input Current of ZZ Input = V
I
OZ
I
DD
I
SB1
[15]
Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply V
Automatic CE
Power Down
Current—TTL Inputs
I
SB2
Automatic CE
Power Down
Current—CMOS Inputs
[13, 14]
For 2.5V IO 2.375 2.625 V
= −4.0 mA 2.4 V
OH
For 2.5V IO, IOH= −1.0 mA 2.0 V
For 2.5V IO, IOL= 1.0 mA 0.4 V
[13]
For 3.3V IO 2.0 VDD + 0.3V V
For 2.5V IO 1.7 VDD + 0.3V V
[13]
For 3.3V IO –0.3 0.8 V
For 2.5V IO –0.3 0.7 V
GND ≤ VI ≤ V
SS
Input = V
Input = V
DD
f = f
DD
SS
DD
= Max., I
= 1/t
MAX
DDQ
Output Disabled –5 5 μA
DDQ,
OUT
CYC
= 0 mA,
4.0-ns cycle, 250 MHz 500 mA
5.0-ns cycle, 200 MHz 500 mA
–5 5 μA
–30 μA
–5 μA
6.0-ns cycle, 167 MHz 450 mA
Max. VDD, Device Deselected,
V
≥ VIH or VIN ≤ VIL,
IN
MAX
= 1/t
CYC
f = f
Max. VDD, Device Deselected,
V
≤ 0.3V or VIN > V
IN
f = 0
DDQ
− 0.3V,
4.0-ns cycle, 250 MHz 245 mA
5.0-ns cycle, 200 MHz 245 mA
6.0-ns cycle, 167 MHz 245 mA
All speed grades 120 mA
DD
5 μA
30 μA
V
Document #: 001-15031 Rev. *C Page 20 of 30
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CY7C1472BV33, CY7C1474BV33
Electrical Characteristics
OUTPUT
R = 317Ω
R = 351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50Ω
Z
0
= 50Ω
VL= 1.5V
3.3V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
≤ 1 ns
≤ 1 ns
(c)
3.3V IO Test Load
OUTPUT
R = 1667Ω
R = 1538Ω
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50Ω
Z
0
= 50Ω
V
L
= 1.25V
2.5V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
≤ 1 ns
≤ 1 ns
(c)
2.5V IO Test Load
Over the Operating Range
Parameter Description T est Conditions Min Max Unit
I
SB3
Automatic CE
Power Down
Current—CMOS Inputs
I
SB4
Automatic CE
Power Down
Current—TTL Inputs
[13, 14]
(continued)
Max. VDD, Device Deselected,
V
≤ 0.3V or VIN > V
IN
f = f
MAX
= 1/t
CYC
Max. VDD, Device Deselected,
V
≥ VIH or VIN ≤ VIL, f = 0
IN
DDQ
− 0.3V,
4.0-ns cycle, 250 MHz 245 mA
5.0-ns cycle, 200 MHz 245 mA
6.0-ns cycle, 167 MHz 245 mA
All speed grades 135 mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions
C
ADDRESS
C
DATA
C
Control Input Capacitance 8 8 8 pF
CTRL
C
CLK
C
IO
Address Input Capacitance TA = 25°C, f = 1 MHz,
= 3.3V
V
Data Inpu t Capacita nce 5 5 5 pF
V
DD
DDQ
= 2.5V
Clock Input Capacitance 6 6 6 pF
Input/Output Capacitance 5 5 5 pF
100 TQFP
Max
6 6 6 pF
165 FBGA
Max
209 FBGA
Max
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameters Description Test Conditions
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA/JESD51.
100 TQFP
Package
24.63 16.3 15.2 °C/W
2.28 2.1 1.7 °C/W
165 FBGA
Package
209 FBGA
Package
Unit
Unit
AC Test Loads and Waveforms
Document #: 001-15031 Rev. *C Page 21 of 30
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CY7C1472BV33, CY7C1474BV33
Switching Characteristics
Notes
16.This part has an internal voltage regulator; t
power
is the time power is supplied above VDD minimum initially, before a read or write operation can be initiated.
17.t
CHZ
, t
CLZ
, t
EOLZ
, and t
EOHZ
are specified with AC test conditions shown in (b) of “AC Test Loads and Waveforms” on page 21. Transition is measured ±200 mV
from steady-state voltage.
18.At any voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High-Z before Low-Z under the same system conditions.
19.This parameter is sampled and not 100% tested.
Over the Operating Range. Timing reference is 1.5V when V
(a) of “AC Test Loads and Waveforms” on page 21 unless otherwise noted.
= 3.3V and is 1.25V when V
DDQ
= 2.5V. Test conditions shown in
DDQ
Parameter Description
[16]
t
Power
VCC (typical) to the First Access Read or Write 1 1 1 ms
Clock
t
CYC
F
MAX
t
CH
t
CL
Clock Cycle Time 4.0 5.0 6.0 ns
Maximum Operating Frequency 250 200 167 MHz
Clock HIGH 2.0 2.0 2.2 ns
Clock LOW 2.0 2.0 2.2 ns
Output Times
t
CO
t
OEV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Data Output Valid After CLK Rise 3.0 3.0 3.4 ns
OE LOW to Output Valid 3.0 3.0 3.4 ns
Data Output Hold After CLK Rise 1.3 1.3 1.5 ns
Clock to High-Z
Clock to Low-Z
[17, 18, 19]
[17, 18, 19]
OE HIGH to Output High-Z
OE LOW to Output Low-Z
Setup Times
t
AS
t
DS
t
CENS
t
WES
t
ALS
t
CES
Address Setup Before CLK Rise 1.4 1.4 1.5 ns
Data Input Setup Before CLK Rise 1.4 1.4 1.5 ns
CEN Setup Before CLK Rise 1.4 1.4 1.5 ns
WE, BWx Setup Before CLK Rise 1.4 1.4 1.5 ns
ADV/LD Setup Before CLK Rise 1.4 1.4 1.5 ns
Chip Select Setup 1.4 1.4 1.5 ns
Hold Times
t
AH
t
DH
t
CENH
t
WEH
t
ALH
t
CEH
Address Hold After CLK Rise 0.4 0.4 0.5 ns
Data Input Hold After CLK Rise 0.4 0.4 0.5 ns
CEN Hold After CLK Rise 0.4 0.4 0.5 ns
WE, BWx Hold After CLK Rise 0.4 0.4 0.5 ns
ADV/LD Hold after CLK Rise 0.4 0.4 0.5 ns
Chip Select Hold After CLK Rise 0.4 0.4 0.5 ns
[17, 18, 19]
[17, 18, 19]
–250 –200 –167
Min Max Min Max Min Max
Unit
3.0 3.0 3.4 ns
1.3 1.3 1.5 ns
3.0 3.0 3.4 ns
0 0 0 ns
Document #: 001-15031 Rev. *C Page 22 of 30
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CY7C1472BV33, CY7C1474BV33
Switching Waveforms
123 456789
10
I
Notes
20.For this waveform ZZ is tied LOW.
21.When CE
is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.
22.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1= Interleaved). Burst operations are optional.
Figure 5 shows read-write timing waveform.
t
CYC
CLK
t
CEN
CE
ADV/LD
WE
BW
t
CENS
CENH
t
t
CES
CEH
x
t
t
CL
CH
[20, 21, 22]
Figure 5. Read/Write Timing
ADDRESS
Data
n-Out (DQ)
OE
A1 A2
t
t
AH
AS
WRITE
D(A1)
WRITE
D(A2)
A3
t
t
DH
DS
D(A1) D(A2) D(A5)Q(A4)Q(A3)
BURST
WRITE
D(A2+1)
READ
Q(A3)
A4
t
t
D(A2+1)
READ
Q(A4)
CO
CLZ
BURST
READ
Q(A4+1)
t
DOH
A5 A6 A7
t
OEV
t
OEHZ
t
OELZ
WRITE
D(A5)
DON’T CARE UNDEFINED
t
Q(A4+1)
t
DOH
READ
Q(A6)
CHZ
WRITE
D(A7)
Q(A6)
DESELECT
Document #: 001-15031 Rev. *C Page 23 of 30
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Switching Waveforms (continued)
456 78910
123
t
ZZ
I
SUPPLY
CLK
ZZ
t
ZZREC
A
LL INPUTS
(except ZZ)
DON’T CARE
I
DDZZ
t
ZZI
t
RZZI
Outputs (Q)
High-Z
DESELECT or READ Only
Notes
23.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN
being used to create a pause. A Write is not performed during this cycle.
24.Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.
25.IOs are in High-Z when exiting ZZ sleep mode.
Figure 6 shows NOP, STALL and DESELECT Cycles waveform.
Figure 6. NOP, STALL and DESELECT Cycles
CLK
CEN
CE
ADV/LD
WE
BWx
[20, 21, 23]
ADDRESS
Data
In-Out (DQ)
A1
D(A1)
A2
READ
Q(A2)
Figure 7 shows ZZ Mode timing waveform.
A3 A4
D(A1) Q(A2) Q(A3)
STALL NOP READ
READ
Q(A3)
[24, 25]
WRITE
D(A4)
DON’T CARE UNDEFINED
STALLWRITE
A5
D(A4)
DESELECT CONTINUE
Q(A5)
Figure 7. ZZ Mode Timing
t
CHZ
Q(A5)
DESELECT
Document #: 001-15031 Rev. *C Page 24 of 30
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CY7C1472BV33, CY7C1474BV33
Ordering Information
Not all of the speed, package and temperature ranges are available. Pl ease contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
167 CY7C1470BV33-167AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free Commercial
200 CY7C1470BV33-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free Commercial
Ordering Code
CY7C1472BV33-167AXC
CY7C1470BV33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1472BV33-167BZC
CY7C1470BV33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1472BV33-167BZXC
CY7C1474BV33-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1474BV33-167BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
CY7C1470BV33-167AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free lndustrial
CY7C1472BV33-167AXI
CY7C1470BV33-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1472BV33-167BZI
CY7C1470BV33-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1472BV33-167BZXI
CY7C1474BV33-167BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1474BV33-167BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
CY7C1472BV33-200AXC
CY7C1470BV33-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1472BV33-200BZC
CY7C1470BV33-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1472BV33-200BZXC
CY7C1474BV33-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1474BV33-200BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
CY7C1470BV33-200AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free lndustrial
CY7C1472BV33-200AXI
CY7C1470BV33-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1472BV33-200BZI
CY7C1470BV33-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1472BV33-200BZXI
CY7C1474BV33-200BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1474BV33-200BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
Package
Diagram
Part and Package Type
Operating
Range
Document #: 001-15031 Rev. *C Page 25 of 30
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CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Pl ease contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
250 CY7C1470BV33-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free Commercial
Ordering Code
CY7C1472BV33-250AXC
CY7C1470BV33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1472BV33-250BZC
CY7C1470BV33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1472BV33-250BZXC
CY7C1474BV33-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1474BV33-250BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
CY7C1470BV33-250AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free Industrial
CY7C1472BV33-250AXI
CY7C1470BV33-250BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1472BV33-250BZI
CY7C1470BV33-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1472BV33-250BZXI
CY7C1474BV33-250BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1474BV33-250BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free
Package
Diagram
Part and Package Type
Operating
Range
Document #: 001-15031 Rev. *C Page 26 of 30
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Package Diagrams
51-85050-*B
Figure 8. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
R 0.08 MIN.
0.20 MAX.
0.25
GAUGE PLANE
0°-7°
0.60±0.15
1.00 REF.
20.00±0.10
22.00±0.20
1
30
0° MIN.
100
R 0.08 MIN.
0.20 MAX.
0.20 MIN.
DETAIL
16.00±0.20
14.00±0.10
A
81
0513
80
0.30±0.08
0.65
TYP.
51
STAND-OFF
0.05 MIN.
0.15 MAX.
1.40±0.05
12°±1°
(8X)
SEATING PLANE
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
SEE DETAIL
0.20 MAX.
1.60 MAX.
0.10
A
Document #: 001-15031 Rev. *C Page 27 of 30
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CY7C1472BV33, CY7C1474BV33
Package Diagrams (continued)
A
1
PIN 1 CORNER
17.00±0.10
15.00±0.10
7.00
1.00
Ø0.45±0.05(165X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.35
1.40 MAX.
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
PIN 1 CORNER
TOP VIEW
BOTTOM VIEW
2345678910
10.00
14.00
B
C
D
E
F
G
H
J
K
L
M
N
11
1110986754321
P
R
P
R
K
M
N
L
J
H
G
F
E
D
C
B
A
C
1.00
5.00
0.36
+0.05
-0.10
51-85165-*A
Figure 9. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165
Document #: 001-15031 Rev. *C Page 28 of 30
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CY7C1472BV33, CY7C1474BV33
Package Diagrams (continued)
51-85167-**
Figure 10. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167
Document #: 001-15031 Rev. *C Page 29 of 30
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CY7C1472BV33, CY7C1474BV33
Document History Page
Document Title: CY7C1470BV33/CY7C1472BV33/CY7C1474BV33, 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM
with NoBL™ Architecture
Document Number: 001-15031
REV. ECN No. Issue Date
** 1032642 See ECN VKN/KKVTMP New Data Sheet
*A 1897447 See ECN VKN/AESA Added footnote 15 related to IDD
*B 2082487 See ECN VKN Converted from preliminary to final
*C 2159486 See ECN VKN/PYRS Minor Change-Moved to the external web
Orig. of
Change
Description of Change
© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life sa vin g, critical control or safety applications, unl ess p ur sua nt to an express written agreement with Cypress. Fur th ermo r e, Cyp r ess d oe s no t a uth or iz e its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States co pyright la ws and inte rnatio na l tre aty prov isi ons. Cyp ress he reby g rant s to lice nsee a p erson al, no n-ex clusi ve, non-tra nsferable license to copy, use, modify , create derivative works of ,
and compile the Cypress Source Code and derivative works for the sole purpo se of creating custom sof tware and or firm ware in support of licen see product to be use d only in conjunction with a Cypress
integrated circuit as specified in th e applicable agreement. Any reproductio n, modification, translation, co mpilation, o r representati on of this Sour ce Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the ap plicati on or u se o f any pr oduct o r circui t descri bed h erein. Cypr ess does not aut horize it s product s for use a s critical compo nent s in life-support systems whe re
a malfunction or failure may reasonab ly be expected to resu lt in significant injury t o the user. The inclusion of Cypress’ prod uct in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-15031 Rev. *C Revised February 29, 2008 Page 30 of 30
NoBL and No Bus Latency are trade marks of Cypress Semic onductor Corporation. Z BT is a trademark of Integra ted Device Technology, Inc. All products and company names mentioned in this
document may be the trademarks of their respective ho lders.
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