Cypress Semiconductor CY7C1471V33, CY7C1473V33, CY7C1475V33 Specification Sheet

CY7C1471V33 CY7C1473V33 CY7C1475V33

72-Mbit (2M x 36/4M x 18/1M x 72)

Flow-Through SRAM with NoBL™ Architecture

Features

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles

• Supports up to 133 MHz bus operations with zero wait states

• Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™ devices

• Internally self timed output buffer control to eliminate the need to use OE

• Registered inputs for flow through operation

• Byte Write capability

• 3.3V/2.5V IO supply (V

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

• Clock Enable (CEN) pin to enable clock and suspend operation

• Synchronous self timed writes

• Asynchronous Output Enable (OE)

• CY7C1471V33, CY7C1473V33 available in JEDEC-standard Pb-free 100-Pin TQFP, Pb-free and non-Pb-free 165-Ball FBGA package. CY7C1475V33 available in Pb-free and non-Pb-free 209-Ball FBGA package

• Three Chip Enables (CE expansion

• Automatic power down feature available using ZZ mode or CE deselect

• IEEE 1149.1 JTAG Boundary Scan compatible

• Burst Capability — linear or interleaved burst order

• Low standby power

)

DDQ

, CE2, CE3) for simple depth

1

Functional Description

The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are

3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN suspends operation and extends the previous clock cycle.Maximum access delay from the clock rise is 6.5 ns (133-MHz device).

Write operations are controlled by two or four Byte Write Select (BW

) and a Write Enable (WE) input. All writes are conducted

X

with on-chip synchronous self timed write circuitry.

Three synchronous Chip Enables (CE asynchronous Output Enable (OE selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

[1]

) signal, which when deasserted

, CE2, CE3) and an

1

) provide for easy bank

Selection Guide

Maximum Access Time 6.5 8.5 ns

Maximum Operating Current 305 275 mA

Maximum CMOS Standby Current 120 120 mA

Note

1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05288 Rev. *J Revised July 04, 2007

133 MHz 117 MHz Unit

[+] Feedback

Logic Block Diagram – CY7C1471V33 (2M x 36)

CY7C1471V33 CY7C1473V33 CY7C1475V33

ADDRESS REGISTER

A1 A0

ADV/LD

C

WRITE ADDRESS

REGISTER

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

SLEEP

CONTROL

D1 D0

BURST LOGIC

CLK

CEN

A0, A1, A

MODE

C

ADV/LD

BW

WE

CE1 CE2 CE3

ZZ

CE

A

B

C

D

OE

Logic Block Diagram – CY7C1473V33 (4M x 18)

A1'

Q1

A0'

Q0

O U

T P

D

U

A

T

T A

B U

S

F

T

F

E

R

S

I N G

E

DQs DQP DQP DQP DQP

A

B

C

D

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

REGISTER

S E

N

S

E

A

M

P

S

E

CLK

C

EN

A0, A1, A

MODE

C

ADV/LD

BW A

BW B

WE

OE CE1 CE2 CE3

ZZ

CE

ADDRESS REGISTER

READ LOGIC

A1

D1

A0

D0

ADV/LD

C

WRITE ADDRESS

REGISTER

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

SLEEP

CONTROL

BURST LOGIC

Q1 Q0

A1' A0'

WRITE

DRIVERS

MEMORY

ARRAY

REGISTER

INPUT

O U T

P S E

N

S E

A M

P S

E

D

U

A

T

T A

B

U

S

F

T

F

E

R

S

I N G

E

DQs DQP

DQP

A B

Document #: 38-05288 Rev. *J Page 2 of 32

[+] Feedback

Logic Block Diagram – CY7C1475V33 (1M x 72)

CY7C1471V33 CY7C1473V33 CY7C1475V33

CLK

CEN

A0, A1, A

MODE

C

ADV/LD

BW BW BW

BW BW

BW

WE

CE1 CE2 CE3

ZZ

ADDRESS

REGISTER 0

WRITE ADDRESS

REGISTER 1

a

b

c

d

e

f

g

h

OE

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

Sleep Control

A1

D1

A0

D0

ADV/LD

C

WRITE ADDRESS

REGISTER 2

BURST LOGIC

A1'

Q1

A0'

Q0

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

REGISTER 1

O U T P

S

U

E

T

N S

R

E

E G

A

I

M

S

P

T

S

E R

S

E

INPUT

REGISTER 0

O U T P

D

U

A

T

T A

B U

S

F

T

F

E

R

S

I N G

E

DQ s DQ Pa DQ Pb DQ Pc DQ Pd DQ Pe DQ Pf DQ Pg DQ Ph

Document #: 38-05288 Rev. *J Page 3 of 32

[+] Feedback

Pin Configurations

CY7C1471V33 CY7C1473V33 CY7C1475V33

100-Pin TQFP Pinout

BYTE C

BYTE D

DQP

DQ DQ

V

DDQ

V DQ DQ DQ DQ

V

DDQ

DQ DQ

V

V DQ DQ

V

DDQ

V DQ DQ DQ DQ

V

DDQ

DQ DQ

DQP

SS

NC

DD

NC

SS

1CE2

A

CE

A

1009998979695949392919089888786

1

C

2

C

3

C

4 5 6

C

7

C

8

C

9

C

10 11 12

C

13

C

14 15 16 17 18

D

19

D

20 21 22

D

23

D

24

D

25

D

26 27 28

D

29

D

30

D

C

BWDBW

BWBBWACE3VDDV

CY7C1471V33

SS

CLKWECEN

OE

A

ADV/LD

858483

A

82

81

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

DQP DQ DQ V

DDQ

V

SS

DQ DQ DQ DQ V

SS

V

DDQ

DQ DQ V

SS

NC V

DD

ZZ

DQ DQ V

DDQ

V

SS

DQ DQ DQ DQ V

SS

V

DDQ

DQ DQ DQP

B

BYTE B

B

A

BYTE A

A

31

323334

A

MODE

Document #: 38-05288 Rev. *J Page 4 of 32

353637383940414243444546474849

A

A1

A0

NC/288M

SS

V

NC/144M

DD

V

A

50

A

[+] Feedback

Pin Configurations (continued)

CY7C1471V33 CY7C1473V33 CY7C1475V33

100-Pin TQFP Pinout

BYTE B

V

DDQ

V

DQ DQ

V

DDQ

DQ DQ

V

V DQ DQ

V

DDQ

V DQ DQ

DQP

V

DDQ

NC NC NC

SS

NC NC

SS

NC

DD

NC

SS

NC

SS

NC NC NC

1CE2

A

100

A

999897

CE

NC

1 2 3 4 5 6 7 8

B

9

B

10 11 12

B

13

B

14 15 16 17 18

B

19

B

20 21 22

B

23

B

24

B

25 26 27 28 29 30

BBWA

NC

BW

9695949392919089888786

CE3VDDV

SS

CLKWECEN

OE

CY7C1473V33

A

ADV/LD

858483

A

82

81

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

A NC NC V

DDQ

V

SS

NC DQP DQ DQ V

SS

V

DDQ

DQ DQ V

SS

NC V

DD

ZZ

DQ DQ V

DDQ

V

SS

DQ DQ NC NC V

SS

V

DDQ

NC NC NC

A

BYTE A

A

31323334353637383940414243444546474849

A

MODE

Document #: 38-05288 Rev. *J Page 5 of 32

50

A

A1

A0

NC/288M

NC/144M

SS

DD

A

V

A

[+] Feedback

Pin Configurations (continued)

CY7C1471V33 CY7C1473V33 CY7C1475V33

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1471V33 (2M x 36)

A

B C D

E F G

H

J K L M N P

R

A

B C D

E F G

H

J K L M N P

R

234 5671

NC/576M

NC/1G

DQP

C

DQ

C

DQ

C

DQ

C

DQ

C

NC

DQ

D

DQ

D

DQ

D

DQ

D

DQP

D

NC/144M

MODE

NC

DQ

NC

DQ

NC

A

CE

CE2

V

DDQ

V

C

V

DDQ

NC

V

DDQ

A

D

A

BW

1

BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

BW

V

V V V

V

B

A

SS

C

D

NC

TDI

TMS

CY7C1473V33 (4M x 18)

234 5671

NC/576M

NC/1G

NC

NC V

NC

NC NC

DQ

B

DQ

B

DQ

B

DQ

B

DQP

B

NC/144M

MODE

A

NC

DQ

NC

A

CE

CE2

V

DDQ

V

B

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

BW

1

B

NC BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

NC CE

A

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

CE

CLK

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

A1

A0

CLK

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

A1

A0

891011

A

NC

NC DQP

B

A

DQ

ZZ

DQ

DQP

NC/288M

DQ

NC

DQ

NC

A

B

A

AA

SS

ADV/LD

OE

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

CEN

3

WE

V

V V

V

NC

TDO

TCK

V

A

DDQ

NC

DDQ

A

891011

A

NC

NC DQP

A

DQ

ZZ

NCV

NC

NC/288M

NC

NC NC

DQ

NC

A

AA

SS

ADV/LD

OE

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

CEN

3

WE

V

V V

V

NC

TDO

TCK

V

A

DDQ

NC

DDQ

A

Document #: 38-05288 Rev. *J Page 6 of 32

[+] Feedback

Pin Configurations (continued)

123456789 1110

CY7C1471V33 CY7C1473V33 CY7C1475V33

209-Ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1475V33 (1M × 72)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

DQg

DQPg

DQc

NC

DQh

DQPd

DQd

DQg

DQPc

DQc

NC

DQh

DQPh

DQd

AA A A

BWScBWS

BWS

V

SS

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

CLK

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

V

SS

NC/144M

AA

TMS

CE

2

g

BWS

NC/576M

V

NC

DDQ

V

DDQ

V

DDQ

d

NC/1G

SS

h

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

NC MODE

A

TDI TDO TCK

ADV/LD

NC

WE

CE

OE

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

DD

NC

CEN

NC

ZZ

V

DD

NC

A A NC/288M

A

AA

A1

A0

A

NC

1

NC

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

NC

A

SS

CE

3

BWS

b

BWSeBWS

V

NC

DDQ

V

DDQ

V

DDQ

NC

DDQ

V

DDQ

V

DDQ

NC

SS

V

DDQ

V

DDQ

V

DDQ

NC

DDQ

V

DDQ

V

DDQ

V

AA

SS

DQb

f

DQb

a

DQb

DQPf

DQf

NC

DQa

DQPa

DQe

DQb

DQPb

DQf

NC

DQa

DQPe

DQe

Document #: 38-05288 Rev. *J Page 7 of 32

[+] Feedback

Pin Definitions

Name IO Description

, A1, A Input-

A

0

BW BW BW BW

, BWB,

A

, BWD,

C

, BWF,

E

, BW

G

H

Synchronous

Input-

Synchronous

WE Input-

Synchronous

ADV/LD Input-

Synchronous

CLK Input-

Clock

CE

OE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

CEN Input-

Synchronous

ZZ Input-

Asynchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. A

are fed to the two-bit burst counter.

[1:0]

Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK.

Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence.

Advance/Load Input. Advances the on-chip address counter or loads a new address. When HIGH (and CEN

is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should must driven LOW to load a new address.

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE3 to select or deselect the device.

2

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE3 to select or deselect the device.

1

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE2 to select or deselect the device.

1

Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block inside the device to control the direction of the IO pins. When LOW, the IO pins are enabled to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE

is masked during the data portion of a write sequence, during the first

clock when emerging from a deselected state, when the device is deselected.

Clock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, use CEN

to extend the previous cycle when required.

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull down.

CY7C1471V33 CY7C1473V33 CY7C1475V33

DQ

s

IO-

Synchronous

Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous read cycle. The direction of the pins is controlled by OE pins behave as outputs. When HIGH, DQ outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE

DQP

X

IO-

Synchronous

Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During write sequences, DQP

MODE Input Strap Pin Mode Input. Selects the burst order of the device.

When tied to Gnd selects linear burst sequence. When tied to V interleaved burst sequence.

V

DD

DDQ

SS

Power Supply Power supply inputs to the core of the device.

IO Power Supply Power supply for the IO circuitry.

Ground Ground for the device.

Document #: 38-05288 Rev. *J Page 8 of 32

and DQPX are placed in a tri-state condition.The

s

.

is controlled by BWX correspondingly.

X

. When OE is asserted LOW, the

clock rise of the

or left floating selects

DD

[+] Feedback

Pin Definitions (continued)

Name IO Description

TDO JTAG serial

output

Synchronous

TDI JTAG serial input

Synchronous

TMS JTAG serial input

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not used, this pin must be left unconnected. This pin is not available on TQFP packages.

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used, this pin can be left floating or connected to V pin is not available on TQFP packages.

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used, this pin can be disconnected or connected to V TQFP packages.

CY7C1471V33 CY7C1473V33 CY7C1475V33

through a pull up resistor. This

DD

. This pin is not available on

DD

TCK JTAG

-Clock

Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be connected to V

. This pin is not available on TQFP packages.

SS

NC - No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address

expansion pins and are not internally connected to the die.

Functional Overview

The CY7C1471V33, CY7C1473V33, and CY7C1475V33 are synchronous flow through burst SRAMs designed specifically to eliminate wait states during write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (t device).

Accesses can be initiated by asserting all three Chip Enables (CE

, CE2, CE3) active at the rising edge of the clock. If (CEN)

1

is active LOW and ADV/LD presented to the device is latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE

). Byte Write Select (BWX) can be used to conduct

Byte Write operations.

Write operations are qualified by the Write Enable (WE writes are simplified with on-chip synchronous self timed write circuitry.

Three synchronous Chip Enables (CE asynchronous Output Enable (OE

). If CEN is HIGH, the clock

) is 6.5 ns (133-MHz

CDV

is asserted LOW, the address

). All

, CE2, CE3) and an

1

) simplify depth expansion.

the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE

is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW to drive out the requested data. On the subsequent clock, another operation (read/write/deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, output is be tri-stated immediately.

Burst Read Accesses

The CY7C1471V33, CY7C1473V33 and CY7C1475V33 have an on-chip burst counter that enables the user to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD

must be driven LOW to load a new address into the SRAM, as described in the Single Read Access section. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and wraps around when incremented sufficiently. A HIGH input on ADV/LD

increments the internal

burst counter regardless of the state of chip enable inputs or

. WE is latched at the beginning of a burst cycle. Therefore,

WE the type of access (read or write) is maintained throughout the burst sequence.

All operations (reads, writes, and deselects) are pipelined. ADV/LD

must be driven LOW after the device is deselected to

load a new address for the next operation.

Single Read Accesses

A read access is initiated when these conditions are satisfied at clock rise:

•CEN

is asserted LOW

, CE2, and CE3 are ALL asserted active

•CE

1

is deasserted HIGH

•WE

•ADV/LD

is asserted LOW.

The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic. The control logic determines that a read access

Single Write Accesses

Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN and CE LOW. The address presented to the address bus is loaded into

are ALL asserted active, and (3) WE is asserted

3

is asserted LOW, (2) CE1, CE2,

the Address Register. The Write signals are latched into the Control Logic block. The data lines are automatically tri-stated regardless of the state of the OE external logic to present the data on DQs and DQP

input signal. This allows the

.

X

On the next clock rise the data presented to DQs and DQP (or a subset for Byte Write operations, see “Truth Table for

Read/Write” on page 12 for details) inputs is latched into the

device and the write is complete. Additional accesses (read/write/deselect) can be initiated on this cycle.

is in progress and allows the requested data to propagate to

X

Document #: 38-05288 Rev. *J Page 9 of 32

[+] Feedback

CY7C1471V33 CY7C1473V33 CY7C1475V33

The data written during the write operation is controlled by

signals. The CY7C1471V33, CY7C1473V33, and

BW

X

CY7C1475V33 provides Byte Write capability that is described in the “Truth Table for Read/Write” on page 12. The input WE with the selected BWX input selectively writes to only the desired bytes. Bytes not selected during a Byte Write operation remain unaltered. A synchronous self timed write mechanism has been provided to simplify the write operations. Byte write capability is included to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations.

Because the CY7C1471V33, CY7C1473V33, and CY7C1475V33 are common IO devices, data must not be driven into the device while the outputs are active. The Output Enable (OE to the DQs and DQP drivers. As a safety precaution, DQs and DQP cally tri-stated during the data portion of a write cycle, regardless of the state of OE

) can be deasserted HIGH before presenting data

inputs. Doing so tri-states the output

X

are automati-

X

.

Burst Write Accesses

The CY7C1471V33, CY7C1473V33, and CY7C1475V33 have an on-chip burst counter that enables the user to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD

must be driven LOW to load the initial address, as described in the Single Write Access section. When ADV/LD is dr iven HIG H on the subsequent clock rise, the Chip Enables (CE CE

) and WE inputs are ignored and the burst counter is incre-

3

mented. The correct BW of the burst write to write the correct bytes of data.

inputs must be driven in each cycle

X

, CE2, and

1

Interleaved Burst Address Table (MODE = Floating or V

First

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Second

Address

A1: A0

DD

)

Third

Address

A1: A0

Linear Burst Address Table (MODE = GND)

First

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

Fourth

Address

A1: A0

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CE for the duration of t

, CE2, and CE3, must remain inactive

1

after the ZZ input returns LOW.

ZZREC

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Sleep mode standby current ZZ > VDD – 0.2V 120 mA

Device operation to ZZ ZZ > VDD – 0.2V 2t

ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ active to sleep current This parameter is sampled 2t

CYC

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

ns

Document #: 38-05288 Rev. *J Page 10 of 32

[+] Feedback

CY7C1471V33 CY7C1473V33 CY7C1475V33

Truth Table

The truth table for CY7C1471V33, CY7C1473V33, CY7C1475V33 follows.

Operation

Address

Used

CE1CE

ZZ ADV/LD WE BWXOE CEN CLK DQ

CE

2

3

Deselect Cycle None H X X L L X X X L L->H Tri-State

Deselect Cycle None X X H L L X X X L L->H Tri-State

Deselect Cycle None X L X L L X X X L L->H Tri-State

Continue Deselect Cycle None X X X L H X X X L L->H Tri-State

Read Cycle

External L H L L L H X L L L->H Data Out (Q)

(Begin Burst)

Read Cycle

Next X X X L H X X L L L->H Data Out (Q)

(Continue Burst)

NOP/Dummy Read

External L H L L L H X H L L->H Tri-State

(Begin Burst)

Dummy Read

Next X X X L H X X H L L->H Tri-State

(Continue Burst)

Write Cycle

External L H L L L L L X L L->H Data In (D)

(Begin Burst)

Write Cycle

Next X X X L H X L X L L->H Data In (D)

(Continue Burst)

NOP/Write Abort

None L H L L L L H X L L->H Tri-State

(Begin Burst)

Write Abort

Next X X X L H X H X L L->H Tri-State

(Continue Burst)

Ignore Clock Edge (Stall) Current X X X L X X X X H L->H -

Sleep Mode None X X X H X X X X X X Tri-State

[2, 3, 4, 5, 6, 7, 8]

Notes

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW Selects are asserted, see “Truth Table for Read/Write” on page 12 for details.

3. Write is defined by BW

4. When a Write cycle is detected, all IOs are tri-stated, even during Byte Writes.

5. The DQs and DQP

= H, inserts wait states.

6. CEN

7. Device powers up deselected with the IOs in a tri-state condition, regardless of OE

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE

8. OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.

, and WE. See “Truth Table for Read/Write” on page 12.

X

pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

X

Document #: 38-05288 Rev. *J Page 11 of 32

= L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write

X

.

[+] Feedback

Truth Table for Read/Write

The read-write truth table for CY7C1471V33 follows.

CY7C1471V33 CY7C1473V33 CY7C1475V33

[2, 3, 9]

Function

WE

BW

A

BW

B

BW

C

BW

D

Read H X X X X

Write No bytes written LHHHH

Write Byte A – (DQ

Write Byte B – (DQ

Write Byte C – (DQ

Write Byte D – (DQ

and DQPA) L LHHH

A

and DQPB)LHLHH

B

and DQPC)LHHLH

C

and DQPD) L HHH L

D

Write All Bytes L L L L L

Truth Table for Read/Write

The read-write truth table for CY7C1473V33 follows.

Function

Read H X X

Write – No Bytes Written L H H

Write Byte a – (DQ

Write Byte b – (DQ

and DQPa)LHL

a

and DQPb)LLH

b

Write Both Bytes L L L

[2, 3, 9]

WE

BW

b

BW

a

Truth Table for Read/Write

The read-write truth table for CY7C1475V33 follows.

Function

Read HX

Write – No Bytes Written L H

Write Byte X − (DQ

and DQP

x

x)

Write All Bytes L All BW

[2, 3, 9]

WE

BW

x

LL

= L

Note

9. Table only lists a partial listing of the byte write combinations. Any combination of BW

Document #: 38-05288 Rev. *J Page 12 of 32

is valid. Appropriate write is based on which byte write is active.

X

[+] Feedback

CY7C1471V33 CY7C1473V33 CY7C1475V33

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1471V33, CY7C1473V33, and CY7C1475V33 incorporate a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard

1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V IO logic levels.

The CY7C1471V33, CY7C1473V33, and CY7C1475V33 contain a TAP controller, instruction register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (V

) to prevent clocking of the device. TDI and TMS are inter-

SS

nally pulled up and may be unconnected. They may alternately be connected to V left unconnected. During power up, the device comes up in a

through a pull up resistor. TDO must be

DD

reset state, which does not interfere with the operation of the device.

TAP Controller State Diagram

TEST-LOGIC

1

RESET

0

RUN-TEST/

IDLE

1

SELE CT

DR-SCAN

1 1

CAPTU RE-DR

SHIFT -DR

EXIT1-DR

PAU SE-DR

0 0

EXIT2-DR

UPDATE-DR

1 0

1

0

0 0

1

1 1

0 0

0

1

IR-SCAN

CAPTU RE-IR

SHIFT -IR

EXIT1-IR

PAU SE-IR

EXIT2-IR

UPDATE-IR

1

SELE CT

1

0

1

0

1

0

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.)

TAP Controller Block Diagram

0

Bypass Register

012

TDI TDO

TCK

TMS

Sele ction

Circuitry

Instruction Register

Identication Register

Boundary Scan Register

TAP CONTROLLER

Sele ction Circuitry

012293031 ...

012..x ...

The 0/1 next to each state represents the value of TMS at the rising edge of TCK.

Document #: 38-05288 Rev. *J Page 13 of 32

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (V rising edges of TCK. This RESET does not affect the operation

) for five

DD

of the SRAM and may be performed while the SRAM is operating.

During power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

[+] Feedback

CY7C1471V33 CY7C1473V33 CY7C1475V33

TAP R e gisters

Registers are connected between the TDI and TDO balls and enable data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.

nstruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the “TAP Controller Block

Diagram” on page 13. During power up, the instruction register

is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.

When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to enable fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (V

) when the BYPASS instruction is executed.

SS

Boundary Scan Register

The boundary scan register is connected to all the input and bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring.

The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in “Identification Register Defini-

tions” on page 18.

TAP Instruction Set

Overview

Eight different instructions are possible with the three-bit instruction register. All combinations are listed in “Identification

Codes” on page 18. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions are described in detail below.

The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented.

The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the IO ring when these instructions are executed.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction.

When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register during power up or whenever the TAP controller is in a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant.

When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a

Document #: 38-05288 Rev. *J Page 14 of 32

[+] Feedback

CY7C1471V33 CY7C1473V33 CY7C1475V33

signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible.

To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (t

plus tCH).

CS

The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls.

TAP Ti ming

123456

Test Clock

(TCK)

t

Test Mode Select

(TMS)

t

TMSS

TDIS

t

TH

t

TMSH

t

TDIH

Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

t

TL

t

CYC

Test Data-In

(TDI)

Test Data-Out

(TDO)

t

TDOX

DON’T CARE UNDEFINED

TDOV

Document #: 38-05288 Rev. *J Page 15 of 32

[+] Feedback

CY7C1471V33 CY7C1473V33 CY7C1475V33

TAP AC Switching Characteristics

Over the Operating Range

Parameter Description Min Max Unit

Clock

t

TCYC

t

TF

t

TH

t

TL

TCK Clock Cycle Time 50 ns

TCK Clock Frequency 20 MHz

TCK Clock HIGH time 20 ns

TCK Clock LOW time 20 ns

Output Times

t

TDOV

t

TDOX

TCK Clock LOW to TDO Valid 5 ns

TCK Clock LOW to TDO Invalid 0 ns

Setup Times

t

TMSS

t

TDIS

t

CS

TMS Setup to TCK Clock Rise 5 ns

TDI Setup to TCK Clock Rise 5 ns

Capture Setup to TCK Rise 5 ns

Hold Times

t

TMSH

t

TDIH

t

CH

TMS Hold after TCK Clock Rise 5 ns

TDI Hold after Clock Rise 5 ns

Capture Hold after Clock Rise 5 ns

[10, 11]

Notes

and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

10.t

CS

11.Test conditions are specified using the load in TAP AC Test Conditions. t

Document #: 38-05288 Rev. *J Page 16 of 32

R/tF

= 1 ns.

[+] Feedback

CY7C1471V33

TDO

1.25V

20pF

Z = 50Ω

O

50Ω

CY7C1473V33 CY7C1475V33

3.3V TAP AC Test Conditions

Input pulse levels ................................................ VSS to 3.3V

Input rise and fall times................................................... 1 ns

Input timing reference levels ...........................................1.5V

Output reference levels...................................................1.5V

Test load termination supply voltage...............................1.5V

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Test Conditions

Input pulse levels.................................................VSS to 2.5V

Input rise and fall time .....................................................1 ns

Input timing reference levels......................................... 1.25V

Output reference levels ................................................1.25V

Test load termination supply voltage ............................ 1.25V

2.5V TAP AC Output Load Equivalent

1.5V

50Ω

TDO

Z = 50Ω

O

20pF

TAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)

Parameter Description Test Conditions Min Max Unit

V

OH1

OH2

OL1

Output HIGH Voltage IOH = –4.0 mA, V

I

= –1.0 mA, V

OH

Output HIGH Voltage IOH = –100 µA V

Output LOW Voltage IOL = 8.0 mA V

IOL = 1.0 mA V

V

OL2

V

IH

V

IL

I

X

Output LOW Voltage IOL = 100 µA V

Input HIGH Voltage V

Input LOW Voltage V

Input Load Current GND < VIN < V

[12]

= 3.3V 2.4 V

DDQ

= 2.5V 2.0 V

DDQ

= 3.3V 2.9 V

DDQ

V

= 2.5V 2.1 V

DDQ

= 3.3V 0.4 V

DDQ

= 2.5V 0.4 V

DDQ

= 3.3V 0.2 V

DDQ

V

= 2.5V 0.2 V

DDQ

= 3.3V 2.0 VDD + 0.3 V

DDQ

V

= 2.5V 1.7 VDD + 0.3 V

DDQ

= 3.3V –0.3 0.8 V

DDQ

V

= 2.5V –0.3 0.7 V

DDQ

–5 5 µA

Note

12. All voltages refer to V

Document #: 38-05288 Rev. *J Page 17 of 32

(GND).

SS

[+] Feedback

Identification Register Definitions

CY7C1471V33 CY7C1473V33 CY7C1475V33

Instruction Field

Revision Number (31:29) 000 000 000 Describes the version number

Device Depth (28:24)

Architecture/Memory Type(23:18)

Bus Width/Density(17:12) 100100 010100 110100 Defines width and density

Cypress JEDEC ID Code (11:1) 00000110100 00000110100 00000110100 Enables unique identification of SRAM

ID Register Presence Indicator (0) 1 1 1 Indicates the presence of an ID

[13]

CY7C1471V33

(2Mx36)

01011 01011 01011 Reserved for internal use

001001 001001 001001 Defines memory type and architecture

CY7C1473V33

(4Mx18)

CY7C1475V33

(1Mx72)

Description

vendor

register

Scan Register Sizes

Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72)

Instruction 3 3 3

Bypass 1 1 1

ID 32 32 32

Boundary Scan Order – 165FBGA 71 52 -

Boundary Scan Order – 209BGA - - 110

Identification Codes

Instruction Code Description

EXTEST 000 Captures IO ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

SAMPLE Z 010 Captures IO ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures IO ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

Note

13. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.

Document #: 38-05288 Rev. *J Page 18 of 32

[+] Feedback

CY7C1471V33 CY7C1473V33 CY7C1475V33

Boundary Scan Exit Order (2M x 36)

Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID

1C1 21 R3 41 J11 61B7

2 D1 22 P2 42 K10 62 B6

3 E1 23 R4 43 J10 63 A6

4D2 24 P6 44H11 64B5

5E2 25 R6 45G11 65A5

6F1 26 R8 46F11 66A4

7G1 27 P3 47E11 67B4

8 F2 28 P4 48 D10 68 B3

9G2 29 P8 49D11 69A3

10 J1 30 P9 50 C11 70 A2

11 K1 31 P10 51 G10 71 B2

12 L1 32 R9 52 F10

13 J2 33 R10 53 E10

14 M1 34 R11 54 A9

15 N1 35 N11 55 B9

16 K2 36 M11 56 A10

17 L2 37 L11 57 B10

18 M2 38 M10 58 A8

19 R1 39 L10 59 B8

20 R2 40 K11 60 A7

Boundary Scan Exit Order (4M x 18)

Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID

1 D2 14 R4 27 L10 40 B10

2E2 15 P6 28K10 41A8

3F2 16 R6 29J10 42B8

4G2 17 R8 30H11 43A7

5J1 18 P3 31G11 44B7

6K1 19 P4 32F11 45B6

7L1 20 P8 33E11 46A6

8M1 21 P9 34D11 47B5

9 N1 22 P10 35 C11 48 A4

10 R1 23 R9 36 A11 49 B3

11 R2 24 R10 37 A9 50 A3

12 R3 25 R11 38 B9 51 A2

13 P2 26 M10 39 A10 52 B2

Document #: 38-05288 Rev. *J Page 19 of 32

[+] Feedback

CY7C1471V33 CY7C1473V33 CY7C1475V33

Boundary Scan Exit Order (1M x 72)

Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID

1 A1 29 T1 57 U10 85 B11

2A2 30T2 58T11 86B10

3B1 31U1 59T10 87A11

4B2 32U2 60R11 88A10

5 C1 33 V1 61 R10 89 A7

6C2 34V2 62P11 90A5

7 D1 35 W1 63 P10 91 A9

8D2 36W2 64N11 92U8

9 E1 37 T6 65 N10 93 A6

10 E2 38 V3 66 M11 94 D6

11 F1 39 V4 67 M10 95 K6

12 F2 40 U4 68 L11 96 B6

13 G1 41 W5 69 L10 97 K3

14 G2 42 V6 70 P6 98 A8

15 H1 43 W6 71 J11 99 B4

16 H2 44 V5 72 J10 100 B3

17 J1 45 U5 73 H11 101 C3

18 J2 46 U6 74 H10 102 C4

19 L1 47 W7 75 G11 103 C8

20 L2 48 V7 76 G10 104 C9

21 M1 49 U7 77 F11 105 B9

22 M2 50 V8 78 F10 106 B8

23 N1 51 V9 79 E10 107 A4

24 N2 52 W11 80 E11 108 C6

25 P1 53 W10 81 D11 109 B7

26 P2 54 V11 82 D10 110 A3

27 R2 55 V10 83 C11

28 R1 56 U11 84 C10

Document #: 38-05288 Rev. *J Page 20 of 32

[+] Feedback

CY7C1471V33 CY7C1473V33 CY7C1475V33

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied............................................. –55°C to +125°C

Supply Voltage on V

DC Voltage Applied to Outputs

in Tri-State........................................... –0.5V to V

Relative to GND........ –0.5V to +4.6V

DD

Relative to GND ...... –0.5V to +V

DDQ

DD

+ 0.5V

DC Input Voltage ................................... –0.5V to V

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage........................................... >2001V

(MIL-STD-883, Method 3015)

Latch Up Current .................................................... >200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5% Industrial –40°C to +85°C

Ambient

Tem per atu re

V

DD

+ 0.5V

DD

V

to V

DDQ

DD

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Max Unit

V

I

DD

DDQ

OH

OL

IH

IL

X

Power Supply Voltage 3.135 3.6 V

IO Supply Voltage For 3.3V IO 3.135 V

Output HIGH Voltage For 3.3V IO, I

Output LOW Voltage For 3.3V IO, I

Input HIGH Voltage

Input LOW Voltage

Input Leakage Current except ZZ and MODE

Input Current of MODE Input = V

Input Current of ZZ Input = V

I

OZ

I

DD

I

SB1

Output Leakage Current GND ≤ VI ≤ V

VDD Operating Supply Current

Automatic CE Power Down Current—TTL Inputs

I

SB2

Automatic CE Power Down Current—CMOS Inputs

I

SB3

Automatic CE Power Down Current—CMOS Inputs

I

SB4

Automatic CE Power Down Current—TTL Inputs

Notes

14. Overshoot: V

15. T

Power-up

(AC) < VDD +1.5V (pulse width less than t

IH

: assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and V

[14, 15]

For 2.5V IO 2.375 2.625 V

= –4.0 mA 2.4 V

OH

For 2.5V IO, I

[14]

For 3.3V IO 2.0 VDD + 0.3V V

= –1.0 mA 2.0 V

OH

= 8.0 mA 0.4 V

OL

= 1.0 mA 0.4 V

OL

For 2.5V IO 1.7 VDD + 0.3V V

[14]

For 3.3V IO –0.3 0.8 V

For 2.5V IO –0.3 0.7 V

GND ≤ VI ≤ V

Input = V

V

= Max., I

DD

f = f

MAX

V

= Max, Device Deselected,

DD

≥ VIH or VIN ≤ V

V

IN

f = f

MAX

V

= Max, Device Deselected,

DD

V

≤ 0.3V or VIN > VDD – 0.3V,

IN

f = 0, inputs static

V

= Max, Device Deselected, or

DD

V

≤ 0.3V or VIN > V

IN

f = f

MAX

V

= Max, Device Deselected,

DD

V

≥ VDD – 0.3V or VIN ≤

IN

f = 0, inputs static

DDQ

SS

DD

SS

DD

Output Disabled –5 5 µA

DD,

= 0 mA,

OUT

= 1/t

CYC

, inputs switching

/2). Undershoot: VIL(AC) > –2V (pulse width less than t

CYC

IL

DDQ

– 0.3V

,

0.3V

7.5 ns cycle, 133 MHz 305 mA

10 ns cycle, 117 MHz 275 mA

7.5 ns cycle, 133 MHz 200 mA

10 ns cycle, 117 MHz 200 mA

All speeds 120 mA

7.5 ns cycle, 133 MHz 200 mA

10 ns cycle, 117 MHz 200 mA

All Speeds 165 mA

CYC

< VDD.

DDQ

–5 5 µA

–30 µA

–5 µA

/2).

DD

5 µA

30 µA

V

Document #: 38-05288 Rev. *J Page 21 of 32

[+] Feedback

Capacitance

Tested initially and after any design or process change that may affect these parameters.

CY7C1471V33 CY7C1473V33 CY7C1475V33

Parameter Description Test Conditions

C

ADDRESS

C

DATA

C

Control Input Capacitance 8 8 8 pF

CTRL

C

CLK

C

IO

Address Input Capacitance TA = 25°C, f = 1 MHz,

V

= 3.3V

Data Input Capacitance 5 5 5 pF

V

DD

DDQ

= 2.5V

Clock Input Capacitance 6 6 6 pF

Input/Output Capacitance 5 5 5 pF

100 TQFP

Package

6 6 6 pF

165 FBGA

Package

209 BGA

Package

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions

Θ

JA

Θ

JC

Thermal Resistance (Junction to Ambient)

Thermal Resistance (Junction to Case)

Test conditions follow standard test methods and procedures for measuring thermal impedance, according to

100 TQFP

Max

24.63 16.3 15.2 °C/W

2.28 2.1 1.7 °C/W

165 FBGA

Max

EIA/JESD51.

AC Test Loads and Waveforms

209 FBGA

Max

Unit

3.3V IO Test Load

OUTPUT

Z

2.5V IO Test Load

OUTPUT

Z

= 50Ω

0

= 50Ω

0

VL= 1.5V

(a)

= 1.25V

V

L

(a)

R

= 50Ω

L

= 50Ω

L

3.3V

OUTPUT

INCLUDING

2.5V

OUTPUT

INCLUDING

5pF

JIG AND

SCOPE

5pF

JIG AND

SCOPE

R = 317Ω

R = 351Ω

(b)

R = 1667Ω

R = 1538Ω

(b)

V

GND

V

DDQ

GND

DDQ

≤ 1 ns

ALL INPUT PULSES

10%

90%

ALL INPUT PULSES

90%

10%

≤ 1 ns

(c)

90%

10%

≤ 1 ns

(c)

Document #: 38-05288 Rev. *J Page 22 of 32

[+] Feedback

Switching Characteristics

CY7C1471V33 CY7C1473V33 CY7C1475V33

Over the Operating Range. Unless otherwise noted in the following table, timing reference level is 1.5V when V is 1.25V when V

Parameter

POWER

[16]

t

= 2.5V. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 22 unless otherwise noted.

DDQ

Description

133 MHz 117 MHz

Min Max Min Max

1 1 ms

Clock

t

CYC

t

CH

t

CL

Clock Cycle Time 7.5 10 ns

Clock HIGH 2.5 3.0 ns

Clock LOW 2.5 3.0 ns

Output Times

t

CDV

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Data Output Valid After CLK Rise 6.5 8.5 ns

Data Output Hold After CLK Rise 2.5 2.5 ns

Clock to Low-Z

Clock to High-Z

[17, 18, 19]

3.0 3.0 ns

3.8 4.5 ns

OE LOW to Output Valid 3.0 3.8 ns

OE LOW to Output Low-Z

OE HIGH to Output High-Z

[17, 18, 19]

0 0 ns

3.0 4.0 ns

Setup Times

t

AS

t

ALS

t

WES

t

CENS

t

DS

t

CES

Address Setup Before CLK Rise 1.5 1.5 ns

ADV/LD Setup Before CLK Rise 1.5 1.5 ns

WE, BWX Setup Before CLK Rise 1.5 1.5 ns

Setup Before CLK Rise

CEN

1.5 1.5 ns

Data Input Setup Before CLK Rise 1.5 1.5 ns

Chip Enable Setup Before CLK Rise 1.5 1.5 ns

Hold Times

t

AH

t

ALH

t

WEH

t

CENH

t

DH

t

CEH

Address Hold After CLK Rise 0.5 0.5 ns

ADV/LD Hold After CLK Rise 0.5 0.5 ns

WE, BWX Hold After CLK Rise 0.5 0.5 ns

CEN Hold After CLK Rise 0.5 0.5 ns

Data Input Hold After CLK Rise 0.5 0.5 ns

Chip Enable Hold After CLK Rise 0.5 0.5 ns

= 3.3V and

DDQ

Unit

Notes

16. This part has an internal voltage regulator; t can be initiated.

, t

17. t

CHZ

from steady-state voltage.

18. At any supplied voltage and temperature, t data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z before Low-Z under the same system conditions.

19. This parameter is sampled and not 100% tested.

CLZ,tOELZ

, and t

are specified with AC test conditions shown in part (b) of“AC Test Loads and Waveforms” on page 22. Transition is measured ±200 mV

OEHZ

POWER

OEHZ

Document #: 38-05288 Rev. *J Page 23 of 32

is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation

is less than t

OELZ

and t

is less than t

CHZ

to eliminate bus contention between SRAMs when sharing the same

CLZ

[+] Feedback

Switching Waveforms

Figure 1 shows read-write timing waveform.

CY7C1471V33 CY7C1473V33 CY7C1475V33

[20, 21, 22]

Figure 1. Read/Write Timing

CLK

CEN

CE

ADV/LD

WE

BWX

ADDRESS

DQ

123456789

t

CENS

CENH

t

CES

CEH

A1 A2

t

AS

AH

t

CYC

t

CL

CH

A3

t

CDV

t

CLZ

D(A1) D(A2) Q(A4)Q(A3)

D(A2+1)

A4

t

DOH

A5 A6 A7

t

OEV

t

Q(A4+1)

CHZ

D(A5)

10

D(A7)Q(A6)

t

READ

Q(A4)

OEHZ

Q(A4+1)

BURST

READ

t

OELZ

WRITE

D(A5)

t

DOH

READ Q(A6)

OE

COMMAND

WRITE

D(A1)

t

DS

WRITE

D(A2)

t

DH

BURST WRITE

D(A2+1)

READ

Q(A3)

DON’T CARE UNDEFINED

Notes

For this waveform ZZ is tied LOW.

20.

21. When CE

22. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH.

WRITE

D(A7)

DESELECT

Document #: 38-05288 Rev. *J Page 24 of 32

[+] Feedback

Switching Waveforms (continued)

Figure 2 shows NOP, STALL and DESELECT Cycles waveform.

Figure 2. NOP, STALL and DESELECT Cycles

CY7C1471V33 CY7C1473V33 CY7C1475V33

[20, 21, 23]

CLK

CEN

CE

ADV/LD

WE

[A:D]

BW

ADDRESS

DQ

COMMAND

123

A1 A2

456 78910

A3 A4

Q(A2)D(A1) Q(A3)

READ Q(A3)

D(A1)

READ Q(A2)

STALL NOP READ

WRITE

D(A4)

A5

t

CHZ

D(A4)

STALLWRITE

Q(A5)

t

DOH

DESELECT CONTINUE

DESELECT

Note

23. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN

Document #: 38-05288 Rev. *J Page 25 of 32

DON’T CARE UNDEFINED

being used to create a pause. A write is not performed during this cycle.

[+] Feedback

Switching Waveforms (continued)

Figure 3 shows ZZ Mode timing waveform.

CLK

t

ZZ

[24, 25]

Figure 3. ZZ Mode Timing

t

ZZRE C

CY7C1471V33 CY7C1473V33 CY7C1475V33

I

SUPPLY

ALL INPUTS

(except ZZ)

Outputs (Q)

ZZ

t

ZZI

I

DDZZ

High-Z

t

RZZI

DESELECT or READ Only

DON’T CARE

Notes

24. Device must be deselected when entering ZZ mode. See “Truth Table” on page 11 for all possible signal conditions to deselect the device.

25. DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05288 Rev. *J Page 26 of 32

[+] Feedback

CY7C1471V33 CY7C1473V33 CY7C1475V33

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code

133 CY7C1471V33-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1473V33-133AXC

CY7C1471V33-133BZC 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1473V33-133BZC

CY7C1471V33-133BZXC 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1473V33-133BZXC

CY7C1475V33-133BGC 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1475V33-133BGXC 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free

CY7C1471V33-133AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial

CY7C1473V33-133AXI

CY7C1471V33-133BZI 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1473V33-133BZI

CY7C1471V33-133BZXI 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1473V33-133BZXI

CY7C1475V33-133BGI 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1475V33-133BGXI 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free

117 CY7C1471V33-117AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1473V33-117AXC

CY7C1471V33-117BZC 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1473V33-117BZC

CY7C1471V33-117BZXC 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1473V33-117BZXC

CY7C1475V33-117BGC 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1475V33-117BGXC 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free

CY7C1471V33-117AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial

CY7C1473V33-117AXI

CY7C1471V33-117BZI 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)

CY7C1473V33-117BZI

CY7C1471V33-117BZXI 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1473V33-117BZXI

CY7C1475V33-117BGI 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)

CY7C1475V33-117BGXI 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free

Package Diagram

Part and Package Type

Operating

Range

Document #: 38-05288 Rev. *J Page 27 of 32

[+] Feedback

Package Diagrams

Figure 4. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050

16.00±0.20

14.00±0.10

20.00±0.10

22.00±0.20

100

1

30

81

80

0.30±0.08

0.65 TYP.

51

0513

12°±1°

(8X)

CY7C1471V33 CY7C1473V33 CY7C1475V33

1.40±0.05

SEE DETAIL

0.20 MAX.

A

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

0° MIN.

0.20 MIN.

R 0.08 MIN.

0.20 MAX.

DETAIL

1.60 MAX.

STAND-OFF

0.05 MIN.

0.15 MAX.

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

3. DIMENSIONS IN MILLIMETERS

SEATING PLANE

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

A

0.10

51-85050-*B

Document #: 38-05288 Rev. *J Page 28 of 32

[+] Feedback

Package Diagrams (continued)

CY7C1471V33 CY7C1473V33 CY7C1475V33

Figure 5. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165

1.00

PIN 1 CORNER

1

2345678910

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

BOTTOM VIEW

TOP VIEW

PIN 1 CORNER

1110986754321

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

+0.05

0.25 C

0.53±0.05

0.35

-0.10

0.15 C

17.00±0.10

A

1.00

14.00

7.00

B

0.15(4X)

11

5.00

Ø0.05 M C

Ø0.25 M C A B

Ø0.45±0.05(165X)

10.00

15.00±0.10

0.36

SEATING PLANE

C

1.40 MAX.

51-85165-*A

Document #: 38-05288 Rev. *J Page 29 of 32

[+] Feedback

Package Diagrams (continued)

Figure 6. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167

CY7C1471V33 CY7C1473V33 CY7C1475V33

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05288 Rev. *J Page 30 of 32

© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

51-85167-**

[+] Feedback

CY7C1471V33 CY7C1473V33 CY7C1475V33

Document History Page

Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05288

REV. ECN NO.

** 114675 08/06/02 PKS New Data Sheet

*A 121521 02/07/03 CJM Updated features for package offering

*B 223721 See ECN NJY Changed timing diagrams

*C 235012 See ECN RYQ Minor Change: The data sheets do not match on the spec system and

*D 243572 See ECN NJY Changed ball H2 from V

*E 299511 See ECN SYT Removed 117-MHz Speed Bin

*F 320197 See ECN PCI Corrected part number typos in the logic block diagram on page# 2

*G 331513 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as

*H 416221 See ECN RXU Converted from Preliminary to Final

Issue

Date

Orig. of Change Description of Change

Updated ordering information Changed Advanced Information to Preliminary

Changed logic block diagrams Modified Functional Description Modified “Functional Overview” section Added boundary scan order for all packages Included thermal numbers and capacitance values for all packages Removed 150-MHz speed grade offering Included ISB and IDD values Changed package outline for 165FBGA package and 209-Ball BGA package Removed 119-BGA package offering

external web

to NC in the 165-Ball FBGA package in page 6

Modified capacitance values on page 21

Changed Θ TQFP Package on Page # 21

from 16.8 to 24.63 °C/W and Θ

JA

DD

from 3.3 to 2.28 °C/W for 100

JC

Added Pb-free information for 100-Pin TQFP, 165 FBGA and 209 BGA Packages Added comment of ‘Pb-free BG packages availability’ below the Ordering Information

per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Added Industrial Operating Range Modified V Updated Ordering Information Table

, VOH Test Conditions

OL

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed 100MHz Speed bin & Added 117MHz Speed bin Changed the description of I Current on page# 19 Changed the I to –30 µA and 5 µA Changed the I to –5 µA and 30 µA Changed VIH < V Replaced Package Name column with Package Diagram in the Ordering

current values of MODE on page # 19 from –5 µA and 30 µA

X

current values of ZZ on page # 19 from –30 µA and 5 µA

X

to VIH < V

DD

from Input Load Current to Input Leakage

X

on page # 19

DD

Information table Updated the Ordering Information Table

Document #: 38-05288 Rev. *J Page 31 of 32

[+] Feedback

CY7C1471V33 CY7C1473V33 CY7C1475V33

Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05288

REV. ECN NO.

*I 472335 See ECN VKN Corrected the typo in the pin configuration for 209-Ball FBGA pinout

*J 1274732 See ECN VKN/AESA Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform

Issue

Date

Orig. of Change Description of Change

(Corrected the ball name for H9 to VSS from V Added the Maximum Rating for Supply Voltage on V Changed t Switching Characteristics table. Updated the Ordering Information table.

, t

from 25 ns to 20 ns and t

TH

TL

SSQ

from 5 ns to 10 ns in TAP AC

TDOV

).

Relative to GND.

DDQ

Document #: 38-05288 Rev. *J Page 32 of 32

[+] Feedback

Cypress Semiconductor CY7C1471V33, CY7C1473V33, CY7C1475V33 Specification Sheet

Specifications and Main Features

Frequently Asked Questions

User Manual