p
CY7C1470V33
a
b
c
d
C
C
Pi
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 3.3V power supply
• 3.3V/2.5V I/O power supply
• Fast clock-to-output time
— 3.0 ns (for 250-MHz device)
• Clock Enable (CEN
• Synchronous self-timed writes
• CY7C1470V33, CY7C1472V33 available in
JEDEC-standard lead-free 100-pin TQFP, lead-free and
non-lead-free 165-ball FBGA package. CY7C1474V33
available in lead-free and non-lead-free 209 ball FBGA
package
• IEEE 1149.1 JTAG Boundary Scan compatible
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
) pin to suspend operation
elined SRAM with NoBL™ Architecture
CY7C1472V33
CY7C1474V33
72-Mbit (2M x 36/4M x 18/1M x 72)
Functional Description
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back
Read/Write operations with no wait states. The
CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
equipped with the advanced (NoBL) logic requi red to enable
consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1470V33, CY7C1472V33,
and CY7C1474V33 are pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
–BWh for CY7C1474V33, BWa–BWd for CY7C1470V33
a
and BW
input. All writes are conducted with on-chip synchronous
–BWb for CY7C1472V33) and a Write Enable (WE)
a
self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
) signal,
Logic Block Diagram-CY7C1470V33 (2M x 36)
A0, A1, A
MODE
C
LK
EN
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05289 Rev. *I Revised June 20, 2006
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
I
M
S
T
P
E
S
R
S
E
E
REGISTER 0
INPUT
O
D
U
T
A
P
T
U
A
T
B
S
T
E
E
R
I
N
G
E
DQs
U
DQP
F
DQP
F
DQP
E
DQP
R
S
E
[+] Feedback
s
P
a
P
b
P
c
P
d
P
e
P
f
P
g
P
h
C
C
a
b
C
C
Logic Block Diagram-CY7C1472V33 (4M x 18)
CY7C1470V33
CY7C1472V33
CY7C1474V33
A0, A1, A
MODE
C
LK
EN
ADV/LD
BW
a
BW
b
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
Sleep
Control
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
Logic Block Diagram-CY7C1474V33 (1M x 72)
A0, A1, A
MODE
C
LK
EN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1
A0
ADV/LD
C
WRITE ADDRESS
REGISTER 2
D1D0Q1
BURST
LOGIC
A1'
A0'
Q0
O
U
T
P
S
U
E
T
N
S
WRITE
DRIVERS
A1'
A0'
Q0
MEMORY
ARRAY
INPUT
REGISTER 1
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
E
REGISTER 0
INPUT
O
U
T
P
D
U
A
T
T
A
B
DQs
U
S
F
T
E
E
R
I
N
G
E
DQP
F
DQP
E
R
S
E
O
U
T
P
S
U
ARRAY
E
T
N
S
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
ADV/LD
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
WE
INPUT
E
REGISTER 1
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
D
A
T
A
S
T
E
E
R
N
G
INPUT
REGISTER 0
O
U
T
P
U
T
B
DQ
U
F
DQ
F
DQ
E
R
DQ
S
I
E
DQ
DQ
E
DQ
DQ
DQ
Selection Guide
250 MHz 200 MHz 167 MHz Unit
Maximum Access Time 3.0 3.0 3.4 ns
Maximum Operating Current 500 500 450 mA
Maximum CMOS Standby Current 120 120 120 mA
Document #: 38-05289 Rev. *I Page 2 of 29
[+] Feedback
a
Pin Configurations
100-pin TQFP Packages
CY7C1470V33
CY7C1472V33
CY7C1474V33
DQPc
DQc
DQc
V
DDQ
V
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
V
DDQ
DQd
DQd
DQPd
1CE2
A
A
CE
BWa
BWd
BWc
BWb
CE3VDDV
SS
CLKWECEN
100999897969594939291908988878685848382
1
2
3
4
5
SS
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SS
26
27
28
29
30
CY7C1470V33
(2M x 36)
31323334353637383940414243444546474849
OE
ADV/LD
A
A
A
A
81
DDQ
SS
SS
DDQ
SS
DD
DDQ
SS
SS
DDQ
NC
NC
NC
V
DDQ
V
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
NC
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DQPb
NC
V
V
DDQ
NC
NC
NC
SS
SS
DQPb
80
DQb
79
DQb
78
V
77
V
76
DQb
75
DQb
74
DQb
73
DQb
72
V
71
V
70
DQb
69
DQb
68
V
67
NC
66
V
65
ZZ
64
DQa
63
DQa
62
V
61
V
60
DQa
59
DQa
58
DQa
57
DQa
56
V
55
V
54
DQa
53
DQa
52
DQPa
51
50
1CE2
A
A
CE
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
bBWa
3
SS
VDDV
CE
BW
NC
NC
CY7C1472V33
(4M x 18)
CLKWECEN
OE
ADV/LD
A
A
A
A
81
A
80
NC
79
NC
78
V
77
DDQ
V
SS
76
NC
75
DQP
74
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
MODE
AAA
0
A
A1A
SS
DD
V
V
NC(288)
NC(144)
AAA
A
A
A
A
A
A
A
AAA
MODE
1A0
A
AAA
A
A
A
DD
SS
V
V
NC(288)
NC(144)
A
A
A
Document #: 38-05289 Rev. *I Page 3 of 29
[+] Feedback
Pin Configurations (continued)
2345671
NC
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
A
A
A
CE
CE2
V
V
c
V
c
V
c
V
c
NC
V
d
V
d
V
d
V
d
V
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/576M
NC/1G
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
NC
DQ
d
DQ
d
DQ
d
DQ
d
DQP
d
NC/144M
MODE
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1470V33 (2M x 36)
CE
b
CLK
a
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
CEN
3
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
c
BW
d
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
CY7C1470V33
CY7C1472V33
CY7C1474V33
891011
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
V
V
V
V
V
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
A
NC
NC
NC DQP
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
A
b
b
b
b
a
a
a
a
DQ
DQ
DQ
DQ
ZZ
DQ
DQ
DQ
DQ
DQP
NC/288M
b
b
b
b
b
a
a
a
a
a
AA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CY7C1472V33 (4M x 18)
2345671
NC/576M
NC/1G
NC
NC
NC V
NC
NC
NC
DQ
b
DQ
b
DQ
b
DQ
b
DQP
b
NC/144M
MODE
A
A
NC
DQ
DQ
DQ
DQ
NC
NC
NC
NC
NC
NC
A
CE
CE2
V
DDQ
V
b
b
b
b
V
V
V
DDQ
DDQ
DDQ
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
BW
1
b
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
BW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
a
CE
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
891011
A A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
NC DQP
NC
NC
NC
NC
NC
DQ
a
DQ
a
DQ
a
DQ
a
NC
A
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCKA0
A
NC
a
DQ
a
DQ
a
DQ
a
DQ
a
ZZ
NCV
NC
NC
NC
NC
NC/288M
AA
Document #: 38-05289 Rev. *I Page 4 of 29
[+] Feedback
Pin Configurations (continued)
1234 56789 1110
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1474V33 (1M x 72)
CY7C1470V33
CY7C1472V33
CY7C1474V33
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
AAAA
BWScBWS
BWS
V
V
DDQ
V
V
DDQ
V
V
DDQ
CLK
V
DDQ
V
V
DDQ
V
V
DDQ
V
NC/144M
AA
TMS
SS
SS
SS
SS
SS
SS
CE
2
g
NC
V
V
DDQ
SS
DDQ
SS
DDQ
NC/576M
d
NC/1G
BWS
h
V
V
V
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC MODE
A
TDI TDO TCK
ADV/LD
NC
WE
CE
OE
V
V
V
V
V
V
V
V
V
V
V
DD
SS
DD
SS
DD
SS
DD
SS
DD
SS
DD
V
DD
NC
NC
NC
NC
CEN
NC
NC
NC
ZZ
V
DD
NC
A A NC/288M
A
AA
AA
A1
A0
A
NC
1
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
A
CE
3
BWS
BWS
b
BWSeBWS
V
V
V
V
V
V
NC
DDQ
V
DDQ
V
DDQ
NC
DDQ
V
DDQ
V
DDQ
NC
SS
SS
SS
SS
V
V
V
V
V
V
V
DDQ
V
DDQ
V
DDQ
NC
DDQ
V
DDQ
V
DDQ
V
AA
SS
SS
SS
SS
SS
SS
DQb
DQb
f
DQb
a
DQb
DQPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
Document #: 38-05289 Rev. *I Page 5 of 29
[+] Feedback
CY7C1470V33
CY7C1472V33
CY7C1474V33
Pin Definitions
Pin Name I/O Type Pin Description
A0
A1
A
BW
a
BW
b
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
WE
ADV/LD Input-
CLK Input-
CE
1
CE
2
CE
3
OE
CEN
DQ
S
DQP
X
MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
TDO JTAG Serial
TDI JTAG Serial Input
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Synchronous
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
I/O-
Synchronous
I/O-
Synchronous
Output
Synchronous
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
BW
controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf
c
controls DQ
and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.
f
controls DQa and DQPa, BWb controls DQb and DQPb,
a
Write Enable Input, acti ve LOW . Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN
new address can be loaded into the device for an access. After being deselected, ADV/LD
is asserted LOW) the internal burst counter is advanced. When LOW, a
should
be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN
is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
and CE2 to select/deselect the device.
CE
1
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE
is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
deselect the device, CEN
can be used to extend the previous cycle when required.
does not
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
controlled by OE
as outputs. When HIGH, DQ
ically tri-stated during the data portion of a write sequence, during the first clock when emerging
during the previous clock rise of the read cycle. The direction of the pins is
[17:0]
and the internal control logic. When OE is asserted LOW, the pins can behave
–DQd are placed in a tri-state condition. The outputs are automat-
a
from a deselected state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQX. During write
sequences, DQP
and DQP
is controlled by BW
is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg
d
is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,
a
, DQPh is controlled by BWh.
g
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Document #: 38-05289 Rev. *I Page 6 of 29
[+] Feedback
Pin Definitions (continued)
Pin Name I/O Type Pin Description
TMS T est Mode Select
Synchronous
TCK JTAG Clock Clock input to the JTAG circuitry.
V
V
V
DD
DDQ
SS
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground Ground for the device. Should be connected to ground of the system.
NC – No connects. This pin is not connected to the die.
NC(144M,
– These pins are not connected. They will be used for expansion to the 144M, 288M, 576M, and
288M,
576M, 1G)
ZZ Input-
Asynchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
1G densities.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
CY7C1470V33
CY7C1472V33
CY7C1474V33
Functional Overview
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
synchronous-pipelined Burst NoBL SRAMs desig ned specifically to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
) is 3.0 ns (250-MHz device).
CO
Accesses can be initiated by asserting all three Chip Enables
, CE2, CE3) active at the rising edge of the clock. If Clock
(CE
1
Enable (CEN
) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE
Writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD
should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 3.0 ns
). If CEN is HIGH, the clock
). BW
can be used to
[x]
). All
) simplify depth expansion.
is asserted LOW, (2) CE1, CE2,
(250-MHz device) provided OE is active LOW. After the first
clock of the Read access the output buffers are controlled by
OE
and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will tri-state following the
next clock rise.
Burst Read Accesses
The CY7C1470V33, CY7C1472V33, and CY7C1474V33
have an on-chip burst counter that allows the user the ability
to supply a single address and conduct up to four Reads
without reasserting the address inputs. ADV/LD
must be
driven LOW in order to load a new address into the SRAM, as
described in the Single Read Access section above. The
sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD
the state of chip enables inputs or WE
will increment the internal burst counter regardless of
. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address inputs
are ALL asserted active, and (3) the Write signal WE
3
is asserted LOW, (2) CE1, CE2,
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
allows the external logic to present the data on DQ
(DQ
a,b,c,d,e,f,g,h
DQ
a,b,c,d
CY7C1472V33). In addition, the address for the subsequent
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1470V33 and DQ
a,b,c,d
for CY7C1474V33,
input signal. This
and DQP
a,b
/DQP
a,b
for
access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are
asserted).
Document #: 38-05289 Rev. *I Page 7 of 29
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CY7C1470V33
CY7C1472V33
CY7C1474V33
On the next clock rise the data presented to DQ and DQP
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1470V33 & DQ
a,b,c,d
(DQ
a,b,c,d,e,f,g,h
DQ
a,b,c,d
CY7C1472V33) (or a subset for byte write operations, see
for CY7C1474V33,
a,b
/DQP
a,b
for
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
The data written during the Write operation is controlled by BW
(BW
a,b,c,d,e,f,g,h
CY7C1470V33 and BW
CY7C1470V33, CY7C1472V33, and CY7C1474V33 provides
for CY7C1474V33, BW
for CY7C1472V33) signals. The
a,b
a,b,c,d
for
Byte Write capability that is described in the Write Cycle
Description table. Asserting the Write Enable input (WE
the selected Byte Write Select (BW
) input will selectively write
) with
to only the desired bytes. Bytes not selected during a Byte
Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations. Byte Write capability has been included in
order to greatly simplify Read/Modify/Write sequences, which
can be reduced to simple Byte Write operations.
Because the CY7C1470V33, CY7C1472V33, and
CY7C1474V33 are common I/O devices, data should not be
driven into the device while the outputs are active. The Output
Enable (OE
to the DQ
CY7C1474V33, DQ
DQ
a,b
the output drivers. As a safety precaution, DQ
(DQ
DQ
a,b,c,d
CY7C1472V33) are automatically tri-stated during the data
) can be deasserted HIGH before presenting data
/DQP
a,b
a,b,c,d,e,f,g,h
/DQP
and DQP (DQ
a,b,c,d
for CY7C1472V33) inputs. Doing so will tri-state
/DQP
a,b,c,d,e,f,g,h
for CY7C1470V33 and DQ
a,b,c,d
a,b,c,d,e,f,g,h
/DQP
a,b,c,d
for CY7C1474V33,
/DQP
for CY7C1470V33 and
a,b,c,d,e,f,g,h
and DQP
/DQP
a,b
a,b
for
for
portion of a Write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 has
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD
must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
CY7C1474V33, BW
CY7C1472V33) inputs must be driven in each cycle of the
for CY7C1470V33 and BW
a,b,c,d
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
, CE2, and CE3, must remain inactive
1
after the ZZ input returns LOW.
ZZREC
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
DD
)
Third
Address
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
Third
Address
driven HIGH on the subsequent clock rise, the Chip Enables
, CE2, and CE3) and WE inputs are ignored and the burst
(CE
1
counter is incremented. The correct BW
(BW
a,b,c,d,e,f,g,h
for
ZZ Mode Electrical Characteristics
Parameter Description T est Conditions Min. Max Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Sleep mode standby current ZZ > VDD − 0.2V 120 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
CYC
CYC
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
a,b
Fourth
Address
Fourth
Address
ns
ns
ns
for
Document #: 38-05289 Rev. *I Page 8 of 29
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CY7C1470V33
CY7C1472V33
CY7C1474V33
Truth Table
[1, 2, 3, 4, 5, 6, 7]
Operation Address Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ
Deselect Cycle None H L L X X X L L-H Tri-State
Continue
None X L H X X X L L-H Tri-State
Deselect Cycle
Read Cycle
External L L L H X L L L-H Data Out (Q)
(Begin Burst)
Read Cycle
Next X L H X X L L L-H Data Out (Q)
(Continue Burst)
NOP/Dummy Read
External L L L H X H L L-H Tri-State
(Begin Burst)
Dummy Read
Next X L H X X H L L-H Tri-State
(Continue Burst)
Write Cycle
External L L L L L X L L -H Data In (D)
(Begin Burst)
Write Cycle
Next X L H X L X L L-H Data In (D)
(Continue Burst)
NOP/Write Abort
None L L L L H X L L-H Tri-State
(Begin Burst)
Write Abort
Next X L H X H X L L-H Tri-State
(Continue Burst)
Ignore Clock Edge
Current X L X X X X H L-H -
(Stall)
Sleep Mode None X H X X X X X X Tri-State
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE
3. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE
= H inserts wait states.
5. CEN
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE
is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQs and DQP
7. OE
is inactive or when the device is deselected, and DQs= data when OE is active.
and BW
. See Write Cycle Description table for details.
[a:d]
stands for ALL Chip Enables active. BWx = 0 signifies at least one B yte W rite Select is active, BWx = Valid
signal.
.
= tri-state when OE
[a:d]
Document #: 38-05289 Rev. *I Page 9 of 29
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CY7C1470V33
CY7C1472V33
CY7C1474V33
Partial Write Cycle Description
Function (CY7C1470V33) WE BW
[1, 2, 3, 8]
d
BW
c
BW
b
BW
a
Read H X X X X
Write – No bytes written L H H H H
Write Byte a – (DQa and DQPa) LHHHL
Write Byte b – (DQb and DQPb)LHHLH
Write Bytes b, a L H H L L
Write Byte c – (DQ
and DQPc)LHLHH
c
Write Bytes c, a L H L H L
Write Bytes c, b L H L L H
Write Bytes c, b, a L H L L L
Write Byte d – (DQ
and DQPd)LLHHH
d
Write Bytes d, a L L H H L
Write Bytes d, b LLHLH
Write Bytes d, b, a L L H L L
Write Bytes d, c L L L H H
Write Bytes d, c, a L L L H L
Write Bytes d, c, b L L L L H
Write All Bytes L L L L L
Function (CY7C1472V33) WE
BW
b
BW
a
Read Hxx
Write – No Bytes Written L H H
Write Byte a – (DQa and DQPa)LHL
Write Byte b – (DQ
and DQPb)LLH
b
Write Both Bytes L L L
Function (CY7C1474V33) WE BW
x
Read Hx
Write – No Bytes Written L H
Write Byte X − (DQ
Write All Bytes LAll BW
Note:
8. Table only lists a partial listing of the Byte Write combinations. Any combination of BW
active.
and DQP
x
x)
LL
= L
is valid. Appropriate Write will be done based on which Byte Write is
[a:d]
Document #: 38-05289 Rev. *I Page 10 of 29
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CY7C1470V33
T
O
CY7C1472V33
CY7C1474V33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1470V33, CY7C1472V33, and CY7C1474V33
incorporates a serial boundary scan test access port (TAP).
This port operates in accordance with IEEE Standard
1149.1-1990 but does not have the set of functions required
for full 1149.1 compliance. These functions from the IEEE
specification are excluded because their inclusion places an
added delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not conflict
with the operation of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V
I/O logic levels.
The CY7C1470V33, CY7C1472V33, and CY7C1474V33
contains a TAP controller, inst ruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the T AP controller, TCK must be tied LOW
(V
) to prevent clocking of the device. TDI and TMS are inter-
SS
nally pulled up and may be unconnected. They may alternately
be connected to V
left unconnected. Upon power-up, the device will come up in
through a pull-up resistor. TDO should be
DD
a reset state which will not interfere with the operation of the
device.
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1 1
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
0 0
EXIT2-DR
UPDATE-DR
1 0
1
0
0
0 0
1
1 1
0 0
0
1
1
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
SELECT
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
1
0
0
1
0
1
1
0
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See Tap Controller Block Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
012
TDI TD
TCK
MS TAP CONTROLLER
Selection
Circuitry
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (V
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO bal l on
the falling edge of TCK.
Instruction Register
012293031 ...
Identification Register
012..x ...
Boundary Scan Register
S
election
Circuitr
y
DD
) for five
Document #: 38-05289 Rev. *I Page 11 of 29
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CY7C1470V33
CY7C1472V33
CY7C1474V33
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be pla ced betwee n the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V
) when the BYPASS instruction is executed.
SS
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1 149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction reg ister
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarante e th at the boun dary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold time (t
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
plus tCH).
CS
Document #: 38-05289 Rev. *I Page 12 of 29
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CY7C1470V33
123456
T
CY7C1472V33
CY7C1474V33
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
TAP Timing
Test Clock
(TCK)
est Mode Select
(TMS)
Test Data-In
(TDI)
Test Data-Out
(TDO)
t
TMSS
t
TDIS
t
t
TMSH
t
TDIH
TH
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
t
TL
t
CYC
t
TDOX
t
TDOV
DON’T CARE UNDEFINED
TAP AC Switching Characteristics Over the Operating Range
[9, 10]
Parameter Description Min. Max Unit
Clock
t
TCYC
t
TF
t
TH
t
TL
TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH time 20 ns
TCK Clock LOW time 20 ns
Output Times
t
TDOV
t
TDOX
Set-up Times
t
TMSS
t
TDIS
t
CS
TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns
TMS Set-up to TCK Clock Rise 5 ns
TDI Set-up to TCK Clock Rise 5 ns
Capture Set-up to TCK Rise 5 ns
Hold Times
t
TMSH
t
TDIH
t
CH
Notes:
9. t
CS
10.Test conditions are specified using the load in TAP AC Test Conditions. t
TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns
and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
R/tF
= 1 ns.
Document #: 38-05289 Rev. *I Page 13 of 29
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CY7C1470V33
T
F
T
F
CY7C1472V33
CY7C1474V33
3.3V TAP AC Test Conditions
Input pulse levels................................................ VSS to 3.3V
Input rise and fall times................................................ ...1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
1.5V
2.5V TA P AC Test Conditions
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage ............................1.25V
2.5V TA P AC Output Load Equivalent
1.25V
50Ω
DO
Z = 50Ω
O
20p
DO
Z = 50Ω
O
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)
Parameter Description Test Conditions Min. Max. Unit
V
V
V
V
V
V
I
X
OH1
OH2
OL1
OL2
IH
IL
Output HIGH Voltage IOH = –4.0 mA,V
I
= –1.0 mA,V
OH
Output HIGH Voltage IOH = –100 µA V
Output LOW Voltage IOL = 8.0 mA V
I
= 1.0 mA V
OL
Output LOW Voltage IOL = 100 µA V
Input HIGH Voltage V
Input LOW Voltage V
Input Load Current GND < VIN < V
[11]
= 3.3V 2.4 V
DDQ
= 2.5V 2.0 V
DDQ
= 3.3V 2.9 V
DDQ
V
= 2.5V 2.1 V
DDQ
= 3.3V 0.4 V
DDQ
= 2.5V 0.4 V
DDQ
= 3.3V 0.2 V
DDQ
V
= 2.5V 0.2 V
DDQ
= 3.3V 2.0 VDD + 0.3 V
DDQ
V
= 2.5V 1.7 VDD + 0.3 V
DDQ
= 3.3V –0.3 0.8 V
DDQ
V
= 2.5V –0.3 0.7 V
DDQ
DDQ
–5 5 µA
50Ω
20p
Note:
11.All voltages referenced to V
Document #: 38-05289 Rev. *I Page 14 of 29
(GND).
SS
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CY7C1470V33
CY7C1472V33
CY7C1474V33
Identification Register Definitions
Instruction Field
Revision Number (31:29) 000 000 000 Describes the version number
Device Depth (28:24)
Architecture/Memory
Type(23:18)
Bus Width/Density(17:12) 100100 010100 110100 Defines width and density
Cypress JEDEC ID Code
(11:1)
ID Register Presence
Indicator (0)
[12]
CY7C1470V33
(2M x 36)
01011 01011 01011 Reserved for internal use
001000 001 000 001000 Defines memory type and archi-
00000110100 00000110100 00000110100 Allows unique identification of
1 1 1 Indicates the presence of an ID
Scan Register Sizes
Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72)
Instruction 3 3 3
Bypass 1 1 1
ID 32 32 32
Boundary Scan Order - 165 FBGA 71 52 Boundary Scan Order - 209 FBGA - - 110
CY7C1472V33
(4M x 18)
CY7C1474V33
(1M x 72) Description
tecture
SRAM vendor
register
Identification Codes
Instruction Code Description
EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE 001 Loads the ID register with the vendor ID code and places the regi ster between TDI
and TDO. This operation does not affect SRAM operations.
SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
Note:
12.Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
Document #: 38-05289 Rev. *I Page 15 of 29
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CY7C1472V33
CY7C1474V33
Boundary Scan Exit Order (2M x 36)
Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID
1C1 21 R3 41J11 61B7
2 D1 22 P2 42 K10 62 B6
3E1 23 R4 43J10 63A6
4D2 24 P6 44H11 64B5
5E2 25 R6 45G11 65A5
6F1 26 R8 46F11 66A4
7G1 27 P3 47E11 67B4
8F2 28 P4 48D10 68B3
9G2 29 P8 49D11 69A3
10 J1 30 P9 50 C11 70 A2
11 K1 31 P10 51 G10 71 B2
12 L1 32 R9 52 F10
13 J2 33 R10 53 E10
14 M1 34 R11 54 A9
15 N1 35 N11 55 B9
16 K2 36 M11 56 A10
17 L2 37 L11 57 B10
18 M2 38 M10 58 A8
19 R1 39 L10 59 B8
20 R2 40 K11 60 A7
Boundary Scan Exit Order (4M x 18)
Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID
1D2 14 R4 27L10 40B10
2E2 15 P6 28K10 41A8
3F2 16 R6 29J10 42B8
4G2 17 R8 30H11 43A7
5J1 18 P3 31G11 44B7
6K1 19 P4 32F11 45B6
7L1 20 P8 33E11 46A6
8M1 21 P9 34D11 47B5
9 N1 22 P10 35 C11 48 A4
10 R1 23 R9 36 A11 49 B3
11 R2 24 R10 37 A9 50 A3
12 R3 25 R11 38 B9 51 A2
13 P2 26 M10 39 A10 52 B2
Document #: 38-05289 Rev. *I Page 16 of 29
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CY7C1470V33
CY7C1472V33
CY7C1474V33
Boundary Scan Exit Order (1M x 72)
Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID
1 A1 29 T1 57 U10 85 B11
2A2 30T2 58T11 86B10
3B1 31U1 59T10 87A11
4B2 32U2 60R11 88A10
5 C1 33 V1 61 R10 89 A7
6C2 34V2 62P11 90A5
7 D1 35 W1 63 P10 91 A9
8D2 36W2 64N11 92U8
9 E1 37 T6 65 N10 93 A6
10 E2 38 V3 66 M11 94 D6
11 F1 39 V4 67 M10 95 K6
12 F2 40 U4 68 L11 96 B6
13 G1 41 W5 69 L10 97 K3
14 G2 42 V6 70 P6 98 A8
15 H1 43 W6 71 J11 99 B4
16 H2 44 V5 72 J10 100 B3
17 J1 45 U5 73 H11 101 C3
18 J2 46 U6 74 H10 102 C4
19 L1 47 W7 75 G11 103 C8
20 L2 48 V7 76 G10 104 C9
21 M1 49 U7 77 F11 105 B9
22 M2 50 V8 78 F10 106 B8
23 N1 51 V9 79 E10 107 A4
24 N2 52 W11 80 E11 108 C6
25 P1 53 W10 81 D11 109 B7
26 P2 54 V11 82 D10 110 A3
27 R2 55 V10 83 C11
28 R1 56 U11 84 C10
Document #: 38-05289 Rev. *I Page 17 of 29
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CY7C1470V33
CY7C1472V33
CY7C1474V33
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
Supply Voltage on V
DC to Outputs in Tri-State...................–0.5V to V
Relative to GND........–0.5V to +4.6V
DD
Relative to GND......–0.5V to +V
DDQ
DDQ
DD
+ 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current...................................... ... ........... > 200 mA
Operating Range
Range
Commercial 0°C to +70°C 3.3V
Industrial –40°C to +85°C
Ambient
Temperature V
–5%/+10%
DD
V
DDQ
2.5V – 5%
to V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range
[13, 14]
Parameter Description Test Conditions Min. Max. Unit
V
V
DD
DDQ
Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage for 3.3V I/O 3.135 V
DD
for 2.5V I/O 2.375 2.625 V
V
OH
Output HIGH Voltage for 3.3V I/O, I
= −4.0 mA 2.4 V
OH
for 2.5V I/O, IOH= −1.0 mA 2.0 V
V
OL
Output LOW Voltage for 3.3V I/O, IOL= 8.0 mA 0.4 V
for 2.5V I/O, IOL= 1.0 mA 0.4 V
V
IH
Input HIGH Voltage
[13]
for 3.3V I/O 2.0 VDD + 0.3V V
for 2.5V I/O 1.7 VDD + 0.3V V
V
IL
Input LOW Voltage
[13]
for 3.3V I/O –0.3 0.8 V
for 2.5V I/O –0.3 0.7 V
I
I
I
X
OZ
DD
Input Leakage Current
GND ≤ VI ≤ V
except ZZ and MODE
Input Current of MODE Input = V
Input = V
Input Current of ZZ Input = V
Input = V
SS
DD
SS
DD
Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply V
DD
f = f
= Max., I
= 1/t
MAX
DDQ
–5 5 µA
–30 µA
–5 µA
Output Disabled –5 5 µA
DDQ,
OUT
CYC
= 0 mA,
4.0-ns cycle, 250 MHz 500 mA
5.0-ns cycle, 200 MHz 500 mA
5 µA
30 µA
6.0-ns cycle, 167 MHz 450 mA
I
SB1
I
SB2
I
SB3
I
SB4
Notes:
13.Overshoot: V
14.T
Power-up
Automatic CE
Power-down
Current—TTL Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—TTL Inputs
(AC) < V
IH
: Assumes a linear ramp from 0V to V
+1.5V (Pulse width less than t
DD
Max. VDD, Device Deselected,
≥ VIH or VIN ≤ VIL,
V
IN
f = f
MAX
= 1/t
CYC
Max. VDD, Device Deselected,
≤ 0.3V or VIN > V
V
IN
f = 0
DDQ
− 0.3V,
Max. VDD, Device Deselected,
V
≤ 0.3V or VIN > V
IN
f = f
MAX
= 1/t
CYC
DDQ
− 0.3V,
Max. VDD, Device Deselected,
≥ VIH or VIN ≤ VIL, f = 0
V
IN
/2), undershoot: VIL(AC)> –2V (Pulse width less than t
CYC
(min.) within 200 ms. During this time VIH < V
DD
4.0-ns cycle, 250 MHz 245 mA
5.0-ns cycle, 200 MHz 245 mA
6.0-ns cycle, 167 MHz 245 mA
All speed grades 120 mA
4.0-ns cycle, 250 MHz 245 mA
5.0-ns cycle, 200 MHz 245 mA
6.0-ns cycle, 167 MHz 245 mA
All speed grades 135 mA
/2).
DD
and V
DDQ
< V
DD
CYC
.
DD
V
Document #: 38-05289 Rev. *I Page 18 of 29
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CY7C1472V33
CY7C1474V33
Capacitance
Parameter Description Test Conditions
C
ADDRESS
C
DATA
C
Control Input Capacitance 8 8 8 pF
CTRL
C
CLK
C
I/O
Thermal Resistance
Parameters Description Test Conditions
Θ
JA
Θ
JC
[15]
100 TQFP
Max.
Address Input Capacitance TA = 25°C, f = 1 MHz,
V
= 3.3V
Data Input Capacitance 5 5 5 pF
V
DD
DDQ
= 2.5V
6 6 6 pF
165 FBGA
Max.
209 FBGA
Clock Input Capacitance 6 6 6 pF
Input/Output Capacitance 5 5 5 pF
[15]
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA/JESD51.
100 TQFP
Package
24.63 16.3 15.2 °C/W
2.28 2.1 1.7 °C/W
165 FBGA
Package
209 FBGA
Package Unit
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
Z
= 50Ω
0
VL= 1.5V
(a)
R
= 50Ω
L
3.3V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
R = 317Ω
(b)
R = 351Ω
V
DDQ
GND
≤ 1 ns
ALL INPUT PULSES
10%
90%
(c)
Max. Unit
90%
10%
≤ 1 ns
2.5V I/O Test Load
OUTPUT
= 50Ω
Z
0
= 1.25V
V
L
R
L
(a)
Note:
15.Tested initially and after any design or process changes that may affect these parameters.
2.5V
OUTPUT
= 50Ω
5pF
INCLUDING
JIG AND
SCOPE
R = 1667Ω
R = 1538Ω
(b)
V
DDQ
GND
≤ 1 ns
ALL INPUT PULSES
10%
90%
90%
10%
≤ 1 ns
(c)
Document #: 38-05289 Rev. *I Page 19 of 29
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CY7C1472V33
CY7C1474V33
Switching Characteristics Over the Operating Range
Parameter Description
[18]
t
Power
Clock
t
CYC
F
MAX
t
CH
t
CL
Output Times
t
CO
t
OEV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Set-up Times
t
AS
t
DS
t
CENS
t
WES
t
ALS
t
CES
Hold Times
t
AH
t
DH
t
CENH
t
WEH
t
ALH
t
CEH
VCC (typical) to the First Access Read or Write 1 1 1 ms
Clock Cycle Time 4.0 5.0 6.0 ns
Maximum Operating Frequency 250 200 167 MHz
Clock HIGH 2.0 2.0 2.2 ns
Clock LOW 2.0 2.0 2.2 ns
Data Output Valid Af ter CLK Rise 3.0 3.0 3.4 ns
OE LOW to Output Valid 3.0 3.0 3.4 ns
Data Output Hold After CLK Rise 1.3 1.3 1.5 ns
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
[19, 20, 21]
[19, 20, 21]
[19, 20, 21]
[19, 20, 21]
Address Set-up Before CLK Rise 1.4 1.4 1.5 ns
Data Input Set-up Before CLK Rise 1.4 1.4 1.5 ns
CEN Set-up Before CLK Rise 1.4 1.4 1.5 ns
WE, BWx Set-up Before CLK Rise 1.4 1.4 1.5 ns
ADV/LD Set-up Before CLK Rise 1.4 1.4 1.5 ns
Chip Select Set-up 1.4 1.4 1.5 ns
Address Hold After CLK Rise 0.4 0.4 0.5 ns
Data Input Hold After CLK Rise 0.4 0.4 0.5 ns
CEN Hold After CLK Rise 0.4 0.4 0.5 ns
WE, BWx Hold After CLK Rise 0.4 0.4 0.5 ns
ADV/LD Hold after CLK Rise 0.4 0.4 0.5 ns
Chip Select Hold After CLK Rise 0.4 0.4 0.5 ns
[16, 17]
–250
–200 –167
3.0 3.0 3.4 ns
1.3 1.3 1.5 ns
3.0 3.0 3.4 ns
0 0 0 ns
UnitMin. Max. Min. Max. Min. Max.
Notes:
16.Timing reference is 1.5V when V
17.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18.This part has a voltage regulator internally; t
initiated.
, t
, t
19.t
CHZ
20.At any given voltage and temperature, t
21.This parameter is sampled and not 100% tested.
CLZ
data bus. These specifications do not imply a b us contention con dition, bu t reflect p aramet ers guarantee d over worst case user cond itions. Devi ce is designed
to achieve High-Z prior to Low-Z under the same system conditions.
EOLZ
, and t
EOHZ
= 3.3V and is 1.25V when V
DDQ
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
EOHZ
Document #: 38-05289 Rev. *I Page 20 of 29
= 2.5V.
DDQ
is the time power needs to be supplied above VDD minimum initially, b efore a Read or Write op eration ca n be
power
is less than t
EOLZ
and t
is less than t
CHZ
to eliminate bus contention between SRAMs whe n sha ring the sa me
CLZ
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Switching Waveforms
123456789
10
I
CE
x
[22, 23, 24]
t
CENS
t
CES
t
CENH
t
CEH
Read/Write/Timing
CLK
CEN
ADV/LD
WE
BW
CY7C1470V33
CY7C1472V33
CY7C1474V33
t
CYC
t
t
CL
CH
ADDRESS
Data
n-Out (DQ)
OE
A1 A2
t
t
AH
AS
WRITE
D(A1)
WRITE
D(A2)
A3
t
t
DH
DS
D(A1) D(A2) D(A5)Q(A4)Q(A3)
BURST
WRITE
D(A2+1)
READ
Q(A3)
A4
t
CO
t
CLZ
D(A2+1)
READ
Q(A4)
t
BURST
READ
Q(A4+1)
DOH
A5 A6 A7
t
OEHZ
t
WRITE
D(A5)
OEV
t
OELZ
t
CHZ
Q(A4+1)
t
DOH
READ
Q(A6)
DON’T CARE UNDEFINED
Notes:
22.For this waveform ZZ is tied LOW.
23.When CE
24.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1= Interleaved). Burst operations are optional.
is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
WRITE
D(A7)
Q(A6)
DESELECT
Document #: 38-05289 Rev. *I Page 21 of 29
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Switching Waveforms (continued)
45678910
123
A
NOP, STALL and DESELECT Cycles
CLK
CEN
CE
ADV/LD
WE
BWx
[22, 23, 25]
CY7C1470V33
CY7C1472V33
CY7C1474V33
ADDRESS
Data
In-Out (DQ)
ZZ Mode Timing
A1
D(A1)
[26, 27]
READ
Q(A2)
CLK
ZZ
I
SUPPLY
LL INPUTS
(except ZZ)
A2
STALL NOP READ
t
ZZ
t
ZZI
I
DDZZ
A3 A4
D(A1) Q(A2) Q(A3)
READ
Q(A3)
WRITE
D(A4)
DON’T CARE UNDEFINED
STALLWRITE
A5
D(A4)
Q(A5)
t
ZZREC
t
RZZI
DESELECT or READ Only
t
CHZ
Q(A5)
DESELECT CONTINUE
DESELECT
Outputs (Q)
Notes:
25.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN
26.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
27.I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05289 Rev. *I Page 22 of 29
High-Z
DON’T CARE
being used to create a pause. A Write is not performed during this cycle.
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CY7C1472V33
CY7C1474V33
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz) Ordering Code
167 CY7C1470V33-167AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1472V33-167AXC
CY7C1470V33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1472V33-167BZC
CY7C1470V33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1472V33-167BZXC
CY7C1474V33-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1474V33-167BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
CY7C1470V33-167AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial
CY7C1472V33-167AXI
CY7C1470V33-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1472V33-167BZI
CY7C1470V33-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1472V33-167BZXI
CY7C1474V33-167BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1474V33-167BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
200 CY7C1470V33-200AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1472V33-200AXC
CY7C1470V33-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1472V33-200BZC
CY7C1470V33-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1472V33-200BZXC
CY7C1474V33-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1474V33-200BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
CY7C1470V33-200AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial
CY7C1472V33-200AXI
CY7C1470V33-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm)
CY7C1472V33-200BZI
CY7C1470V33-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4mm) Lead-Free
CY7C1472V33-200BZXI
CY7C1474V33-200BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1474V33-200BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
visit www.cypress.com for actual products offered.
Package
Diagram Part and Package Type
Operating
Range
Document #: 38-05289 Rev. *I Page 23 of 29
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CY7C1470V33
CY7C1472V33
CY7C1474V33
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz) Ordering Code
250 CY7C1470V33-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1472V33-250AXC
CY7C1470V33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1472V33-250BZC
CY7C1470V33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1472V33-250BZXC
CY7C1474V33-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1474V33-250BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
CY7C1470V33-250AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
CY7C1472V33-250AXI
CY7C1470V33-250BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1472V33-250BZI
CY7C1470V33-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1472V33-250BZXI
CY7C1474V33-250BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1474V33-250BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
visit www.cypress.com for actual products offered.
Package
Diagram Part and Package Type
Operating
Range
Document #: 38-05289 Rev. *I Page 24 of 29
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Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
14.00±0.10
20.00±0.10
22.00±0.20
100
1
30
31 50
81
80
0.30±0.08
0.65
TYP.
51
12°±1°
(8X)
CY7C1470V33
CY7C1472V33
CY7C1474V33
1.40±0.05
SEE DETAIL
0.20 MAX.
A
GAUGE PLANE
R 0.08 MIN.
0.20 MAX.
0.25
0°-7°
0.60±0.15
1.00 REF.
0° MIN.
R 0.08 MIN.
0.20 MIN.
0.20 MAX.
DETAIL
1.60 MAX.
0.10
51-85050-*B
STAND-OFF
0.05 MIN.
0.15 MAX.
SEATING PLANE
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
A
Document #: 38-05289 Rev. *I Page 25 of 29
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Package Diagrams (continued)
TOP VIEW
PIN 1 CORNER
165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)
1110986754321
CY7C1470V33
CY7C1472V33
CY7C1474V33
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
11
Ø0.45±0.05(165X)
PIN 1 CORNER
1
2345678910
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
+0.05
0.25 C
0.53±0.05
SEATING PLANE
C
0.36
0.35
-0.10
0.15 C
1.40 MAX.
17.00±0.10
A
14.00
0.15(4X)
1.00
7.00
5.00
B
15.00±0.10
1.00
10.00
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
51-85165-*A
Document #: 38-05289 Rev. *I Page 26 of 29
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Package Diagrams (continued)
209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)
CY7C1470V33
CY7C1472V33
CY7C1474V33
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05289 Rev. *I Page 27 of 29
© Cypress Semiconductor Corporation, 2006. The information contained herein is su bj ect to ch an ge wi t hou t notice. Cypress Semiconductor Corporation assumes no responsibility for th e u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypre ss does not aut horize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
51-85167-**
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CY7C1470V33
CY7C1472V33
CY7C1474V33
Document History Page
Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05289
REV. ECN No. Issue Date
** 114676 08/06/02 PKS New Data Sheet
*A 121520 01/27/03 CJM Updated features for package offering
*B 223721 See ECN NJY Changed timing diagrams
*C 235012 See ECN RYQ Minor Cha nge: The data sheets do not match on the spec system and
*D 243572 See ECN NJY Changed ball C11,D11,E11,F11,G11 from DQPb,DQb,DQb,DQb,DQb to
*E 299511 See ECN SYT
*F 323039 See ECN PCI Unshaded 250 MHz speed bin in the AC/DC Table and Selection Guide
*G 351937 See ECN PCI Updated Ordering Information Table
Orig. of
Change Description of Change
Removed 300-MHz offering
Changed tCO, tEOV, tCHZ, tEOHZ from 2.4 ns to 2.6 ns (250 MHz),
tDOH, tCLZ from 0.8 ns to 1.0 ns (250 MHz), tDOH, tCLZ from 1.0 ns
to 1.3 ns (200 MHz)
Updated ordering information
Changed Advanced Information to Preliminary
Changed logic block diagrams
Modified Functional Descri ption
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Included IDD and ISB values
Removed 250-MHz offering and included 225-MHz speed bin
Changed package outline for 165FBGA package and 209-ball BGA package
Removed 119-BGA package offering
external web
DQPa,DQa,DQa,DQa,DQa in page 4
Modified capacitance values in page 20
Removed 225-MHz offering and included 250-MHz speed bin
VBL
Changed t
Changed Θ
100 TQFP Package on Page # 20
Added lead-free information for 100-Pin TQFP and 165 FBGA Packages
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
Add Industrial part numbers in Ordering Info section
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added Address Expansion pins in the Pin Definitions Table
Modified V
Changed package name from 209-ball PBGA to 209-ball FBGA on page# 5
Removed comment of ‘Lead-free BG packages availability below the
Ordering Information
Updated Ordering Information Table
Changed from Preliminary to Final
from 4.4 ns to 4.0 ns for 250-MHz Speed Bin
CYC
from 16.8 to 24.63 °C/W and Θ
JA
, VOH Test Conditions
OL
JC
from 3.3 to 2.28 °C/ W fo r
Document #: 38-05289 Rev. *I Page 28 of 29
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CY7C1470V33
CY7C1472V33
CY7C1474V33
Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05289
REV. ECN No. Issue Date
*H 416221 See ECN RXU Converted from Preliminary to Final
*I 4 72335 See ECN VKN Corrected the typo in the pin configuration for 209-Ball FBGA pinout
Orig. of
Change Description of Change
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed Three-state to Tri-state
Changed the description of I
Current on page# 18
Changed the I
to –30 µA and 5 µA
current values of MODE on page # 18 from –5 µA and 30 µA
X
from Input Load Current to Input Leakage
X
Changed the IX current values of ZZ on page # 18 from –30 µA and 5 µA
to –5 µA and 30 µA
<
Changed V
Replaced Package Name column with Package Diagram in the Ordering
DDQ
VDD
to V
< VDD in page #18
DDQ
Information table
Updated the Ordering Information Table
(Corrected the ball name for H9 to V
Added the Maximum Rating for Supply Voltage on V
Changed t
AC Switching Characteristics table.
, t
from 25 ns to 20 ns and t
TH
TL
from V
SS
SSQ
from 5 ns to 10 ns in TAP
TDOV
Updated the Ordering Information table.
).
Relative to GND.
DDQ
Document #: 38-05289 Rev. *I Page 29 of 29
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