• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• 3.3V power supply
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN
) pin to suspend operation
• Synchronous self-timed writes
• CY7C1460AV33, CY7C1462AV33 available in
JEDEC-standard lead-free 100-pin TQFP, lead-free and
non-lead-free 165-ball FBGA package. CY7C1464AV33
available in lead-free and non-lead-free 209-ball FBGA
package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Logic Block Diagram-CY7C1460AV33 (1M x 36)
A0, A1, A
MODE
CLK
C
EN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
Functional Description
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are
3.3V , 1M x 36/2M x 18/512K x72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back
Read/Write operations with no wait states. The
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are
equipped with the advanced (NoBL) logic requi red to enable
consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
–BWh for CY7C1464AV33, BWa–BWd for
(BW
a
CY7C1460AV33 and BW
Write Enable (WE
) input. All writes are conducted with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
A1'
A0'
Q0
–BWb for CY7C1462AV33) and a
a
, CE2, CE3) and an
1
) provide for easy bank
) signal,
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
Cypress Semiconductor Corporation•198 Champion Court•San Jose, CA 95134-1709•408-943-2600
Document #: 38-05353 Rev. *D Revised June 22, 2006
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
I
M
S
T
P
E
S
R
S
E
E
REGISTER 0
INPUT
O
D
U
T
A
P
T
U
A
T
B
S
T
E
E
R
I
N
G
E
DQs
U
DQP
F
DQP
F
DQP
E
DQP
R
S
E
[+] Feedback
a
b
C
C
s
P
a
P
b
P
c
P
d
P
e
P
f
P
g
P
h
C
C
Logic Block Diagram-CY7C1462AV33 (2M x 18)
A0, A1, A
MODE
C
LK
EN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
A1'
A0'
Q0
ADV/LD
BW
BW
ZZ
a
b
WE
OE
CE1
CE2
CE3
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
Sleep
Control
Logic Block Diagram-CY7C1464AV33 (512K x 72)
A0, A1, A
MODE
C
LK
EN
ADV/LD
BW
a
BW
b
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1
A0
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
D1D0Q1
BURST
LOGIC
Q0
WRITE
DRIVERS
A1'
A0'
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
E
MEMORY
ARRAY
INPUT
REGISTER 1
O
U
T
P
S
U
E
T
N
S
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
REGISTER 0
S
E
N
S
E
A
M
P
S
E
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
D
A
T
A
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
O
U
T
P
U
T
B
DQs
U
F
DQP
F
DQP
E
R
S
E
E
O
U
T
P
D
U
A
T
T
A
B
DQ
U
S
F
T
E
E
R
I
N
G
DQ
F
DQ
E
R
DQ
S
DQ
DQ
E
DQ
DQ
DQ
E
OE
CE1
CE2
CE3
ZZ
Selection Guide
Maximum Access Time2.63.23.4ns
Maximum Operating Current475425375mA
Maximum CMOS Standby
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
, BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and
DQP
b
DQP
, BWf controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and
e
DQP
.
h
controls DQa and DQPa, BWb controls DQb and
a
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address coun ter or load a new
address. When HIGH (and CEN
is asserted LOW) the internal burst counter is advanced.
When LOW, a new address can be loaded into the device for an access. After being
deselected, ADV/LD should be driven LOW in order to load a new address.
[+] Feedback
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Pin Definitions (continued)
Pin NameI/O TypePin Description
CLKInput-
Clock
CE
CE
CE
OE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CEN
Input-
Synchronous
DQ
a
DQ
b
DQ
c
DQ
d
DQ
e
DQ
f
DQ
g
DQ
h
DQP
DQP
a,
DQPc,DQP
DQPe,DQP
DQPg,DQP
b,
d
f
h
I/O-
Synchronous
I/O-
Synchronous
MODEInput Strap PinMode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst
TDOJTAG serial output
Synchronous
TDIJTAG serial input
Synchronous
TMST est Mode Select
Synchronous
TCKJTAG-ClockClock input to the JTAG circuitry.
V
V
V
DD
DDQ
SS
Power SupplyPower supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
GroundGround for the device. Should be connected to ground of the system.
NCN/ANo connects. This pin is not connected to the die.
NC/72MN/ANot connected to the die. Can be tied to any voltage level.
NC/144MN/ANot connected to the die. Can be tied to any voltage level.
NC/288MN/ANot connected to the die. Can be tied to any voltage level.
NC/576MN/ANot connected to the die. Can be tied to any voltage level.
NC/1GN/ANot connected to the die. Can be tied to any voltage level.
ZZInput-
Asynchronous
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN
. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE3 to select/deselect the device.
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE2 to select/deselect the device.
1
Output Enable, active LOW . Combined with the synchronous logic block inside the device
to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE
masked during the data portion of a write sequence, during the first clock when emerging
from a deselected state and when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by
the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
does not deselect the device, CEN
can be used to extend the previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
direction of the pins is controlled by OE
LOW, the pins can behave as outputs. When HIGH, DQ
condition. The outputs are automatically tri-stated during the data portion of a write
during the previous clock rise of the read cycle. The
X
and the internal control logic. When OE is asserted
–DQd are placed in a tri-state
a
sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ
During write sequences, DQP
controlled by BW
controlled by BW
, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is
c
, DQPg is controlled by BWg, DQPh is controlled by BWh.
f
is controlled by BWa, DQPb is controlled by BWb, DQPc is
a
.
[31:0]
order. Pulled LOW selects the linear burst order. MODE should not change states during
operation. When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
This pin controls the Test Access Port state machine. Sampled on the rising edge of
TCK.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved. During normal operation, this pin can be connected
or left floating. ZZ pin has an internal pull-down.
to V
SS
is
.
Document #: 38-05353 Rev. *DPage 6 of 27
[+] Feedback
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Functional Overview
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are
synchronous-pipelined Burst NoBL SRAMs desig ned specifically to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN
). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
) is 2.6 ns (250-MHz device).
CO
Accesses can be initiated by asserting all three Chip Enables
(CE
, CE2, CE3) active at the rising edge of the clock. If Clock
1
Enable (CEN
) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE
conduct byte write operations.
Write operations are qualified by the Write Enable (WE
). BW
can be used to
[x]
). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and (4) ADV/LD is asserted
is asserted LOW, (2) CE1, CE2,
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.6 ns
(250-MHz device) provided OE
is active LOW. After the first
clock of the read access the output buffers are controlled by
OE
and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will tri-state following the
next clock rise.
Burst Read Accesses
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 have
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four Reads without
reasserting the address inputs. ADV/LD
must be driven LOW
in order to load a new address into the SRAM, as described in
the Single Read Access section above. The sequence of the
burst counter is determined by the MODE input signal. A LOW
input on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and
A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD
will increment
the internal burst counter regardless of the state of chip
enables inputs or WE
. WE is latched at the beginning of a burst
cycle. Therefore, the type of access (Read or Write) is
maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address inputs
are ALL asserted active, and (3) the write signal WE
3
is asserted LOW, (2) CE1, CE2,
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
allows the external logic to present the data on DQ
(DQ
a,b,c,d,e,f,g,h
DQ
a,b,c,d
for CY7C1462AV33). In addition, the address for the subse-
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1460AV33 and DQ
a,b,c,d
for CY7C1464AV33,
input signal. This
and DQP
/DQP
a,b
a,b
quent access (Read/Write/Deselect) is latched into the
Address Register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1460AV33 & DQ
a,b,c,d
(DQ
a,b,c,d,e,f,g,h
DQ
a,b,c,d
CY7C1462AV33) (or a subset for byte write operations, see
for CY7C1464AV33,
a,b
/DQP
and DQP
a,b
for
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
The data written during the Write operation is controlled by BW
(BW
a,b,c,d,e,f,g,h
CY7C1460AV33 and BW
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 provides
for CY7C1464AV33, BW
for CY7C1462AV33) signals. The
a,b
a,b,c,d
for
byte write capability that is described in the Write Cycle
Description table. Asserting the Write Enable input (WE
the selected Byte Write Select (BW
) input will selectively write
) with
to only the desired bytes. Bytes not selected during a byte
write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations. Byte write capability has been included in
order to greatly simplify Read/Modify/Write sequences, which
can be reduced to simple byte write operations.
Because the
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE
deasserted HIGH before presenting data to the DQ
(DQ
a,b,c,d,e,f,g,h
DQ
a,b,c,d
for CY7C1462AV33) inputs. Doing so will tri-state the output
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1460AV33 and DQ
a,b,c,d
for CY7C1464AV33,
drivers. As a safety precaution, DQ
(DQ
a,b,c,d,e,f,g,h
DQ
a,b,c,d
for CY7C1462AV33) are automatically tri-stated during the
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1460AV33 and DQ
a,b,c,d
for CY7C1464AV33,
data portion of a write cycle, regardless of the state of OE
) can be
and DQP
/DQP
a,b
and DQP
/DQP
a,b
a,b
a,b
.
Burst Write Accesses
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 has
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD
must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD
is
driven HIGH on the subsequent clock rise, the chip enables
(CE
, CE2, and CE3) and WE inputs are ignored and the burst
1
Document #: 38-05353 Rev. *DPage 7 of 27
[+] Feedback
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
counter is incremented. The correct BW (BW
CY7C1464AV33, BW
CY7C1462AV33) inputs must be driven in each cycle of the
for CY7C1460AV33 and BW
a,b,c,d
a,b,c,d,e,f,g,h
a,b
for
for
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
Second
Address
DD
)
Third
Address
A1,A0A1,A0A1,A0A1,A0
00011011
01001110
10110001
11100100
Fourth
Address
guaranteed. The device must be deselected prior to e ntering
the “sleep” mode. CE
for the duration of t
ZZ active to sleep currentThis parameter is sampled2t
ZZ Inactive to exit sleep currentThis parameter is sampled0ns
[1, 2, 3, 4, 5, 6, 7]
Address
UsedCEZZADV/LDWEBW
OECENCLKDQ
x
NoneXLHXXXLL-HTri-State
ExternalLLLHXLLL-HData Out (Q)
NextXLHXXLLL-HData Out (Q)
ExternalLLLHXHLL-HTri-State
NextXLHXXHLL-HTri-State
CYC
CYC
ns
ns
ns
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE
= H inserts wait states.
5. CEN
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Tri-state when OE
7. OE
is inactive or when the device is deselected, and DQ
and BWX. See Write Cycle Description table for details.
Document #: 38-05353 Rev. *DPage 8 of 27
stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx =
signal.
.
=data when OE is active.
s
[+] Feedback
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Truth Table
[1, 2, 3, 4, 5, 6, 7]
(continued)
Address
Operation
Write Cycle
UsedCEZZADV/LDWEBW
OECENCLKDQ
x
ExternalLLLLLXLL-HData In (D)
(Begin Burst)
Write Cycle
NextXLHXLXLL-HData In (D)
(Continue Burst)
NOP/WRITE ABORT
NoneLLLLHXLL-HTri-State
(Begin Burst)
WRITE ABORT
NextXLHXHXLL-HTri-State
(Continue Burst)
IGNORE CLOCK
CurrentXLXXXXHL-HEDGE
(Stall)
SLEEP MODENoneXHXXXXXXTri- State
Partial Write Cycle Description
Function (CY7C1460AV33)WEBW
[1, 2, 3, 8]
d
BW
c
BW
b
BW
a
ReadHXXXX
Write – No bytes writtenLHHHH
Write Byte a – (DQa and DQPa)LHHHL
Write Byte b – (DQb and DQPb)LHHLH
Write Bytes b, aLHHLL
Write Byte c – (DQc and DQPc)LHLHH
Write Bytes c, aLHLHL
Write Bytes c, bLHLLLH
Write Bytes c, b, aLHLLL
Write Byte d – (DQd and DQPd)LLHHH
Write Bytes d, aLLHHL
Write Bytes d, bLLHLH
Write Bytes d, b, aLLHLL
Write Bytes d, cLLLHH
Write Bytes d, c, aLLLHL
Write Bytes d, c, bLLLLH
Write All BytesLLLLL
Function (CY7C1462AV33)
[2,8]
WEBW
b
BW
a
ReadHxx
Write – No Bytes WrittenLHH
Write Byte a – (DQa and DQPa)LHL
Write Byte b – (DQb and DQPb)LLH
Write Both Bytes LLL
Function (CY7C1464AV33)
ReadHx
Write – No Bytes WrittenLH
Write Byte X − (DQ
and DQP
x
x)
Write All Bytes LAll BW = L
Note:
8. Table only lists a partial listing o f the byte write combinations. Any combination of B W
Document #: 38-05353 Rev. *DPage 9 of 27
[2,8]
WEBW
LL
is valid. Appropriate write will be done based on which byte write is active.
[a:d]
x
[+] Feedback
CY7C1460AV33
T
O
CY7C1462AV33
CY7C1464AV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 incorporates a serial boundary scan test access port (TAP). This
part is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic level.
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V
) to prevent clocking of the device. TDI and TMS are inter-
SS
nally pulled up and may be unconnected. They may alternately
be connected to V
left unconnected. Upon power-up, the device will come up in
through a pull-up resistor. TDO should be
DD
a reset state which will not interfere with the operation of the
device.
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
11
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
00
EXIT2-DR
UPDATE-DR
10
1
0
0
00
1
11
00
0
1
1
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
SELECT
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the T AP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
1
0
0
1
0
1
1
0
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
012
TDITD
TCK
MSTAP CONTROLLER
Selection
Circuitry
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO bal l on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Instruction Register
012293031...
Identification Register
012..x...
Boundary Scan Register
S
election
Circuitr
y
Document #: 38-05353 Rev. *DPage 10 of 27
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When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be pla ced betwee n the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V
) when the BYPASS instruction is executed.
SS
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of th e Boundary
Scan Register for the SRAM in different packages is listed in
the Scan Register Sizes table.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next comman d is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1 149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (t
captured correctly if there is no way in a design to stop (o r
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
(for 165-FBGA package) or bit #138 (for 209-FBGA package).
and tCH). The SRAM clock input might not be
CS
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When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR,” the value
TAP Timing
Test Clock
(TCK)
est Mode Select
(TMS)
Test Data-In
(TDI)
Test Data-Out
(TDO)
t
TMSS
t
TDIS
t
TH
t
TMSH
t
TDIH
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Test load termination supply voltage ............................ 1.25V
2.5V TAP AC Output Load Equivalent
1.25V
50Ω
DO
Z = 50Ω
O
20p
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)
ParameterDescriptionTest ConditionsMin.Max.Unit
V
V
V
V
V
V
I
OH1
OH2
OL1
OL2
IH
IL
X
Output HIGH Voltage IOH = –4.0 mA, V
I
= –1.0 mA, V
OH
Output HIGH Voltage IOH = –100 µAV
Output LOW VoltageIOL = 8.0 mAV
I
= 1.0 mAV
OL
Output LOW VoltageIOL = 100 µAV
Input HIGH VoltageV
Input LOW VoltageV
Input Load CurrentGND < VIN < V
[11]
= 3.3V2.4V
DDQ
= 2.5V2.0V
DDQ
= 3.3V2.9V
DDQ
V
= 2.5V2.1V
DDQ
= 3.3V0.4V
DDQ
= 2.5V0.4V
DDQ
= 3.3V0.2V
DDQ
V
= 2.5V0.2V
DDQ
= 3.3V2.0VDD + 0.3V
DDQ
V
= 2.5V1.7VDD + 0.3V
DDQ
= 3.3V–0.30.8V
DDQ
V
= 2.5V–0.30.7V
DDQ
DDQ
–55µA
Identification Register Definitions
Instruction Field
Revision Number (31:29)000000000Describes the version number.
Device Depth (28:24)
[12]
Architecture/Memory Type(23:18)001000001000001000Defines memory type and archi-
Bus Width/Density(17:12)100111010111110111Defines width and density
Cypress JEDEC ID Code (11:1)000001101000000011010000000110100Allows unique identification of
ID Register Presence Indicator (0)111Indicates the presence of an ID
Notes:
11.All voltages referenced to V
12.Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Instruction333
Bypass111
ID323232
Boundary Scan Order (165-ball FBGA package)8989Boundary Scan Order (209-ball FBGA package)--138
Identification Codes
InstructionCodeDescription
EXTEST000Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
IDCODE001Loads the ID register with the vendor ID code and places the register between TDI and
SAMPLE Z010Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
RESERVED011Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD100Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
RESERVED101Do Not Use: This instruction is reserved for future use.
RESERVED110Do Not Use: This instruction is reserved for future use.
BYPASS111Places the bypass register between TDI and TDO. This operation does not affect SRAM
Forces all SRAM outputs to High-Z state.
TDO. This operation does not affect SRAM operations.
T est conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA/JESD51.
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
= 50Ω
Z
0
R
L
VT= 1.5V
(a)(b)
2.5V I/O Test Load
OUTPUT
= 50Ω
Z
0
= 1.25V
V
T
R
L
(a)(b)
Note:
17.Tested initially and after any design or process changes that may affect these parameters.
3.3V
OUTPUT
= 50Ω
5pF
INCLUDING
JIG AND
SCOPE
2.5V
OUTPUT
= 50Ω
5pF
INCLUDING
JIG AND
SCOPE
R = 317Ω
R = 351Ω
R = 1667Ω
R =1538Ω
100 TQFP
Max.
165 FBGA
Max.
209 FBGA
Max.Unit
6.575pF
100 TQFP
Package
165 FBGA
Package
209 FBGA
PackageUnit
25.2120.825.31°C/W
2.283.24.48°C/W
V
DDQ
GND
≤ 1 ns
ALL INPUT PULSES
10%
90%
90%
10%
(c)
V
GND
DDQ
≤ 1 ns
ALL INPUT PULSES
10%
90%
90%
10%
(c)
≤ 1 ns
≤ 1 ns
Document #: 38-05353 Rev. *DPage 18 of 27
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Switching Characteristics Over the Operating Range
ParameterDescription
[18]
t
Power
Clock
t
CYC
F
MAX
t
CH
t
CL
Output Times
t
CO
t
EOV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Set-up Times
t
AS
t
DS
t
CENS
t
WES
t
ALS
t
CES
Hold Times
t
AH
t
DH
t
CENH
t
WEH
t
ALH
t
CEH
VCC (typical) to the first access read or write111ms
Clock Cycle Time4.05.06.0ns
Maximum Operating Frequency250200167MHz
Clock HIGH1.52.02.4ns
Clock LOW1.52.02.4ns
Data Output Valid After CLK Rise2.63.23.4ns
OE LOW to Output Valid2.63.03.4ns
Data Output Hold After CLK Rise1.01.51.5ns
Clock to High-Z
Clock to Low-Z
OE
HIGH to Output High-Z
OE LOW to Output Low-Z
[19, 20, 21]
[19, 20, 21]
[19, 20, 21]
[19, 20, 21]
Address Set-up Before CLK Rise1.21.41.5ns
Data Input Set-up Before CLK Rise1.21.41.5ns
CEN Set-up Before CLK Rise1.21.41.5ns
WE, BWx Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise1.21.41. 5ns
Chip Select Set-up1.21.41.5ns
Address Hold After CLK Rise0.30.40.5ns
Data Input Hold After CLK Rise0.30.40.5ns
CEN Hold After CLK Rise0.30.40.5ns
WE, BWx Hold After CLK Rise0.30.40.5ns
ADV/LD Hold after CLK Rise0.30.40.5ns
Chip Select Hold After CLK Rise0.30.40.5ns
[22, 23]
–250–200–167
UnitMin.Max.Min.Max.Min.Max.
2.63.03.4ns
1.01.31.5ns
2.63.03.4ns
000ns
1.21.41.5ns
Notes:
18.This part has a voltage regulator internally; tpower is the time power needs to be supplied above V dd minimum initially, before a Read or Wri te operation can be
initiated.
, t
, t
19.t
CHZ
CLZ
20.At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition , bu t re flect p arame te rs g uara nteed over worst case user co ndit ions. Device is designe d
to achieve High-Z prior to Low-Z under the same system conditions.
21.This parameter is sampled and not 100% tested.
22.Timing reference is 1.5V when V
23.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
EOLZ
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-sta te voltage.
EOHZ
EOHZ
3.3V and is 1.25V when V
DDQ=
Document #: 38-05353 Rev. *DPage 19 of 27
is less than t
EOLZ
and t
DDQ=
is less than t
CHZ
2.5V.
to eliminate bus contention between SRAMs when sharing the same
CLZ
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Switching Waveforms
CLK
CEN
CE
ADV/LD
WE
BW
Data
OE
[24, 25, 26]
t
CENS
t
CES
x
A1A2
t
AS
WRITE
D(A1)
Read/Write/Timing
ADDRESS
n-Out (DQ)
t
CENH
t
CEH
t
AH
WRITE
D(A2)
t
CYC
t
t
CL
CH
A3
t
t
DH
DS
D(A1)D(A2)D(A5)Q(A4)Q(A3)
BURST
WRITE
D(A2+1)
READ
Q(A3)
A4
t
CO
t
D(A2+1)
READ
Q(A4)
CLZ
t
BURST
READ
Q(A4+1)
A5A6A7
WRITE
D(A5)
t
OEV
t
OELZ
DOH
t
OEHZ
t
Q(A4+1)
t
DOH
READ
Q(A6)
CHZ
WRITE
D(A7)
Q(A6)
DESELECT
DON’T CAREUNDEFINED
Notes:
24.For this waveform ZZ is tied low.
25.When CE
26.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.
is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
visit www.cypress.com for actual products offered.
Package
DiagramPart and Package Type
Operating
Range
Document #: 38-05353 Rev. *DPage 23 of 27
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Package Diagrams
R 0.08 MIN.
0.20 MAX.
0.25
GAUGE PLANE
0°-7°
0.60±0.15
1.00 REF.
20.00±0.10
22.00±0.20
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
14.00±0.10
100
1
30
3150
0° MIN.
R 0.08 MIN.
0.20 MAX.
0.20 MIN.
A
DETAIL
81
80
0.30±0.08
0.65
TYP.
51
STAND-OFF
0.05 MIN.
0.15 MAX.
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
1.40±0.05
12°±1°
(8X)
SEATING PLANE
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
51-85050-*B
SEE DETAIL
0.20 MAX.
1.60 MAX.
0.10
A
Document #: 38-05353 Rev. *DPage 24 of 27
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Package Diagrams (continued)
TOP VIEW
PIN 1 CORNER
165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)
1110986754321
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
11
Ø0.45±0.05(165X)
PIN 1 CORNER
1
2345678910
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
+0.05
0.25 C
0.53±0.05
SEATING PLANE
C
0.36
0.35
-0.10
0.15 C
1.40 MAX.
17.00±0.10
A
14.00
0.15(4X)
1.00
7.00
5.00
B
15.00±0.10
1.00
10.00
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
51-85165-*A
Document #: 38-05353 Rev. *DPage 25 of 27
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Package Diagrams (continued)
209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
ZBT is a registered trademark of Integrated Device Technology, Inc. No Bus Latency and NoBL are trademarks of Cypress
Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders.
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
51-85167-**
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Document History Page
Document Title: CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM
with NoBL™ Architecture
Document Number: 38-05353
REV.ECN No. Issue Date
**254911See ECNSYTNew Data sheet
*A303533See ECNSYTChanged H9 pin from V
*B331778See ECNSYTModified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA
*C417509See ECNRXUConverted from Preliminary to Final
*D473229See ECNNXRAdded the Maximum Rating for Supply Voltage on V
Orig. of
ChangeDescription of Change
Part number changed from previous revision. New and old part number differ
by the letter “A”
to VSS on the Pin Configuration table for 209
FBGA on Page # 5
SSQ
Changed the test condition from VDD = Min to VDD = Max for VOL in the
Electrical Characteristics table
Replaced Θ
Packages on the Thermal Resistance Table
Changed I
and 167 MHz respectively
Changed I
MHz respectively
Changed I
Changed I
respectively
Changed I
Changed C
Package
Changed tCO from 3.0 to 3.2 ns and t
Speed Bin
and Θ
JA
from 450, 400 & 350 mA to 475, 425 & 375 mA for 250, 200
DD
from 190, 180 and 170 mA to 225 mA for 250, 200 and 167
SB1
from 80 mA to 100 mA for all frequencies
SB2
from 180, 170 & 160 mA to 200 mA for 250, 200 and 167 MHz
SB3
from 100 mA to 110 mA for all frequencies
SB4
, C
IN
CLK
from TBD to respective Thermal Values for All
JC
and C
to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP
I/O
from 1.3 ns to 1.5 ns for 200 MHz
DOH
Added lead-free information for 100-pin TQFP and 165 FBGA and 209 BGA
packages
Package as per JEDEC standards and updated the Pin Definitions accordingly
Modified V
Changed C
Package
OL, VOH
, C
IN
CLK
test conditions
and C
to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA
I/O
Added Industrial Temperature Grade
Changed I
Updated the Ordering Information by Shading and Unshading MPNs as per
SB2
and I
from 100 and 1 10 mA to 120 and 135 mA respectively
SB4
availability
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed I
tively and also Changed I
µA respectively on page# 18
Modified test condition from V
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
current value in MODE from –5 & 30 µA to –30 & 5 µA respec-
X
current value in ZZ from –30 & 5 µA to –5 & 30
X
IH
< V
DD to VIH
< V
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
, t
Changed t
AC Switching Characteristics table
from 25 ns to 20 ns and t
TH
TL
from 5 ns to 10 ns in TAP
TDOV
Updated the Ordering Information table.
DD
Relative to GND
DDQ
Document #: 38-05353 Rev. *DPage 27 of 27
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