Cypress Semiconductor CY7C1443AV33, CY7C1441AV33, CY7C1447AV33 Specification Sheet

36-Mbit (1M x 36/2M x 18/512K x 72)

Flow-Through SRAM

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Features

■ Supports 133-MHz bus operations

■ 1M x 36/2M x 18/512K x 72 common IO

■ 3.3V core power supply

■ 2.5V or 3.3V IO power supply

■ Fast clock-to-output times
❐ 6.5 ns (133-MHz version)

■ Provide high-performance 2-1-1-1 access rate

■ User-selectable burst counter supporting Intel® Pentium®

interleaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self-timed write

■ Asynchronous output enable

■ CY7C1441AV33, CY7C1443AV33 available in

JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and
non-lead-free 165-ball FBGA package. CY7C1447AV33
available in Pb-free and non-lead-free 209-ball FBGA package

■ IEEE 1149.1 JTAG-Compatible Boundary Scan

■ “ZZ” Sleep Mode option

Selection Guide

Functional Description

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33

3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through
SRAMs, respectively designed to interface with high-speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133-MHz version). A 2-bi t on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE
CE

), Burst Control inputs (ADSC, ADSP, and ADV), Write

3

Enables (BW
Asynchronous inputs include the Output Enable (OE
pin.

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows
either interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst sequence,
while a LOW selects a linear burst sequence. Burst accesses
can be initiated with the Processor Address Strobe (ADSP
cache Controller Address Strobe (ADSC
advancement is controlled by the Address Advancement (ADV
input.

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (A DSP
Strobe Controller (ADSC
addresses can be internally generated as controlled by the
Advance pin (ADV

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
operates from a +3.3V core power supply while all outputs may
operate with either a +2.5 or +3.3V supply. All inputs and outputs
are JEDEC-standard JESD8-5-compatible.

), depth-expansion Chip Enables (CE2 and

1

, and BWE), and Global Write (GW).

x

) inputs. Address

) are active. Subsequent burst

).

[1]

are

) and the ZZ

) or the

) or Address

)

Description 133 MHz 100 MHz Unit

Maximum Access Time 6.5 8.5 ns
Maximum Operating Current 310 290 mA
Maximum CMOS Standby Current 120 120 mA

Note

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05357 Rev. *G Revised May 09, 2008

[+] Feedback

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Logic Block Diagram – CY7C1441AV33 (1M x 36)

ADDRESS
REGISTER

BURST

COUNTER

AND LOGIC

CLR

Q1

Q0

ENABLE

REGISTER

SENSE
AMPS

OUTPUT
BUFFERS

INPUT

REGISTERS

MEMORY

ARRAY

MODE

A

[1:0]

ZZ

DQ s

DQP

A

DQP

B

DQP

C

DQP

D

A0, A1, A

ADV

CLK

ADSP

ADSC

BW

D

BW

C

BW

B

BW

A

BWE

CE1

CE2

CE3

OE

GW

SLEEP

CONTROL

DQ

A

,

DQP

A

BYTE

WRITE REGISTER

DQ

B

,

DQP

B

BYTE

WRITE REGISTER

DQ

C

,

DQP

C

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

DQ

D

,

DQP

D

BYTE

WRITE REGISTER

DQ

D

,

DQP

D

BYTE

WRITE REGISTER

DQ

C

,

DQP

C

BYTE

WRITE REGISTER

DQ

B

,

DQP

B

BYTE

WRITE REGISTER

DQ

A

,

DQP

A

BYTE

WRITE REGISTER

ADDRESS
REGISTER

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

Q1

Q0

ADSC

CE

1

OE

SENSE
AMPS

MEMORY

ARRAY

ADSP

OUTPUT
BUFFERS

INPUT

REGISTERS

MODE

CE

2

CE

3

GW

BWE

A

0,A1,A

BW

B

BW

A

DQB,DQP

B

WRITE REGISTER

DQ

A

,DQP

A

WRITE REGISTER

ENABLE

REGISTER

A[1:0]

DQs
DQP

A

DQP

B

DQB,DQP

B

WRITE DRIVER

DQ

A

,DQP

A

WRITE DRIVER

SLEEP

CONTROL

ZZ

Logic Block Diagram – CY7C1443AV33 (2Mx 18)

Document #: 38-05357 Rev. *G Page 2 of 31

[+] Feedback

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Logic Block Diagram – CY7C1447AV33 (512K x 72)

BW

D

BW

C

BW

B

BW

A

BWE

GW

CE1
CE2
CE3

OE

ENABLE

REGISTER

ADDRESS
REGISTER

ADV

CLK

BURST

COUNTER

AND LOGIC

CLR

Q1

Q0

ADSP

ADSC

MODE

A0, A1,A

A[1:0]

BW

F

BW

E

BW

H

BW

G

OUTPUT
BUFFERS

DQA, DQP

A

WRITE DRIVER

DQB, DQP

B

WRITE DRIVER

DQC, DQP

C

WRITE DRIVER

DQD, DQP

D

WRITE DRIVER

BYTE

“a”

WRITE DRIVER

DQE, DQP

E

WRITE DRIVER

DQF, DQP

F

WRITE DRIVER

DQG, DQP

G

WRITE DRIVER

DQH, DQP

H

WRITE DRIVER

MEMORY

ARRAY

SENSE
AMPS

SLEEP

CONTROL

ZZ

INPUT

REGISTERS

DQs
DQP

A

DQP

B

DQP

C

DQP

D

DQP

E

DQP

F

DQP

G

DQP

H

DQA, DQP

A

WRITE REGISTER

DQB, DQP

B

WRITE REGISTER

DQC, DQP

C

WRITE REGISTER

DQD, DQP

D

WRITE REGISTER

DQE, DQP

E

WRITE REGISTER

DQF, DQP

F

WRITE REGISTER

DQF, DQP

F

WRITE REGISTER

DQH, DQP

H

WRITE REGISTER

Document #: 38-05357 Rev. *G Page 3 of 31

[+] Feedback

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

AAA

A

A

1A0

NC/72M

A

V

SS

V

DD

A

AAAAA

A

A

DQP

B

DQ

B

DQ

B

V

DDQ

V

SSQ

DQ

B

DQ

B

DQ

B

DQ

B

V

SSQ

V

DDQ

DQ

B

DQ

B

V

SS

NC
V

DD

ZZ
DQ

A

DQ

A

V

DDQ

V

SSQ

DQ

A

DQ

A

DQ

A

DQ

A

V

SSQ

V

DDQ

DQ

A

DQ

A

DQP

A

DQP

C

DQ

C

DQ

C

V

DDQ

V

SSQ

DQ

C

DQ

C

DQ

C

DQ

C

V

SSQ

V

DDQ

DQ

C

DQ

C

V

DD

NC

V

SS

DQ

D

DQ

D

V

DDQ

V

SSQ

DQ

D

DQ

D

DQ

D

DQ

D

V

SSQ

V

DDQ

DQ

D

DQ

D

DQP

D

A

A

CE

1CE2

BWD

BWC

BWB

BWA

CE3VDDV

SS

CLKGWBWEOEADSC

ADSP

ADV

A

A

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100999897969594939291908988878685848382

81

MODE

CY7C1441AV33

(1Mx 36)

NC

AAA

A

A

1A0

NC/72M

A

V

SS

V

DD

A

AAAAA

A

A

A
NC
NC
V

DDQ

V

SSQ

NC
DQP

A

DQ

A

DQ

A

V

SSQ

V

DDQ

DQ

A

DQ

A

V

SS

NC
V

DD

ZZ
DQ

A

DQ

A

V

DDQ

V

SSQ

DQ

A

DQ

A

NC
NC
V

SSQ

V

DDQ

NC
NC
NC

NC
NC
NC

V

DDQ

V

SSQ

NC
NC

DQ

B

DQ

B

V

SSQ

V

DDQ

DQ

B

DQ

B

V

DD

NC

V

SS

DQ

B

DQ

B

V

DDQ

V

SSQ

DQ

B

DQ

B

DQP

B

NC

V

SSQ

V

DDQ

NC
NC
NC

A

A

CE

1CE2

NCNCBWBBWA

CE3VDDV

SS

CLKGWBWEOEADSC

ADSP

ADV

A

A

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100999897969594939291908988878685848382

81

MODE

CY7C1443AV33

(2M x 18)

NC

A

A

Pin Configurations

Figure 1. 100-Pin TQFP Pinout

Document #: 38-05357 Rev. *G Page 4 of 31

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Pin Configurations (continued)

165-ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1441AV33 (1M x 36)

2345671
A
B
C
D
E

F
G
H

J
K

L

M

N
P

R

TDO

NC/288M
NC/144M

DQP

C

DQ

C

DQP

D

NC

DQ

D

CE

1

BW

B

CE

3

BW

C

BWE

A

CE

2

DQ

C

DQ

D

DQ

D

MODE

NC

DQ

C

DQ

C

DQ

D

DQ

D

DQ

D

A

NC/72M

V

DDQ

BW

D

BW

A

CLK

GW

V

SS

V

SS

V

SS

V

SS

V

DDQ

V

SS

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A
A

V

DD

V

SS

V

DD

V

SS

V

SS

V

DDQ

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

SS

V

SS

V

DD

V

DD

V

SS

V

DD

V

SS

V

SS

NC

TCK

V

SS

TDI

A

A

DQ

C

V

SS

DQ

C

V

SS

DQ

C

DQ

C

NC

V

SS

V

SS

V

SS

V

SS

NC

V

SS

A1

DQ

D

DQ

D

NC

NC

V

DDQ

V

SS

TMS

891011

A

ADV

AADSC

NC

OE ADSP

A

NC/576M

V

SS

V

DDQ

NC/1G DQP

B

V

DDQ

V

DD

DQ

B

DQ

B

DQ

B

NC

DQ

B

NC

DQ

A

DQ

A

V

DD

V

DDQ

V

DD

V

DDQ

DQ

B

V

DD

NC

V

DD

DQ

A

V

DD

V

DDQ

DQ

A

V

DDQ

V

DD

V

DD

V

DDQ

V

DD

V

DDQ

DQ

A

V

DDQ

AA

V

SS

A

A

A

DQ

B

DQ

B

DQ

B

ZZ

DQ

A

DQ

A

DQP

A

DQ

A

A

V

DDQ

A

CY7C1443AV33 (2M x 18)

A0

A

V

SS

234 5671

A
B
C

D
E

F

G

H

J

K

L

M

N
P

R

TDO

NC/288M
NC/144M

NC
NC

DQP

B

NC

DQ

B

ACE

1

NC

CE

3

BW

B

BWE

A

CE

2

NC

DQ

B

DQ

B

MODE

NC

DQ

B

DQ

B

NC

NC

NC

A

NC/72M

V

DDQ

NC BW

A

CLK

GW

V

SS

V

SS

V

SS

V

SS

V

DDQ

V

SS

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A
A

V

DD

V

SS

V

DD

V

SS

V

SS

V

DDQ

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

SS

V

SS

V

DD

V

DD

V

SS

V

DD

V

SS

V

SS

NC

TCKA0

V

SS

TDI

A

A

DQ

B

V

SS

NC V

SS

DQ

B

NC

NC

V

SS

V

SS

V

SS

V

SS

NC

V

SS

A1

DQ

B

NC

NC

NC

V

DDQ

V

SS

TMS

891011

A

ADV

AADSC

A

OE ADSP

A

NC/576M

V

SS

V

DDQ

NC/1G DQP

A

V

DDQ

V

DD

NC

DQ

A

DQ

A

NC

NC

NC

DQ

A

NC

V

DD

V

DDQ

V

DD

V

DDQ

DQ

A

V

DD

NC

V

DD

NC

V

DD

V

DDQ

DQ

A

V

DDQ

V

DD

V

DD

V

DDQ

V

DD

V

DDQ

NC

V

DDQ

AA

V

SS

A

A

A

DQ

A

NC

NC

ZZ

DQ

A

NC

NC

DQ

A

A

V

DDQ

A

A

A

Document #: 38-05357 Rev. *G Page 5 of 31

[+] Feedback

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Pin Configurations (continued)

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W

123456789 1110

DQ

G

DQ

G

DQ

G

DQ

G

DQ

G

DQ

G

DQ

G

DQ

G

DQ

C

DQ

C

DQ

C

DQ

C

NC

DQP

G

DQ

H

DQ

H

DQ

H

DQ

H

DQ

D

DQ

D

DQ

D

DQ

D

DQP

D

DQP

C

DQ

C

DQ

C

DQ

C

DQ

C

NC

DQ

H

DQ

H

DQ

H

DQ

H

DQP

H

DQ

D

DQ

D

DQ

D

DQ

D

DQ

B

DQ

B

DQ

B

DQ

B

DQ

B

DQ

B

DQ

B

DQ

B

DQ

F

DQ

F

DQ

F

DQ

F

NC

DQP

F

DQ

A

DQ

A

DQ

A

DQ

A

DQ

E

DQ

E

DQ

E

DQ

E

DQP

A

DQP

B

DQ

F

DQ

F

DQ

F

DQ

F

NC

DQ

A

DQ

A

DQ

A

DQ

A

DQP

E

DQ

E

DQ

E

DQ

E

DQ

E

A

ADSP

ADV

A

NC

NC

NC/72M

AA A

A

AA

AA

A

A1
A0

A

AA

AA

A

NC/144M

NC288M

NC/576M

GW

NC

NC

BWS

B

BWS

F

BWS

E

BWS

A

BWS

C

BWS

G

BWS

D

BWS

H

TMS

TDI TDO TCK

NC

NC MODE

NC

V

SS

V

SS

NC

CLK

NC

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC/1G

V

DD

NC

OE

CE

3

CE

1

CE

2

ADSC

BW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

ZZ

V

SS

V

SS

V

SS

V

SS

NC

V

DDQ

V

SS

V

SS

NC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

V

SS

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

209-ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1447AV33 (512K × 72)

Document #: 38-05357 Rev. *G Page 6 of 31

[+] Feedback

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Pin Definitions

Name IO Description

, A1, A Input-

A

0

, BW

BW

A

, BWF,

E

, BW

G

B

H

BWC, BWD,
BW
BW

GW Input-

CLK Input-

CE

1

CE

2

CE

3

OE Input-

ADV Input-

ADSP

ADSC

BWE

ZZ Input-

Synchronous

Input-

Synchronous

Synchronous

Clock

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Asynchronous

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Asynchronous

Address Inputs Used to Select One of the Address Locations. Sampled
at the rising edge of the CLK if ADSP
and

are sampled active. A

CE3

or ADSC is active LOW, and CE1, CE2,

feed the 2-bit counter.

[1:0]

Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.

Global Write Enable Input, Active LOW. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless
of the values on BWX and BWE).

Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE
ignored if CE
loaded.

is HIGH. CE1 is sampled only when a new external address is

1

and CE3 to select/deselect the device. ADSP is

2

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE
only when a new external address is loaded.

and CE3 to select/deselect the device. CE2 is sampled

1

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE
assumed active throughout this document for BGA. CE
a new external address is loaded.

and CE2 to select/deselect the device. CE3 is

1

is sampled only when

3

Output Enable, Asynchronous Input, Active LOW. Controls the direction
of the IO pins. When LOW, the IO pins behave as outputs. When deasserted
HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during
the first clock of a read cycle when emerging from a deselected state.

Advance Input Signal, Sampled on the Rising Edge of CLK. When
asserted, it automatically increments the address in a burst cycle.

Address Strobe from Processor, Sampled on the Rising Edge of CLK,
Active LOW. When asserted LOW, addresses presented to the device are

captured in the address registers. A
When ADSP
is ignored when

and ADSC are both asserted, only ADSP is recognized. ASDP

CE

is deasserted HIGH

1

are also loaded into the burst counter.

[1:0]

Address Strobe from Controller, Sampled on the Rising Edge of CLK,
Active LOW. When asserted LOW, addresses presented to the device are

captured in the address registers. A
When ADSP

and ADSC are both asserted, only ADSP is recognized

are also loaded into the burst counter.

[1:0]

.

Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK.
This signal must be asserted LOW to conduct a byte write.

ZZ “sleep” Input, Active HIGH. When asserted HIGH places the device in
a non-time-critical “sleep” condition with data integrity preserved. For normal
operation, this pin must be LOW or left floating. ZZ pin has an internal pull
down.

Document #: 38-05357 Rev. *G Page 7 of 31

[+] Feedback

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Pin Definitions (continued)

Name IO Description

DQ

DQP

s

X

IO-

Synchronous

IO-

Synchronous

MODE Input-Static Selects Burst Order. When tied to GND selects linear burst sequence. When

V
V
V
V

DD
DDQ
SS
SSQ

Power Supply Power Supply Inputs to the Core of the Device.

IO Power Supply Power Supply for the IO Circuitry.

Ground Ground for the Core of the Device.

IO Ground Ground for the IO Circuitry.

TDO JTAG serial output

Synchronous

TDI JTAG serial

input

Synchronous

TMS JTAG serial

input

Synchronous

TCK JTAG-Clock Clock Input to the JT AG Ci rcuitry. If the JTAG feature is not being utilized,

NC - No Conn ect s. Not internally connected to the die. 72M, 144M and 288M are

NC/72M, NC/144M,

- No Connects. Not internally connected to the die. NC/72M, NC/144M,
NC/288M, NC/576M
NC/1G

Bidirectional Data IO lines . As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by the addresses presented during
the previous clock rise of the read cycle. The direction of the pins is controlled
by OE

. When OE is asserted LOW, the pins behave as outputs. When HIGH,

DQ

and DQPX are placed in a tri-state condition.The outputs are automati-

s

cally tri-stated during the data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE

.

Bidirectional Data Parity IO Lines. Functionally, these signals are identical
to DQ
ingly.

tied to V
pin and should remain static during device operation. Mode Pin has an internal

During write sequences, DQPx is controlled by BW

s.

or left floating selects interleaved burst sequence. This is a strap

DD

correspond-

[A:H]

pull up.

Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of
TCK. If the JTAG feature is not being utilized, this pin should be left uncon­nected. This pin is not available on TQFP packages.

Serial Data-In to the JT AG Circuit. Sampled on the rising edge of TCK. If
the JTAG feature is not being utilized, this pin can be left floating or connected
to V

through a pull up resistor. This pin is not available on TQFP packages.

DD

Serial Data-In to the JT AG Circuit. Sampled on the rising edge of TCK. If
the JTAG feature is not being utilized, this pin can be disconnected or
connected to V

. This pin is not available on TQFP packages.

DD

this pin must be connected to VSS. This pin is not available on TQFP
packages.

address expansion pins are not internally connected to the die.

NC/288M, NC/576M and NC/1G are address expansion pins are not internally
connected to the die.

Document #: 38-05357 Rev. *G Page 8 of 31

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Functional Overview

All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
supports secondary cache in systems utilizing either a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium and i486™ processors. The linear burst
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user-selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the Processor Address Strobe (ADSP
Address Strobe (ADSC
burst sequence is controlled by the ADV
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.

Byte write operations are qualified with the Byte Write Enable
(BWE

) and Byte Write Select (BWx) inputs. A Global Write
Enable (GW
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
HIGH.

Single Read Accesses

A single read access is initiated when the following condition s
are satisfied at clock rise: (1) CE
active, and (2) ADSP
initiated by ADSC
this first cycle). The address presented to the address i nputs is
latched into the address register and the burst counter/control
logic and presented to the memory core. If the OE
asserted LOW, the requested data is available at the data
outputs a maximum to t
CE

is HIGH.

1

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
and (2) ADSP
loaded into the address register and the burst inputs (GW
and BW
inputs are asserted active (see Write Cycle Descriptions table for
appropriate states that indicate a write) on the next clock rise, the
appropriate data is latched and written into the device. Byte
writes are allowed. All IOs are tri-stated during a byte write.Since
this is a common IO device, the asynchronous OE
must be deasserted and the IOs must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless of
the state of OE

) is 6.5 ns (133-MHz device).

CDV

) or the Controller

). Address advancement through the

input. A two-bit on-chip

) overrides all byte write inputs and writes data to all

, CE2, CE3) and an

1

) provide for easy bank

is ignored if CE1 is

, CE2, and CE3 are all asserted

or ADSC is asserted LOW (if the access is

, the write inputs must be deasserted during

CDV

is asserted LOW. The addresses presented are

)are ignored during this first clock cycle. If the write

X

.

1

input is

after clock rise. ADSP is ignored if

, CE2, CE3 are all asserted active,

1

, BWE,

input signal

Single Write Accesse s Initiated by ADSC

This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, (2) ADSC
HIGH, and (4) the write input signals (GW
indicate a write access. ADSC

The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQ
specified address location. Byte writes are allowed. All IOs are
tri-stated when a write is detected, even a byte write. Since this
is a common IO device, the asynchronous OE
be deasserted and the IOs must be tri-stated prior to the presen­tation of data to DQs. As a safety precaution, the data lines are
tri-stated once a write cycle is detected, regardless of the state
of OE

.

is asserted LOW, (3) ADSP is deasserted

, CE2, and CE3 are all asserted

1

, BWE, and BWX)

is ignored if ADSP is active LOW.

is written into the

S

input signal must

Burst Sequences

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
provides an on-chip two-bit wraparound burst counter inside the
SRAM. The burst counter is fed by A
linear or interleaved burst order. The burst order is determined
by the state of the MODE in put. A LOW on MODE selects a linear
burst sequence. A HIGH on MODE selects an interleaved burst
order. Leaving MODE unconnected causes the device to default
to a interleaved burst sequence.

, and can follow either a

[1:0]

Interleaved Burst Address Table
(MODE = Floating or VDD)

First

Address

A1: A0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

Linear Burst Address Table
(MODE = GND)

First

Address

A1: A0

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
CE

, ADSP, and ADSC must remain inactive for the duration of

3

after the ZZ input returns LOW.

t

ZZREC

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

, CE2,

1

Document #: 38-05357 Rev. *G Page 9 of 31

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Sleep mode standby current ZZ > VDD – 0.2V 100 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ active to sleep current This parameter is sampled

2t

CYC

CYC

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

Truth Table

tThe truth table for CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 follows.

[2, 3, 4, 5, 6]

ns
ns
ns

Cycle Description

ADDRESS

Used

CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselected Cycle, Power down None H X X L X L X X X L-H Tri-State
Deselected Cycle, Power down None L L X L L X X X X L-H Tri-State
Deselected Cycle, Power down None L X H L L X X X X L-H Tri-State
Deselected Cycle, Power down None L L X L H L X X X L-H Tri-State
Deselected Cycle, Power down None X X X L H L X X X L-H Tri-State
Sleep Mode, Power down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L H L L L X X X L L-H Q

Read Cycle, Begin Burst External L H L L L X X X H L-H

Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L-H D
Read Cycle, Begin Burst External L H L L H L X H L L-H Q
Read Cycle, Begin Burst External L H L L H L X H H L-H

Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H

Tri-State
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q

Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
Write Cycle, Suspend Burst Current X X X L H H H L X L-H D
Write Cycle, Suspend Burst Current H X X L X H H L X L-H D

Notes

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3. WRITE

4. The DQ pins are controlled by the current cycle and the OE

5. The SRAM always initiates a read cycle when ADSP

6. OE

= L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.

the ADSP
for the remainder of the write cycle.

or when the device is deselected, and all data bits behave as output when OE

or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive

Document #: 38-05357 Rev. *G Page 10 of 31

signal. OE is asynchronous and is not sampled with the clock.

is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after

is active (LOW).

[+] Feedback

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Partial T ruth Table for Read/Write

Notes

7. Table only lists a partial listing of the byte write combinations. Any Combination of BW

X

is valid Appropriate write is done based on which byte write is active.

8. BW

x represents any byte write signal BW

[A..H]

.To enable any byte write BWx, a Logic LOW signal should be applied at clock rise.Any number of bye writes can be

enabled at the same time for any given write.

Function (CY7C1441AV33)

Read HHXXXX
Read HLHHHH
Write Byte A (DQ
Write Byte B(DQ
Write Bytes A, B (DQ
Write Byte C (DQ
Write Bytes C, A (DQ
Write Bytes C, B (DQ
Write Bytes C, B, A (DQ

DQP

, DQPA)

B

Write Byte D (DQ
Write Bytes D, A (DQ
Write Bytes D, B (DQ
Write Bytes D, B, A (DQ

DQP

, DQPA)

B

Write Bytes D, B (DQ
Write Bytes D, B, A (DQ

, DQPA)

DQP

C

Write Bytes D, C, A (DQ
DQP

, DQPA)

B

, DQPA) HLHHHL

A

, DQPB)HLHHLH

B

, DQB, DQPA, DQPB)H L H H L L

A

, DQPC)HLHLHH

C

, DQ

C

A,

, DQ

C

B,

, DQB, DQ

C

, DQPD) HL LHHH

D

, DQ

D

A,

, DQ

D

A,

, DQB, DQ

D

, DQ

D

B,

, DQC, DQ

D

, DQB, DQA, DQPD,

D

Write All Bytes H L L L L L
Write All Bytes L XXXXX

[2, 7]

GW BWE BW

D

BW

C

BW

B

BW

A

DQPC, DQPA)H L H L H L
DQPC, DQPB)H L H L L H

DQPC,

A,

HLHLLL

DQPD, DQPA)H L L H H L
DQPD, DQPA)H L L H L H

DQPD,

A,

HLLHLL

DQPD, DQPB)H L L L H H

DQPD,

A,

HLLLHL

HLLLLH

Truth Table for Read/Write

Function (CY7C1443AV33)

Read H H X X
Read H L H H
Write Byte A - (DQ
Write Byte B - (DQ

and DQPA)HLHL

A

and DQPB)HLLH

B

Write All Bytes H L L L
Write All Bytes L X X X

[2]

Truth Table for Read/Write

Function (CY7C1447AV33)

Read H H X
Read H L All BW
Write Byte x – (DQ

x

Write All Bytes H L All BW
Write All Bytes L X X

Document #: 38-05357 Rev. *G Page 11 of 31

[2, 8]

and DQPx)HLL

GW BWE BW

B

GW BWE BW

BW

A

X

= H

= L

[+] Feedback

CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

IEEE 1149.1 Serial Boundary Scan (JTAG)

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

1

1

1

0

1 1

0 0

1 1

1

0

0

0

0 0

0

0

0 0

1

0

1

1

0

1

0

1

1

1

1 0

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

1

1

1

0

1 1

0 0

1 1

1

0

0

0

0 0

0

0

0 0

1

0

1

1

0

1

0

1

1

1

1 0

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 incor­porates a serial boundary scan test access port (TAP). This part
is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3V or 2.5V IO logic levels.

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter­nally pulled up and may be unconnected. They may alternately
be connected to V
left unconnected. Upon power up, the device comes up in a reset
state which does not interfere with the operation of the device.

DD through a pull up resistor. TDO should be

TAP Controller State Diagram

this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register . TDI is internally pulled
up and can be unconnected if the TAP is unused in an appli­cation. TDI is connected to the most significant bit (MSB) of any
register. (See Tap Controller Block Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP st ate machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See Tap Controller State Diagram.)

TAP Controller State Diagram

The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave

Document #: 38-05357 Rev. *G Page 12 of 31

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.

At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and
scan data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register.
Data is serially loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of TCK.

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the Tap Controller Block Diagram.
Upon power up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.

When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (V
BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the IO ring.

The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.

) when the

SS

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in this section in detail.

Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller must be
moved into the Update-IR state.

IDCODE

The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction registe r
upon power up or whenever the TAP controller is given a test
logic reset state.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is given during the
“Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.

The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.

To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (t
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK

After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.

PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells prior to the selection
of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.

and tCH). The SRAM clock input might not be captured

CS

captured in the boundary scan register.

Document #: 38-05357 Rev. *G Page 13 of 31

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

EXTEST

t

TL

Test Clock

(TCK)

123456

T

est Mode Select

(TMS)

t

TH

Test Data-Out

(TDO)

t

CYC

Test Data-In

(TDI)

t

TMSH

t

TMSS

t

TDIH

t

TDIS

t

TDOX

t

TDOV

DON’T CARE UNDEFINED

The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the shift-DR controller state.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #89
(for 165-FBGA package) or bit #138 (for 209-FBGA package).
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current

TAP Timing

instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is pre-set HIGH
to enable the output when the device is po wered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

Document #: 38-05357 Rev. *G Page 14 of 31

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

TAP AC Switching Characteristics

Notes

9. t

CS

and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

10.Test conditions are specified using the load in TAP AC test Conditions. t

R/tF

= 1 ns.

Over the Operating Range

Parameter Description Min. Max. Unit

Clock

t

TCYC

t

TF

t

TH

t

TL

TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH time 20 ns
TCK Clock LOW time 20 ns

Output Times

t

TDOV

t

TDOX

TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns

Setup Times

t

TMSS

t

TDIS

t

CS

TMS Setup to TCK Clock Rise 5 ns
TDI Setup to TCK Clock Rise 5 ns
Capture Setup to TCK Rise 5 ns

Hold Times

t

TMSH

t

TDIH

t

CH

TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns

[9, 10]

Document #: 38-05357 Rev. *G Page 15 of 31

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

3.3V TAP AC Test Conditions

T

DO

1.5V

20p

F

Z=50Ω

O

50Ω

T

DO

1.25V

20p

F

Z=50Ω

O

50Ω

2.5V TAP AC Test Conditions

Input pulse levels.................................................VSS to 3.3V

Input rise and fall times....................................................1 ns

Input timing reference levels...........................................1.5V

Output reference levels ..................................................1.5V

Test load termination supply voltage ..............................1.5V

3.3V TAP AC Output Load Equivalent

Input pulse levels.................................................VSS to 2.5V

Input rise and fall time .....................................................1 ns

Input timing reference levels.........................................1.25V

Output reference levels ................................................1.25V

Test load termination supply voltage ............................1.25V

2.5V TAP AC Output Load Equivalent

TAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)

Parameter Description Description Conditions Min. Max. Unit

V

OH1

Output HIGH Voltage IOH = –4.0 mA V

IOH = –1.0 mA V

V

V

V

V

V

I

OH2

OL1

OL2

IH

IL

X

Output HIGH Voltage IOH = –100 µA V

Output LOW Voltage IOL = 8.0 mA V

I

= 1.0 mA V

OL

Output LOW Voltage IOL = 100 µA V

Input HIGH Voltage V

Input LOW Voltage V

Input Load Current GND < VIN < V

DDQ

[11]

= 3.3V 2.4 V

DDQ

= 2.5V 2.0 V

DDQ

= 3.3V 2.9 V

DDQ

V

= 2.5V 2.1 V

DDQ

= 3.3V 0.4 V

DDQ

= 2.5V 0.4 V

DDQ

= 3.3V 0.2 V

DDQ

V

= 2.5V 0.2 V

DDQ

= 3.3V 2.0 VDD + 0.3 V

DDQ

V

= 2.5V 1.7 VDD + 0.3 V

DDQ

= 3.3V –0.3 0.8 V

DDQ

V

= 2.5V –0.3 0.7 V

DDQ

–5 5 µA

Note

11.All voltages referenced to V

Document #: 38-05357 Rev. *G Page 16 of 31

SS

(GND).

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CY7C1443AV33,CY7C1447AV33

Identification Register Definitions

Instruction Field

Revision Number (31:29) 000 000 000 Describes the version number.
Device Depth (28:24) 01011 01011 01011 Reserved for Internal Use
Architecture/Memory

Type(23:18)
Bus Width/Density(17:12) 100111 010111 110111 Defines width and density
Cypress JEDEC ID Code (11:1) 00000110100 00000110100 00000110100 Allows unique identification of SRAM

ID Register Presence Indicator (0) 1 1 1 Indicates the presence of an ID

[12]

CY7C1441AV33

(1M x 36)

000001 000001 000001 Defines memory type and architecture

CY7C1443AV33

(2M x 18)

CY7C1447AV33

(512K x 72)

Description

vendor.

register.

Scan Register Sizes

Register Name Bit Size (x36) Bit Size (x18) Bit Size (x18)

Instruction 3 3 3
Bypass 1 1 1

ID 32 32 32
Boundary Scan Order (165-ball FBGA package) 89 89 ­Boundary Scan Order (209-ball FBGA package) - - 138

Identification Codes

Instruction Code Description

EXTEST 000 Captures IO ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and

SAMPLE Z 010 Captures IO ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures IO ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register be tween TDI and TDO. This operation does not affect SRAM

TDO. This operation does not affect SRAM operations.

Forces all SRAM output drivers to a High-Z state.

Does not affect SRAM operation.

operations.

Note

12.Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.

Document #: 38-05357 Rev. *G Page 17 of 31

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CY7C1443AV33,CY7C1447AV33

165-ball FBGA Boundary Scan Order

CY7C1441AV33 (1M x 36), CY7C1443AV33 (2M x 18)

Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID

1
2
3N10 28G10 53B2 78P1
4P11 29F10 54C2 79R1
5 P8 30 E10 55 B1 80 R2
6 R8 31 D10 56 A1 81 P3
7R9 32C11 57C1 82R3
8P9 33A11 58D1 83P2

9P10 34B11 59E1 84R4
10 R10 35 A10 60 F1 85 P4
11 R11 36 B10 61 G1 86 N5
12 H11 37 A9 62 D2 87 P6
13 N11 38 B9 63 E2 88 R6
14 M11 39 C10 64 F2 89 Internal
15 L11 40 A8 65 G2
16 K11 41 B8 66 H1
17 J11 42 A7 67 H3
18 M10 43 B7 68 J1
19 L10 44 B6 69 K1
20 K10 45 A6 70 L1
21 J10 46
22 H9 47
23 H10 48 A4 73 K2
24 G11 49 B4 74 L2
25 F11 50 B3 75 M2

N6
N7

[13,14]

26 E11 51 A3 76 N1
27 D11 52 A2 77 N2

B5
A5

71 M1
72 J2

Notes

13.Balls which are NC (No Connect) are preset LOW.

14.Bit# 89 is preset HIGH.

Document #: 38-05357 Rev. *G Page 18 of 31

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CY7C1443AV33,CY7C1447AV33

Maximum Ratings

Notes

15.Overshoot: V

IH

(AC) < VDD +1.5V (Pulse width less than t

CYC

/2), undershoot: VIL(AC) > –2V (Pulse width less than t

CYC

/2).

16.T

Power-up

: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and V

DDQ

< V

DD.

Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested .

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied ............................................ –55°C to +125°C

Supply Voltage on V
Supply Voltage on V

Relative to GND........–0.3V to +4.6V

DD

Relative to GND...... –0.3V to +V

DDQ

DD

DC Voltage Applied to Outputs

in Tri-State .................. ... ... ...................–0.5V to V

DDQ

+ 0.5V

Electrical Characteristics Over the Operating Range

DC Input Voltage...................................–0.5V to V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current..................................................... >200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V –5%
Industrial –40°C to +85°C

[15, 16]

Ambient

T emperature

V

DD

+ 0.5V

DD

to V

V

DDQ

DC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Max. Unit

V
V

V

V

V

V

I

I
I

I

I

I

I

DD
DDQ

OH

OL

IH

IL

X

OZ
DD

SB1

SB2

SB3

SB4

Power Supply Voltage 3.135 3.6 V
IO Supply Voltage for 3.3V IO 3.135 V

DD

for 2.5V IO 2.375 2.625 V

Output HIGH Voltage for 3.3V IO, I

for 2.5V IO, I

Output LOW Voltage for 3.3V IO, I

for 2.5V IO, I

Input HIGH Voltage

[15]

for 3.3V IO 2.0 VDD + 0.3V V
for 2.5V IO 1.7 V

Input LOW Voltage

[15]

for 3.3V IO –0.3 0.8 V

= –4.0 mA 2.4 V

OH

= –1.0 mA 2.0 V

OH

= 8.0 mA 0.4 V

OL

= 1.0 mA 0.4 V

OL

+ 0.3V V

DD

for 2.5V IO –0.3 0.7 V

Input Leakage Current
except ZZ and MODE

Input Current of MODE Input = V

Input Current of ZZ Input = V

Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply

Current
Automatic CE

Power down
Current—TTL Inputs

Automatic CE
Power down
Current—CMOS Inputs

Automatic CE
Power down
Current—CMOS Inputs

Automatic CE
Power down
Current—TTL Inputs

GND ≤ VI ≤ V

Input = V

Input = V

V

= Max., I

DD

f = f

MAX

SS
DD
SS
DD

= 1/t

DDQ

Output Disabled –5 5 μA

DDQ,

= 0 mA,

OUT

CYC

Max. VDD, Device Deselected,

≥ VIH or VIN ≤ VIL, f = f

V

IN

inputs switching

MAX,

Max. VDD, Device Deselected,

≥ VDD – 0.3V or VIN ≤ 0.3V,

V

IN

f = 0, inputs static
Max. VDD, Device Deselected,

V

IN

f = f

≥ V

– 0.3V or VIN ≤ 0.3V,

DDQ

, inputs switching

MAX

Max. VDD, Device Deselected,

≥ V

V
f = 0, inputs static

– 0.3V or VIN ≤ 0.3V,

IN

DD

–5 5 μA

–30 μA

5 μA

–5 μA

30 μA

7.5-ns cycle, 133 MHz 310 mA
10-ns cycle, 100 MHz 290 mA

All Speeds 180 mA

All speeds 120 mA

All Speeds 180 mA

All Speeds 135 mA

DD

V

Document #: 38-05357 Rev. *G Page 19 of 31

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CY7C1443AV33,CY7C1447AV33

Capacitance

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

R

L

= 50Ω

Z

0

= 50Ω

VT= 1.5V

3.3V

ALL INPUT PULSES

V

DDQ

GND

90%

10%

90%

10%

≤ 1 ns

≤ 1 ns

(c)

OUTPUT

R = 1667Ω

R = 1538Ω

5pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

R

L

= 50Ω

Z

0

= 50Ω

V

T

= 1.25V

2.5V

ALL INPUT PULSES

V

DDQ

GND

90%

10%

90%

10%

≤ 1 ns

≤ 1 ns

(c)

3.3V IO Test Load

2.5V IO Test Load

Note

17.Tested initially and after any design or process change that may affect these parameters

Parameter

CIN Input Capacitance TA = 25°C, f = 1 MHz,
C

CLK

C

IO

[17]

Description Test Conditions

V

= 3.3V

Clock Input Capacitance 3 7 5 pF
Input/Output Capacitance 5.5 6 7 pF

V

DD

DDQ

= 2.5V

Thermal Resistance

100 TQFP

Max.

165 FBGA

Max.

209 FBGA

Max.

6.5 7 5 pF

Unit

Parameter

Θ

JA

Θ

JC

[17]

Description Test Conditions

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

100 TQFP

Package

Test conditions follow standard

25.21 20.8 25.31 °C/W
test methods and procedures for
measuring thermal impedance,
per EIA/JESD51.

2.28 3.2 4.48 °C/W

Figure 2. AC Test Loads and Waveforms

165 FBGA

Package

209 FBGA

Package

Unit

Document #: 38-05357 Rev. *G Page 20 of 31

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CY7C1443AV33,CY7C1447AV33

Switching Characteristics

Notes

18.This part has a voltage regulator internally; t

POWER

is the time that the power must be supplied above VDD(minimum) initially, before a read or write operation can be

initiated.

19.t

CHZ

, t

CLZ,tOELZ

, and t

OEHZ

are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 20. Transition is measured ± 200 mV

from steady-state voltage.

20.At any given voltage and temperature, t

OEHZ

is less than t

OELZ

and t

CHZ

is less than t

CLZ

to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but refl ect parameters guaranteed over worst case user conditions. Device is designed to achieve
High-Z prior to Low-Z under the same system conditions.

21.This parameter is sampled and not 100% tested.

22.Timing reference level is 1.5V when V

DDQ

= 3.3V and is 1.25V when V

DDQ

= 2.5V.

23.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Over the Operating Range

Parameter

t

POWER

Clock

t

CYC

t

CH

t

CL

Output Times

t

CDV

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Setup Times

t

AS

t

ADS

t

ADVS

t

WES

t

DS

t

CES

Hold Times

t

AH

t

ADH

t

WEH

t

ADVH

t

DH

t

CEH

[22, 23]

V

(Typical) to the first Access

DD

Clock Cycle Time 7.5 10 ns
Clock HIGH 2.5 3.0 ns
Clock LOW 2.5 3.0 ns

Data Output Valid After CLK Rise 6.5 8.5 ns
Data Output Hold After CLK Rise 2.5 2.5 ns
Clock to Low-Z
Clock to High-Z
OE LOW to Output Valid 3.0 3.8 ns
OE LOW to Output Low-Z
OE HIGH to Output High-Z

Address Setup Before CLK Rise 1.5 1.5 ns
ADSP, ADSC Setup Before CLK Rise 1.5 1.5 ns
ADV Setup Before CLK Rise 1.5 1.5 ns
GW, BWE, BWX Setup Before CLK Rise 1.5 1.5 ns
Data Input Setup Before CLK Rise 1.5 1.5 ns
Chip Enable Setup 1.5 1.5 ns

Address Hold After CLK Rise 0.5 0.5 ns
ADSP, ADSC Hold After CLK Rise 0.5 0.5 ns
GW, BWE, BWX Hold After CLK Rise 0.5 0.5 ns
ADV Hold After CLK Rise 0.5 0.5 ns
Data Input Hold After CLK Rise 0.5 0.5 ns
Chip Enable Hold After CLK Rise 0.5 0.5 ns

Description

[19, 20, 21]

[19, 20, 21]

[18]

[19, 20, 21]

[19, 20, 21]

–133 –100

Min. Max. Min. Max.

Unit

11ms

2.5 2.5 ns

3.8 0 4.5 ns

00ns

3.0 4.0 ns

Document #: 38-05357 Rev. *G Page 21 of 31

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CY7C1443AV33,CY7C1447AV33

Timing Diagrams

t

CYC

t

CL

CLK

t

ADH

t

ADS

ADDRESS

t

CH

t

AH

t

AS

A1

t

CEH

t

CES

Data Out (Q)

High-Z

t

CLZ

t

DOH

t

CDV

t

OEHZ

t

CDV

Single READ

BURST

READ

t

OEV

t

OELZ

t

CHZ

Burst wraps around
to its initial state

t

ADVH

t

ADVS

t

WEH

t

WES

t

ADH

t

ADS

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1)

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

A2

ADV suspends burst

Deselect Cycle

DON’T CARE

UNDEFINED

ADSP

ADSC

G

W, BWE,BW

X

CE

ADV

OE

Note

24.On this diagram, when CE

is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Figure 3. Read Cycle Timing

[24]

.

Document #: 38-05357 Rev. *G Page 22 of 31

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Timing Diagrams (continued)

t

CYC

t

CL

CLK

t

ADH

t

ADS

ADDRESS

t

CH

t

AH

t

AS

A1

t

CEH

t

CES

High-Z

BURST READ BURST WRITE

D(A2)

D(A2 + 1)

D(A2 + 1)

D(A1)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

A2 A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

t

ADH

t

ADS

t

ADH

t

ADS

t

OEHZ

t

ADVH

t

ADVS

t

WEH

t

WES

t

DH

t

DS

t

WEH

t

WES

Byte write signals are ignored for rst cycle when
ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

ADSP

ADSC

BWE,

BW

X

GW

CE

ADV

OE

Data in (D)

D

ata Out (Q)

Note

25.

Full width write can be initiated by either GW

LOW; or by GW HIGH, BWE LOW and BWX LOW

Figure 4. Write Cycle Timing

[24, 25]

.

Document #: 38-05357 Rev. *G Page 23 of 31

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Timing Diagrams (continued)

t

CYC

t

CL

CLK

t

ADH

t

ADS

ADDRESS

t

CH

t

AH

t

AS

A2

t

CEH

t

CES

Single WRITE

D(A3)

A3 A4

BURST READ

Back-to-Back READs

High-Z

Q(A2)

Q(A4) Q(A4+1)

Q(A4+2)

Q(A4+3)

t

WEH

t

WES

t

OEHZ

t

DH

t

DS

t

CDV

t

OELZ

A1 A5 A6

D(A5) D(A6)

Q(A1)

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

ADSP

ADSC

BWE, BW X

CE

ADV

OE

Data In (D)

D

ata Out (Q)

Note

26.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP

or ADSC.

27.

GW

is HIGH

Figure 5. Read/Write Cycle Timing

[24, 26, 27]

.

Document #: 38-05357 Rev. *G Page 24 of 31

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Timing Diagrams (continued)

A

Note

28.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

29.DQs are in high-Z when exiting ZZ sleep mode.

CLK

Figure 6. ZZ Mode Timing

t

ZZ

[28, 29]

t

ZZREC

I

SUPPLY

LL INPUTS

(except ZZ)

Outputs (Q)

ZZ

t

ZZI

I

DDZZ

High-Z

t

RZZI

DESELECT or READ Only

DON’T CARE

Document #: 38-05357 Rev. *G Page 25 of 31

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Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.

Speed

(MHz)

133 CY7C1441AV33-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free Commercial

100 CY7C1441AV33-100AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free Commercial

Ordering Code

CY7C1443AV33-133AXC
CY7C1441AV33-133BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1443AV33-133BZC
CY7C1441AV33-133BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1443AV33-133BZXC
CY7C1447AV33-133BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm)
CY7C1447AV33-133BGXC 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-free
CY7C1441AV33-133AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free lndustrial
CY7C1443AV33-133AXI
CY7C1441AV33-133BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1443AV33-133BZI
CY7C1441AV33-133BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1443AV33-133BZXI
CY7C1447AV33-133BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm)
CY7C1447AV33-133BGXI 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-free

CY7C1443AV33-100AXC
CY7C1441AV33-100BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1443AV33-100BZC
CY7C1441AV33-100BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1443AV33-100BZXC
CY7C1447AV33-100BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm)
CY7C1447AV33-100BGXC 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-free
CY7C1441AV33-100AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free lndustrial
CY7C1443AV33-100AXI
CY7C1441AV33-100BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1443AV33-100BZI
CY7C1441AV33-100BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free
CY7C1443AV33-100BZXI
CY7C1447AV33-100BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm)
CY7C1447AV33-100BGXI 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-free

Package
Diagram

Part and Package Type

Operating

Range

Document #: 38-05357 Rev. *G Page 26 of 31

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Package Diagrams

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

3. DIMENSIONS IN MILLIMETERS

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

0.30±0.08

0.65

20.00±0.10

22.00±0.20

1.40±0.05

12°±1°

1.60 MAX.

0.05 MIN.

0.60±0.15

0° MIN.

0.25

0°-7°

(8X)

STAND-OFF

R 0.08 MIN.

TYP.

0.20 MAX.

0.15 MAX.

0.20 MAX.

R 0.08 MIN.

0.20 MAX.

14.00±0.10

16.00±0.20

0.10

SEE DETAIL

A

DETAIL

A

1

100

30

31 50

51

80

81

GAUGE PLANE

1.00 REF.

0.20 MIN.

SEATING PLANE

51-85050-*B

Figure 1. 100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)

Document #: 38-05357 Rev. *G Page 27 of 31

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Package Diagrams (continued)

A

1

PIN 1 CORNER

17.00±0.10

15.00±0.10

7.00

1.00

Ø0.45±0.05(165X)

Ø0.25 M C A B

Ø0.05MC

B

A

0.15(4X)

0.35

1.40 MAX.

SEATING PLANE

0.53±0.05

0.25 C

0.15 C

PIN1CORNER

TOP VIEW

BOTTOM VIEW

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14.00

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J

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1110986754321

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51-85165-*A

Figure 2. 165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)

Document #: 38-05357 Rev. *G Page 28 of 31

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Package Diagrams (continued)

51-85167-**

Figure 3. 209-ball FBGA (14 x 22 x1.76 mm) (51-85167)

Document #: 38-05357 Rev. *G Page 29 of 31

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Document History Page

Document Title: CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
Document Number: 38-05357

REV. ECN NO. Issue Date

** 124459 03/06/03 CJM New Data Sheet

*A 254910 See ECN SYT Part number changed from previous revision. New and old part number differ by

*B 300131 See ECN SYT Removed 150 and 117 MHz Speed Bins

*C 320813 See ECN SYT Changed H9 pin from V

*D 331551 See ECN SYT Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA

Orig. of
Change Description of Change

the letter “A”
Modified Functional Block diagrams
Modified switching waveforms
Added Footnote #13 (32-Bit Vendor I.D Code changed)
Added Boundary scan information
Added I
Added t
Removed 119 PBGA Package

, IX and ISB values in the DC Electrical Characteristics

DD

specifications in Switching Characteristics table

POWER

Changed 165 FBGA Package from BB165C (15 x 17 x 1.20 mm) to BB165
(15 x 17 x 1.40 mm)
Changed 209-Lead PBGA BG209 (14 x 22 x 2.20 mm) to BB209A
(14 x 22 x 1.76 mm)

Changed
Package on Pg # 21

Θ

JA

and Θ

from TBD to 25.21 and 2.58 °C/W respectively for TQFP

JC

Added lead-free information for 100-pin TQFP, 165 FBGA and 209 BGA
Packages.
Added comment of ‘Lead-free BG and BZ packages availability’ below the
Ordering Information

to VSS on the Pin Configuration table for 209 FBGA

Changed the test condition from V

SSQ

Characteristics table.
Replaced the TBD’s for I
Replaced TBD’s for Θ
fBGA packages on the Thermal Resistance table.
Changed C
Package.

IN,CCLK

and CIO to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP

, I

DD

and ΘJC to their respective values for 165 fBGA and 209

JA

= Min. to VDD = Max for VOL in the Electrical

DD

, I

, I

SB1

SB2

SB3

and I

SB4

Removed “Lead-free BG and BZ packages availability” comment below the
Ordering Information

Packages as per JEDEC standards and updated the Pin Definitions accordingly
Modified V
Replaced TBD to 100 mA for I

OL, VOH

Changed CIN, C
Package.

test conditions

and CIO to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA

CLK

DDZZ

Added Industrial Temperature Grade
Changed I
Updated the Ordering Information by shading and unshading MPNs as per avail-

SB2

and I

from 100 and 110 mA to 120 and 135 mA respectively

SB4

ability

to their respective values.

Document #: 38-05357 Rev. *G Page 30 of 31

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CY7C1441AV33

CY7C1443AV33,CY7C1447AV33

Document Title: CY7C1441A V33/CY7C1443AV33/CY7C1447AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Flow-Through SRAM
Document Number: 38-05357

Orig. of

REV. ECN NO. Issue Date

Change Description of Change

*E 417547 See ECN RXU Converted from Preliminary to Final.

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”.
Changed I
and also Changed I
tively on page# 19.
Modified test condition in note# 8 from VIH < V
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

current value in MODE from –5 & 30 μA to –30 & 5 μA respectively

X

current value in ZZ from –30 & 5 μA to –5 & 30 μA respec-

X

DD to VIH

< V

DD.

Electrical Characteristics Table.
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information.

*F 473650 See ECN VKN Added the Maximum Rating for Supply Voltage on V

, t

Changed t
Switching Characteristics table.

from 25 ns to 20 ns and t

TH

TL

from 5 ns to 10 ns in TAP AC

TDOV

Relative to GND.

DDQ

Updated the Ordering Information table.

*G 2447027 See ECN VKN/AESA Corrected typo in the Ordering Information table

Corrected typo in the CY7C1447AV33 ‘s Logic Block diagram
Updated the x72 block diagram

© Cypress Semiconductor Corporation, 2003- 2008. The infor mation cont ain ed herein is subj ect to change wi thout notice. C ypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used fo r
medical, life support, life saving, critica l contr o l or safety applications, unless pursuant to an express written agreemen t w it h C ypr ess. Fu rth erm ore, Cyp ress doe s not auth ori ze i t s pr o ducts for use as
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application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (Unit ed States and foreign),
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integrated circuit as specified in the ap plicable agreem ent. Any reprod uction, modificatio n, translation, co mpilation, or repr esentation of this Source Co de except as speci fied above is pro hibited with out
the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials des cribed herei n. Cypress doe s not
assume any liability arising out of the applic ation or use o f any pr oduct or circ uit de scribed herein . Cypr ess does n ot author ize its p roducts fo r use as critical compon ents in life-su pport systems whe re
a malfunction or failure may reason ably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 38-05357 Rev. *G Revised May 09, 2008 Page 31 of 31

i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.

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