Cypress Semiconductor CY7C1440AV33, CY7C1442AV33, CY7C1446AV33 Specification Sheet

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

36-Mbit (1M x 36/2M x 18/512K x 72)

Pipelined Sync SRAM

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200 and 167 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

• 2.5V/3.3V I/O power supply

• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel
Pentium

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• CY7C1440AV33, CY7C1442AV33 available in lead-free
100-pin TQFP package, lead-free and non-lead-free
165-ball FBGA package. CY7C1446AV33 available in
lead-free and non-lead-free 209-ball FBGA package

• Also available in lead-free packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

®

interleaved or linear burst sequences

®

Functional Description

The CY7C1440AV33/CY7C1442AV33/CY7C1446A V33 SRAM
integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

), depth-expansion Chip Enables (CE2 and CE3), Burst

1

Control inputs (ADSC
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC
burst addresses can be internally generated as controlled by
the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active

causes all bytes to be written.

LOW
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33

operates from a +3.3V core power supply while all outputs may
operate with either a +2.5 or +3.3V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.

, ADSP, and ADV), Write Enables (BW

[1]

) and the ZZ pin.

) or

) are active. Subsequent

X

Selection Guide

250 MHz 200 MHz 167 MHz Unit

Maximum Access Time 2.6 3.2 3.4 ns
Maximum Operating Current 475 425 375 mA
Maximum CMOS Standby Current 120 120 120 mA

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05383 Rev. *E Revised June 23, 2006

[+] Feedback

Logic Block Diagram – CY7C1440AV33 (1M x 36)

A

A

A
B

0, A1, A

MODE

ADV

CLK

ADSC
ADSP

BW

D

BW

BW

BW

BWE

GW

CE
CE
CE

OE

C

B

A

1
2
3

ADDRESS
REGISTER

D ,

DQPD

DQ

BYTE

WRITE REGISTER

C ,

DQPC

DQ

BYTE

WRITE REGISTER

B ,

DQPB

DQ

BYTE

WRITE REGISTER

DQ

A ,

DQPA

BYTE

WRITE REGISTER

ENABLE

REGISTER

2

BURST

COUNTER

AND

CLR

LOGIC

PIPELINED

ENABLE

A

[1:0]

Q1

Q0

D

DQ

BYTE

WRITE DRIVER

C ,

DQ

BYTE

WRITE DRIVER

B ,

DQ

BYTE

WRITE DRIVER

DQ

BYTE

WRITE DRIVER

,DQP

DQPC

DQPB

A ,

DQPA

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

D

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQs
DQP
DQP
DQP
DQP

A
B
C
D

ZZ

SLEEP

CONTROL

Logic Block Diagram – CY7C1442AV33 (2M x 18)

0, A1, A

MODE

ADV

CLK

ADSC

ADSP

BW

BW

B

A

BWE

GW

CE

1

CE2
CE3

OE

ADDRESS
REGISTER

COUNTER AND

CLR

DQB,DQP

B

WRITE REGISTER

DQA,DQP

A

WRITE REGISTER

ENABLE

REGISTER

2

BURST
LOGIC

PIPELINED

ENABLE

A[1:0]

Q1

Q0

DQB,DQP

B

WRITE DRIVER

DQA,DQP

A

WRITE DRIVER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

DQs
DQP
DQP

INPUT

REGISTERS

ZZ

SLEEP

CONTROL

Document #: 38-05383 Rev. *E Page 2 of 31

[+] Feedback

A

A
B
C
D
E
F
G
H

Logic Block Diagram – CY7C1446AV33 (512K x 72)

DQH, DQP

WRITE DRIVER

DQF, DQP

WRITE DRIVER

DQF, DQP

WRITE DRIVER

DQE, DQP

WRITE DRIVER

DQD, DQP

WRITE DRIVER

DQC, DQP

WRITE DRIVER

DQB, DQP

WRITE DRIVER

DQA, DQP

WRITE DRIVER

ENABLE

REGISTER

ADDRESS
REGISTER

H

F

F

E

D

C

B

A

BINARY

COUNTER

CLR

PIPELINED

ENABLE

A[1:0]

Q1

Q0

DQH, DQP

WRITE DRIVER

DQG, DQP

WRITE DRIVER

DQF, DQP

WRITE DRIVER

DQE, DQP

BYTE

“a”

WRITE DRIVER

WRITE DRIVER

DQD, DQP

WRITE DRIVER

DQC, DQP

WRITE DRIVER

DQB, DQP

WRITE DRIVER

DQA, DQP

WRITE DRIVER

0, A1,A

MODE

ADV

CLK

ADSC
ADSP

BW

BW

BW

BW

BW

BW

BW

BW

BWE

GW
CE1
CE2
CE3

H

G

F

E

D

C

B

A

OE

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

H

G

F

E

MEMORY

ARRAY

D

C

SENSE

B

A

AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQs
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP

ZZ

SLEEP

CONTROL

Document #: 38-05383 Rev. *E Page 3 of 31

[+] Feedback

Pin Configurations

1CE2

A

A

BWD

CE

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

100-pin TQFP Pinout

BWA

CE3VDDV

SS

CLKGWBWEOEADSC

ADSP

ADV

A

A

BWC

BWB

1CE2

A

A

NCNCBWBBWA

CE

CE3VDDV

SS

CLKGWBWEOEADSC

ADSP

ADV

A

A

DQP
DQC
DQc

V

DDQ

V

SSQ

DQC
DQC
DQC
DQC

V

SSQ

V

DDQ

DQC
DQC

NC

V

NC

V
DQD
DQD

V

DDQ

V

SSQ

DQD
DQD
DQD
DQD

V

SSQ

V

DDQ

DQD
DQD

DQPD

100999897969594939291908988878685848382

C

1
2
3
4
5
6
7
8
9
10
11
12
13
14

DD

15
16

SS

17
18
19
20
21
22
23
24
25
26
27
28
29
30

CY7C1440AV33

(1M x 36)

31323334353637383940414243444546474849

MODE

AAA

1A0

A

A

A

NC/72M

A

A

DD

V

AAAAA

SS

V

81

DQPB

80

DQB

79

DQB

78

V

77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DDQ

V

SSQ

DQB
DQB
DQB
DQB
V

SSQ

V

DDQ

DQB
DQB
V

SS

NC
V

DD

ZZ
DQ
DQA
V

DDQ

V

SSQ

DQA
DQA
DQA
DQA
V

SSQ

V

DDQ

DQA
DQA
DQPA

A

NC
NC
NC

V

DDQ

V

SSQ

NC

NC
DQ
DQB

V

SSQ

V

DDQ

DQB
DQB

NC

V

NC

V
DQB
DQB

V

DDQ

V

SSQ

DQB
DQB

DQPB

NC

V

SSQ

V

DDQ

NC
NC
NC

B

DD

SS

50

A

A

100999897969594939291908988878685848382

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CY7C1442AV33

(2M x 18)

31323334353637383940414243444546474849

MODE

AAA

1A0

A

A

A

NC/72M

A

A

DD

V

AAAAA

SS

V

81

A

80

NC

79

NC

78

V

77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DDQ

V

SSQ

NC
DQP
DQA
DQA
V

SSQ

V

DDQ

DQA
DQA
V

SS

NC
V

DD

ZZ
DQ
DQA
V

DDQ

V

SSQ

DQA
DQA
NC
NC
V

SSQ

V

DDQ

NC
NC
NC

A

A

50

A

A

Document #: 38-05383 Rev. *E Page 4 of 31

[+] Feedback

Pin Configurations (continued)

2345671

NC/288M

A
B
C

D
E
F
G

H

J
K
L

M

N
P

R

NC/144M

DQP

C

DQ

C

DQ

C

DQ

C

DQ

C

NC

DQ

D

DQ

D

DQ

D

DQ

D

DQP

D

NC

MODE

A

A

NC

DQ
DQ
DQ

DQ

NC
DQ
DQ
DQ

DQ

NC

NC/72M

A

CE
CE2

V

DDQ

V

C
C
C
C

V
V
V

DDQ
DDQ
DDQ

DDQ

NC

V
V
V
V
V

DDQ
DDQ
DDQ
DDQ
DDQ

D
D
D
D

A
A

165-ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1440AV33 (1M x 36)

BW

1

BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

BW

BW

V
V

V
V
V

V
V

V
V
V

B

SS
SS

SS
SS
SS

SS
SS

SS
SS
SS

C
D

NC

TDI

TMS

CE

CLK

A

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A

A1

A0

BWE

3

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO
TCK

ADSC

V
V

V
V
V

V
V
V
V

V
V

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

891011

ADV

OE ADSP

V
V

V
V
V

V
V
V
V
V

DDQ
DDQ

DDQ
DDQ
DDQ

NC

DDQ
DDQ
DDQ
DDQ
DDQ

A

A

SS

DD
DD
DD
DD

DD
DD
DD
DD

DD
SS

A

A

A
A

NC/1G DQP

DQ

B

DQ

B

DQ

B

DQ

B

NC

DQ

A

DQ

A

DQ

A

DQ

A

NC

A

NC

NC/576M

B

DQ

B

DQ

B

DQ

B

DQ

B

ZZ

DQ

A

DQ

A

DQ

A

DQ

A

DQP

A

A
AA

A
B
C

D
E

F
G
H

J
K

L

M

N
P

R

CY7C1442AV33 (2M x 18)

2345671

NC/288M
NC/144M

NC
NC

NC V
NC
NC

NC

DQ

B

DQ

B

DQ

B

DQ

B

DQP

B

NC

MODE

A
A

NC

DQ

B

DQ

B

DQ

B

DQ

B

NC
NC
NC
NC

NC
NC

NC/72M

A

CE

CE2

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

BW

1

B

NC BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A
A

A

A

NC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

891011

CE
CLK

A

V

SS

V

SS
SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A

A1

BWE

3

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCKA0

ADSC

OE ADSP

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD
DD

V

DD

V

DD

V

DD

V

SS

A

A

ADV

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

A
A

NC/1G DQP

NC
NC
NC
NC

NC

DQ

A

DQ

A

DQ

A

DQ

A

NC

A

A

NC/576M

DQ

A

DQ

A

DQ

A

DQ

A

ZZ
NCV
NC
NC

NC
NC

A
AA

A

Document #: 38-05383 Rev. *E Page 5 of 31

[+] Feedback

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

Pin Configurations

123456789 1110

A

DQ
DQ

B

DQ

C
D

DQ

E

DQP

DQ

F
G

DQ

H
J
K
L
M
N
P
R
T
U
V
W

DQ

DQ

NC

DQ
DQ

DQ
DQ

DQP

DQ
DQ

DQ
DQ

(continued)

DQ

G

G
G

G

C

C

C

H
H

H

H

D

D
D

D

G

DQ

G

DQ

G

DQ

G

DQP

G

DQ

DQ

C

DQ

DQ

NC

DQ
DQ
DQ

DQ
DQP

D

DQ

DQ
DQ
DQ

209-ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1446AV33 (512K × 72)

A

BWS

BWS

V

SS

V

C

DDQ

V

C

SS

V

DDQ

C

V

SS

C

V

C

DDQ

CLK

V

DDQ

H

V

SS

H

V

DDQ

H

V

SS

H

V

DDQ

H

V

D

SS

NC/72M

D

AA

D

TMS

D

CE

BWS

C

BWS

H

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

NC MODE

A

TDI TDO TCK

ADSP

2

NC/288M

G

NC/144M

D

NC/1G

V

DD

V
V
V

V
V
V
V

V

V

V

NC

AA A

AA

A

SS

DD

SS

DD

SS

DD

SS

DD

SS

DD

ADSC

BW
CE

1

OE

V

DD

NC

NC
NC
NC

V

SS

NC
NC

NC

ZZ

V

DD

ADV
A

NC/576M

GW

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

NC

AA

A1

A

A0

CE

BWS

BWS

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

NC

A

3

BWS

B

E

BWS

V

SS

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

F

A

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

V

SS

AA

DQ

DQ

DQ
DQ
DQP

DQ
DQ

DQ

DQ

NC

DQ
DQ

DQ
DQ

DQP

DQ
DQ

DQ
DQ

DQ

B

B
B

B

F

F

F

F

F

DQ

DQ
DQ

DQP
DQ

DQ
DQ

DQ

B

B

B

B

B

F

F

F

F

NC

DQ

A
A

A

A

A
E

E
E

E

DQ
DQ
DQ
DQP
DQ

DQ
DQ
DQ

A

A
A
A

E

E

E
E
E

Pin Definitions

Name I/O Description

, A1, A Input-

A

0

BWA, BWB,
BW

, BWD,

C

, BWF,

BW

E

BW

, BW

G

GW

H

Synchronous

Input-

Synchronous

Input-

Synchronous

BWE

Input-

Synchronous

CLK Input-

Clock

CE

1

Input-

Synchronous

Document #: 38-05383 Rev. *E Page 6 of 31

Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP
A1: A0 are fed to the two-bit counter.

Byte Write Select Inputs, active LOW. Qualified with BWE
SRAM. Sampled on the rising edge of CLK.

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are written, regardless of the values on BW
BWE

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
sampled only when a new external address is loaded.

or ADSC is active LOW, and CE1, CE2, and CE

[2]

are sampled active.

3

to conduct byte writes to the

).

is asserted LOW, during a burst operation.

and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is

2

and

X

[+] Feedback

Pin Definitions (continued)

Name I/O Description

CE

2

CE

3

OE

ADV Input-

ADSP

ADSC

ZZ Input-

DQs, DQP

V

DD

V

SS

V

SSQ

V

DDQ

X

MODE Input-

TDO JTAG serial

TDI JT AG serial input

TMS JT AG serial input

TCK JTAG-

NC – No Connects. Not internally connected to the die
NC/72M,

NC/144M,
NC/288M,
NC/576M,
NC/1G

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
address is loaded.

and CE3 to select/deselect the device. CE2 is sampled only when a new external

1

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
connected for BGA. Where referenced, CE
for BGA. CE

and CE2 to select/deselect the device. Not available for AJ package version. Not

1

is sampled only when a new external address is loaded.

3

is assumed active throughout this document

3

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.

Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted,

Synchronous

Input-

Synchronous

it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both

Input-

Synchronous

asserted, only ADSP
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented to the device are captured in the address

is recognized. ASDP is ignored when CE1 is deasserted HIGH.

registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP

is recognized.

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a

Asynchronous

non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous
read cycle. The direction of the pins is controlled by OE
pins behave as outputs. When HIGH, DQs and DQP

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

I/O Ground Ground for the I/O circuitry.

I/O Power Supply Power supply for the I/O circuitry.

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V

Static

or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull-up.

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the

output

Synchronous

JT AG feature is not being utilized, this pin should be disconnected. This pin is not available
on TQFP packages.

Serial data-In to the JT AG circuit. Sampled on the rising edge of TCK. If the JT AG feature

Synchronous

is not being utilized, this pin can be disconnected or connected to V
available on TQFP packages.

Serial data-In to the JT AG circuit. Sampled on the rising edge of TCK. If the JT AG feature

Synchronous

is not being utilized, this pin can be disconnected or connected to V
available on TQFP packages.

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must

Clock

be connected to V

. This pin is not available on TQFP packages.

SS

– No Connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M

and NC/1G are address expansion pins are not internally connected to the die.

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

clock rise of the

. When OE is asserted LOW, the

are placed in a tri-state cond i ti on .

X

. This pin is not

DD

. This pin is not

DD

DD

Document #: 38-05383 Rev. *E Page 7 of 31

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CY7C1442AV33
CY7C1446AV33

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(250-MHz device).

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
supports secondary cache in systems utilizing either a linear
or interleaved burst sequence. The interleaved burst order
supports Pentium and i486™ processors. The linear burst
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is deter­mined by sampling the MODE input. Accesses can be initiated
with either the Processor Address Strobe (ADSP
Controller Address Strobe (ADSC
through the burst sequence is controlled by the ADV
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.

Byte Write operations are qualified with the Byte Write Enable
(BWE

) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
is HIGH.

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP
(2) CE
signals (GW

is HIGH. The address presented to the address inputs (A)

CE

1

is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP
ately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
(2) CE
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW

inputs are ignored during this first cycle.

ADV
ADSP-triggered Write accesses require two clock cycles to

complete. If GW
data presented to the DQs inputs is written into the corre­sponding address location in the memory array. If GW

Document #: 38-05383 Rev. *E Page 8 of 31

) overrides all Byte Write inputs and writes data to

, CE2, CE3 are all asserted active, and (3) the Write

1

, BWE) are all deserted HIGH. ADSP is ignored if

or ADSC signals, its output will tri-state immedi-

, CE2, CE3 are all asserted active. The address

1

is asserted LOW on the second clock rise, the

). Address advancement

, CE2, CE3) and an

1

) provide for easy bank

or ADSC is asserted LOW,

is asserted LOW, and

, BWE, and BWX) and

) is 2.6ns

CO

) or the

input. A

is ignored if CE

is active

is HIGH,

then the Write operation is controlled by BWE
signals.

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
provides Byte Write capability that is described in the Write
Cycle Descriptions table. Asserting the Byte Write Enable
input (BWE
selectively write to only the desired bytes. Bytes not selected
during a Byte Write operation will remain unaltered. A
synchronous self-timed Write mechanism has been provided
to simplify the Write operations.

Because CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
is a common I/O device, the Output Enable (OE
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi­tions are satisfied: (1) ADSC
deserted HIGH, (3) CE
(4) the appropriate combination of the Write inputs (GW
and BW
byte(s). ADSC
cycle to complete. The address presented to A is loaded into
the address register and the address advancement logic while
being delivered to the memory array. The ADV
during this cycle. If a global Write is conducted, the data

1

presented to the DQs is written into the corresponding address
location in the memory core. If a Byte Write is conducted, only
the selected bytes are written. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.

Because CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE

Burst Sequences

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
provides a two-bit wraparound counter, fed by A1: A0, that
implements either an interleaved or linear burst sequence. The
interleaved burst sequence is designed specifically to support
Intel Pentium applications. The linear burst sequence is
designed to support processors that follow a linear burst
sequence. The burst sequence is user selectable through the
MODE input. Asserting ADV
cally increment the burst counter to the next address in the
burst sequence. Both Read and Write burst operations are
supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering

the

“sleep” mode. CE
remain inactive for the duration of t
returns LOW.

) with the selected Byte Write (BWX) input, will

is asserted LOW, (2) ADSP is

, CE2, CE3 are all asserted active, and

1

) are asserted active to conduct a Write to the desired

X

-triggered Write accesses require a single clock

LOW at clock rise will automati-

, CE2, CE3, ADSP, and ADSC must

1

after the ZZ input

ZZREC

and BW

) must be

.

, BWE,

input is ignored

.

X

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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

Interleaved Burst Address Table
(MODE = Floating or V

First

Address

A1: A0

Second

Address

A1: A0

DD

)

Third

Address

A1: A0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Fourth

Address

A1: A0

Linear Burst Address Table (MODE = GND)

First

Address

A1: A0

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

ZZ Mode Electrical Characteristics

Parameter Description T est Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Truth Table

Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State
Sleep Mode, Power Down None X X X H X X X X X X Tri-State
READ Cycle, Begin Burst External L H L L L X X X L L-H Q
READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-St a te
WRITE Cycle, Begin Burst External L H L L H L X L X L-H D
READ Cycle, Begin Burst External L H L L H L X H L L-H Q
READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
READ Cycle, Continue Burst Next X X X L H H L H L L-H Q
READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
READ Cycle, Continue Burst Next H X X L X H L H L L-H Q

READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D
WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D
READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q

Sleep mode standby current ZZ > VDD – 0.2V 100 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ Active to sleep current This parameter is sampled 2t

CYC

CYC

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

[2, 3, 4, 5, 6, 7]

ns
ns
ns

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3. WRITE

4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

5. CE

6. The SRAM always initiates a read cycle when ADSP

7. OE

= L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.

, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.

1

after the ADSP
don't care for the remainder of the write cycle.

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a re ad cycle all dat a bit s a re Tri-State when OE is

inactive or when the device is deselected, and all data bits behave as output when OE

or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a

Document #: 38-05383 Rev. *E Page 9 of 31

is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks

is active (LOW).

[+] Feedback

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

Truth Table (continued)

[2, 3, 4, 5, 6, 7]

Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q
READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D
WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D

Truth Table for Read/Write

Function (CY7C1440AV33) GW BWE BW

[4,8,9]

D

BW

C

BW

B

BW

A

Read HHXXXX
Read HLHHHH
Write Byte A – (DQ
Write Byte B – (DQ

and DQPA) HLHHHL

A

and DQPB)HLHHLH

B

Write Bytes B, A H L H H L L
Write Byte C – (DQ

and DQPC) HLHLHH

C

Write Bytes C, A H L H L H L
Write Bytes C, B H L H L L H
Write Bytes C, B, A H L H L L L
Write Byte D – (DQ

and DQPD) HL LHHH

D

Write Bytes D, A H L L H H L
Write Bytes D, B H L L H L H
Write Bytes D, B, A H L L H L L
Write Bytes D, C H L L L H H
Write Bytes D, C, A H L L L H L
Write Bytes D, C, B HLLLLH
Write All Bytes HLLLLL
Write All Bytes LXXXXX

Truth Table for Read/Write

[4, 8, 9]

Function (CY7C1442AV33) GW BWE BW

Read H H X X
Read H L H H
Write Byte A – (DQ
Write Byte B – (DQ

and DQPA)HLHL

A

and DQPB)HLLH

B

Write Bytes B, A H L L L
Write All Bytes H L L L
Write All Bytes L X X X

Notes:

represents any byte write signal. To enable any byte write BWx, a Logic LOW signal should be applied at clock rise.Any number of bye writes can be enabled

8. BW

x

at the same time for any given write.

9. Table only lists a partial listing of the byte wr ite combinations. Any combination of BW

Document #: 38-05383 Rev. *E Page 10 of 31

B

is valid. Appropriate write will be done based on which byte write is active.

X

BW

A

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CY7C1440AV33

T

O

CY7C1442AV33
CY7C1446AV33

Truth Table for Read/Write

Function (CY7C1446AV33) GW BWE BW

[4, 8, 9]

X

Read HHX
Read H L All BW
Write Byte x – (DQ

and DQPx)HLL

x

Write All Bytes H L All BW

= H

= L

Write All Bytes L X X

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 incor­porates a serial boundary scan test access port (TAP). This
part is fully compliant with IEEE Standard 1149.1. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.

The CY7C1440AV33/CY7C1442A V33/CY 7C1446A V33 contains
a TAP controller, instruction register, boundary scan register,
bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V

) to prevent clocking of the device. TDI and TMS are inter-

SS

nally pulled up and may be unconnected. They may alternately
be connected to V
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.

through a pull-up resistor. TDO should be

DD

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-

TAP Controller State Diagram

TEST-LOGIC

1

RESET

0

0

RUN-TEST/

IDLE

1

DR-SCAN

1 1

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

0 0

EXIT2-DR

UPDATE-DR

1 0

1

SELECT

0

0

0 0

1

1 1

0 0

0

1

1

SELECT

IR-SCAN

0

CAPTURE-IR

0

SHIFT-IR

1

EXIT1-IR

PAUSE-IR

1

EXIT2-IR

1

UPDATE-IR

1

0

1

0

icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

0

Bypass Register

012

TDI TD

Selection

Circuitry

Instruction Register

012293031 ...

Identification Register

012..x ...

Boundary Scan Register

S

election

Circuitr

y

The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.

Document #: 38-05383 Rev. *E Page 11 of 31

TCK

MS TAP CONTROLLER

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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (V
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.

At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.

When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be pla ced betwee n the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V

) when the BYPASS instruction is executed.

SS

Boundary Scan Register

The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.

The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.

PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells pri-

) for five

DD

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc­tions are described in detail below.

Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction reg ister
upon power-up or whenever the TAP controller is given a test
logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next comman d is
given during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1 149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the in­struction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is cap­tured in the boundary scan register.

The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possi­ble that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value th at will be
captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (t
captured correctly if there is no way in a design to stop (o r
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK
boundary scan register.

Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the bound­ary scan register between the TDI and TDO pins.

or to the selection of another boundary scan test operation.

and tCH). The SRAM clock input might not be

CS

captured in the

Document #: 38-05383 Rev. *E Page 12 of 31

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123456

T

CY7C1442AV33
CY7C1446AV33

The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.

TAP Timing

Test Clock

(TCK)

t

TMSS

t

t

TMSH

TH

The boundary scan register has a special bit located at, bit #89
(for 165-FBGA package) or bit #138 (for 209-FBGA package).
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

t

TL

t

CYC

est Mode Select

(TMS)

Test Data-In

(TDI)

Test Data-Out

(TDO)

t

TDIS

t

TDIH

DON’T CARE UNDEFINED

t

TDOX

t

TDOV

Document #: 38-05383 Rev. *E Page 13 of 31

[+] Feedback

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T

F

T

F

CY7C1442AV33
CY7C1446AV33

TAP AC Switching Characteristics Over the operating Range

[10, 11]

Parameter Description Min. Max. Unit

Clock

t

TCYC

t

TF

t

TH

t

TL

TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH time 20 ns
TCK Clock LOW time 20 ns

Output Times

t

TDOV

t

TDOX

TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns

Set-up Times

t

TMSS

t

TDIS

t

CS

TMS Set-up to TCK Clock Rise 5 ns
TDI Set-up to TCK Clock Rise 5 ns
Capture Set-up to TCK Rise 5 ns

Hold Times

t

TMSH

t

TDIH

t

CH

3.3V TAP AC Test Conditions

Input pulse levels ............................................... VSS to 3.3V

Input rise and fall times....................................................1ns

Input timing reference levels...........................................1.5V

Output reference levels...................................................1.5V

Test load termination supply voltage...............................1.5V

TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns

2.5V TAP AC Test Conditions

Input pulse levels.................................................VSS to 2.5V

Input rise and fall time .....................................................1 ns

Input timing reference levels.........................................1.25V

Output reference levels ................................................1.25V

Test load termination supply voltage ............................1.25V

3.3V TAP AC Output Load Equivalent

1.5V

50Ω

DO

Z = 50Ω

O

Notes:

and t

10.t

CS

11.Test conditions are specified using the load in TAP AC test Conditions. t

refer to the set-up and hold time requirements of latching data from the boundary scan register.

CH

20p

2.5V TAP AC Output Load Equivalent

DO

Z = 50Ω

O

= 1 ns.

R/tF

1.25V

50Ω

20p

Document #: 38-05383 Rev. *E Page 14 of 31

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CY7C1442AV33
CY7C1446AV33

TAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; V

Parameter Description Test Conditions Min. Max. Unit

V

OH1

V

OH2

V

OL1

V

OL2

V

IH

V

IL

I

X

= 3.135 to 3.6V unless otherwise noted)

DD

Output HIGH Voltage IOH = –4.0 mA, V

IOH = –1.0 mA, V

Output HIGH Voltage IOH = –100 µA V

Output LOW Voltage IOL = 8.0 mA V

I

= 1.0 mA V

OL

Output LOW Voltage IOL = 100 µA V

Input HIGH Volt age V

Input LOW Voltage V

Input Load Current GND < VIN < V

[12]

= 3.3V 2.4 V

DDQ

= 2.5V 2.0 V

DDQ

= 3.3V 2.9 V

DDQ

V

= 2.5V 2.1 V

DDQ

= 3.3V 0.4 V

DDQ

= 2.5V 0.4 V

DDQ

= 3.3V 0.2 V

DDQ

V

= 2.5V 0.2 V

DDQ

= 3.3V 2.0 VDD + 0.3 V

DDQ

V

= 2.5V 1.7 VDD + 0.3 V

DDQ

= 3.3V –0.3 0.8 V

DDQ

V

= 2.5V –0.3 0.7 V

DDQ

DDQ

–5 5 µA

Identification Register Definitions

Instruction Field

(1M x 36)

Revision Number (31:29) 000 000 000 Describes the version number.

CY7C1440AV33

Device Depth (28:24)

[13]

01011 01011 01011 Reserved for Internal Use

Architecture/Memory Type(23:18) 000000 000000 000000 Defines memory type and

Bus Width/Density(17:12) 100111 010111 110111 Defines width and density
Cypress JEDEC ID Code (11:1) 00000110100 00000110100 00000110100 Allows unique identification of

ID Register Presence Indicator (0) 1 1 1 Indicates the presence of an ID

CY7C1442AV33

(2M x 18)

CY7C1446AV33

(512K x 72) Description

architecture

SRAM vendor.

register.

Scan Register Sizes

Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72)

Instruction 3 3 3
Bypass 1 1 1
ID 32 32 32
Boundary Scan Order (165-ball FBGA package) 89 89 –
Boundary Scan Order (209-ball FBGA package) – – 138

Identification Codes

Instruction Code Description

EXTEST 000 Captures the I/O ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

Notes:

12.All voltages referenced to V

13.Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.

(GND).

SS

Document #: 38-05383 Rev. *E Page 15 of 31

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Identification Codes (continued)

Instruction Code Description

SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

165-ball FBGA Boundary Scan Order

CY7C1440AV33 (1M x 36), CY7C1442AV33 (2M x 18)

Bit # ball ID Bit # ball ID Bit # ball ID Bit # ball ID

1
2
3N10 28G10 53B2 78P1
4P11 29F10 54C2 79R1
5 P8 30 E10 55 B1 80 R2
6 R8 31 D10 56 A1 81 P3
7R9 32C11 57C1 82R3
8P9 33A11 58D1 83P2
9P10 34B11 59E1 84R4

10 R10 35 A10 60 F1 85 P4

11 R11 36 B10 61 G1 86 N5
12 H11 37 A9 62 D2 87 P6
13 N11 38 B9 63 E2 88 R6
14 M11 39 C10 64 F2 89 Internal
15 L11 40 A8 65 G2
16 K11 41 B8 66 H1
17 J11 42 A7 67 H3
18 M10 43 B7 68 J1
19 L10 44 B6 69 K1
20 K10 45 A6 70 L1
21 J10 46
22 H9 47
23 H10 48 A4 73 K2
24 G11 49 B4 74 L2
25 F11 50 B3 75 M2

N6
N7

26 E11 51 A3 76 N1
27 D11 52 A2 77 N2

[14,15]

B5
A5

71 M1
72 J2

Notes:

14.Balls that are NC (No Connect) are preset LOW.

15.Bit# 89 is preset HIGH.

Document #: 38-05383 Rev. *E Page 16 of 31

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CY7C1446AV33

209-ball FBGA Boundary Scan Order

CY7C1446AV33 (512K x 72)

Bit # ball ID Bit # ball ID Bit # ball ID Bit # ball ID

1
2
3 U6 38 K9 73 B6 108 K6
4 W7 39 K10 74 A6 109 K2
5V7 40J11 75A5 110L2
6 U7 41 J10 76 B5 111 L1
7T7 42H11 77C5 112M2
8 V8 43 H10 78 D5 113 M1
9 U8 44 G11 79 D4 114 N2

10 T8 45 G10 80 C4 115 N1

11 V9 46 F11 81 A4 116 P2
12 U9 47 F10 82 B4 117 P1
13 P6 48 E10 83 C3 118 R2
14 W11 49 E11 84 B3 119 R1
15 W10 50 D11 85 A3 120 T2
16 V11 51 D10 86 A2 121 T1
17 V10 52 C11 87 A1 122 U2
18 U11 53 C10 88 B2 123 U1
19 U10 54 B11 89 B1 124 V2
20 T11 55 B10 90 C2 125 V1
21 T10 56 A1 1 91 C1 126 W2
22 R11 57 A10 92 D2 127 W1
23 R10 58 C9 93 D1 128 T6
24 P11 59 B9 94 E1 129 U3
25 P10 60 A9 95 E2 130 V3
26 N11 61 D7 96 F2 131 T4
27 N10 62 C8 97 F1 132 T5
28 M11 63 B8 98 G1 133 U4
29 M10 64 A8 99 G2 134 V4
30 L11 65 D8 100 H2 135 5W
31 L10 66 C7 101 H1 136 5V
32 K11 67 B7 102 J2 137 5U
33 M6 68 A7 103 J1 138 Internal
34 L6 69 D6 104 K1
35 J6 70

W6

V6

36 F6 71
37 K8 72 C6 107 K4

[14, 16]

G6

H6

105 N6

106 K3

Note:

16.Bit# 138 is preset HIGH.

Document #: 38-05383 Rev. *E Page 17 of 31

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Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V
Supply Voltage on V

Relative to GND........–0.3V to +4.6V

DD

Relative to GND......–0.3V to +V

DDQ

DD

DC Voltage Applied to Outputs

in Tri-State........................................... –0.5V to V

DDQ

+ 0.5V

Electrical Characteristics Over the Operating Range

DC Input Voltage.......................... .. ... ....–0.5V to V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current...................................... ... ........... > 200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%
Industrial –40°C to +85°C

[17, 18]

Ambient

Temperature V

DD

+ 0.5V

DD

V

to V

DDQ

DD

DC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Max. Unit

V
V

DD
DDQ

Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage for 3.3V I/O 3.135 V

DD

for 2.5V I/O 2.375 2.625 V

V

OH

V

OL

V

IH

V

IL

Output HIGH Voltage for 3.3V I/O, I

for 2.5V I/O, I

Output LOW Voltage for 3.3V I/O, I

for 2.5V I/O, I

Input HIGH Voltage

[17]

for 3.3V I/O 2.0 VDD + 0.3V V
for 2.5V I/O 1.7 V

Input LOW Voltage

[17]

for 3.3V I/O –0.3 0.8 V

= −4.0 mA 2.4 V

OH

= −1.0 mA 2.0 V

OH

= 8.0 mA 0.4 V

OL

= 1.0 mA 0.4 V

OL

+ 0.3V V

DD

for 2.5V I/O –0.3 0.7 V

I

I
I

X

OZ
DD

Input Leakage Current

GND ≤ VI ≤ V

except ZZ and MODE
Input Current of MODE Input = V

Input = V

Input Current of ZZ Input = V

Input = V

SS
DD
SS
DD

Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply

Current

V

DD

f = f

= Max., I

= 1/t

MAX

DDQ

–5 5 µA

–30 µA

–5 µA

Output Disabled –5 5 µA

DDQ,

OUT

CYC

= 0 mA,

4-ns cycle, 250 MHz 475 mA
5-ns cycle, 200 MHz 425 mA

5 µA

30 µA

6-ns cycle, 167 MHz 375 mA

I

SB1

I

SB2

I

SB3

I

SB4

Notes:

17.Overshoot: V

18.T

Power-up

Automatic CE
Power-down
Current—TTL Inputs

Automatic CE
Power-down
Current—CMOS Inputs

Automatic CE
Power-down
Current—CMOS Inputs

Automatic CE
Power-down
Current—TTL Inputs

(AC) < VDD +1.5V (Pulse width less than t

IH

: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and V

V

= Max, Device Deselected,

DD

V

≥ VIH or VIN ≤ V

IN

f = f
V

V
f = 0

V
V
f = f

V
V

= 1/t

MAX

= Max, Device Deselected,

DD

≤ 0.3V or VIN > V

IN

= Max, Device Deselected, or

DD

≤ 0.3V or VIN > V

IN

= 1/t

MAX

= Max, Device Deselected,

DD

≥ VIH or VIN ≤ VIL, f = 0

IN

/2), undershoot: VIL(AC) > –2V (Pulse width less than t

CYC

IL

CYC

DDQ

DDQ

CYC

All speeds 225 mA

All speeds 120 mA

– 0.3V,

All speeds 200 mA

– 0.3V

All speeds 135 mA

DDQ

< V

DD.

CYC

/2).

V

Document #: 38-05383 Rev. *E Page 18 of 31

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CY7C1446AV33

Capacitance

[19]

Parameter Description Test Conditions

CIN Input Capacitance TA = 25°C, f = 1 MHz,

V

= 3.3V

C

CLK

C

I/O

Clock Input Capacitance 3 7 5 pF
Input/Output Capacitance 5.5 6 7 pF

Thermal Resistance

[19]

V

DD

DDQ

= 2.5V

Parameter Description Test Conditions

Θ

JA

Θ

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA/JESD51.

AC Test Loads and Waveforms

3.3V I/O Test Load

OUTPUT

Z

= 50Ω

0

R

L

VT= 1.5V

(a) (b)

3.3V

OUTPUT

= 50Ω

5pF

INCLUDING

JIG AND

SCOPE

2.5V I/O Test Load

OUTPUT

= 50Ω

Z

0

= 1.25V

V

T

R

L

(a) (b)

Note:

19.Tested initially and after any design or process change that may affect these parameters.

2.5V

OUTPUT

= 50Ω

5pF

INCLUDING

JIG AND

SCOPE

R = 317Ω

R = 351Ω

R = 1667Ω

R = 1538Ω

100 TQFP

Max.

165 FBGA

Max.

209 FBGA

Max. Unit

6.5 7 5 pF

100 TQFP

Package

165 FBGA

Package

209 FBGA

Package

25.21 20.8 25.31 °C/W

2.28 3.2 4.48 °C/W

V

DDQ

GND

≤ 1ns

ALL INPUT PULSES

10%

90%

90%

10%

(c)

V

GND

DDQ

≤ 1ns

ALL INPUT PULSES

10%

90%

90%

10%

(c)

Unit

≤ 1ns

≤ 1ns

Document #: 38-05383 Rev. *E Page 19 of 31

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Switching Characteristics Over the Operating Range

Parameter Description

t

POWER

Clock

t

CYC

t

CH

t

CL

Output Times

t

CO

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Set-up Times

t

AS

t

ADS

t

ADVS

t

WES

t

DS

t

CES

Hold Times

t

AH

t

ADH

t

ADVH

t

WEH

t

DH

t

CEH

VDD(Typical) to the first Access

Clock Cycle Time 4.0 5 6 ns
Clock HIGH 1.5 2.0 2.4 ns
Clock LOW 1.5 2.0 2.4 ns

Data Output V alid After CLK Rise 2.6 3.2 3.4 ns
Data Output Hold After CLK Rise 1.0 1.5 1.5 ns
Clock to Low-Z
Clock to High-Z

[21, 22, 23]

[21, 22, 23]

OE LOW to Output Valid 2.6 3.0 3.4 ns
OE LOW to Output Low-Z
OE HIGH to Output High-Z

Address Set-up Before CLK Rise 1.2 1.4 1.5 ns
ADSC, ADSP Set-up Before CLK Rise 1.2 1.4 1.5 ns
ADV Set-up Before CLK Rise 1.2 1.4 1.5 ns
GW, BWE, BWX Set-up Before CLK Rise 1.2 1.4 1.5 ns
Data Input Set-up Before CLK Rise 1.2 1.4 1.5 ns
Chip Enable Set-up Before CLK Rise 1.2 1.4 1.5 ns

Address Hold After CLK Rise 0.3 0.4 0.5 ns
ADSP, ADSC Hold After CLK Rise 0.3 0.4 0.5 ns
ADV Hold After CLK Rise 0.3 0.4 0.5 ns
GW, BWE, BWX Hold After CLK Rise 0.3 0.4 0.5 ns
Data Input Hold After CLK Rise 0.3 0.4 0.5 ns
Chip Enable Hold After CLK Rise 0.3 0.4 0.5 ns

[20]

[21, 22, 23]

[21, 22, 23]

[24, 25]

–250 –200 –167

UnitMin. Max Min. Max. Min. Max

111ms

1.0 1.3 1.5 ns

2.6 3.0 3.4 ns

000ns

2.6 3.0 3.4 ns

Notes:

20.This part has a voltage regulator internally; t
can be initiated.

, t

21.t

CHZ

22.At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but ref lect p arame te rs guarant eed over worst case user condit ions. Device is d esigned
to achieve High-Z prior to Low-Z under the same system conditions.

23.This parameter is sampled and not 100% tested.

24.Timing reference level is 1.5V when V

25.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

CLZ,tOELZ

, and t

are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

OEHZ

POWER

OEHZ

= 3.3V and is 1.25V when V

DDQ

Document #: 38-05383 Rev. *E Page 20 of 31

is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation

is less than t

OELZ

and t

is less than t

CHZ

= 2.5V.

DDQ

to eliminate bus contention between SRAMs when sharing the same

CLZ

[+] Feedback

Switching Waveforms

D

Read Cycle Timing

[26]

t

CYC

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

CLK

ADSP

ADSC

ADDRESS

GW, BWE,

BWx

CE

ADV

OE

ata Out (Q)

t

ADS

t

t

AS

CES

t

t

CL

CH

t

ADH

t

t

ADH

ADS

t

AH

A1

t

WES

t

CEH

High-Z

Single READ BURST READ

A2 A3

t

WEH

t

t

ADVH

ADVS

ADV
suspends
burst.

t

t

t

CLZ

t

CO

OEHZ

Q(A1)

OEV

t

OELZ

t

CO

t

DOH

Q(A2) Q(A2 + 1) Q(A2 + 2)

Burst continued with
new base address

Deselect
cycle

t

CHZ

Q(A2) Q(A2 + 1)Q(A2 + 3)

Burst wraps around
to its initial state

Note:

26.On this diagram, when CE

is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05383 Rev. *E Page 21 of 31

DON’T CARE

UNDEFINED

[+] Feedback

Switching Waveforms (continued)

D

Write Cycle Timing

[26, 27]

t

CYC

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

CLK

ADSP

ADSC

ADDRESS

BWE,

BW

GW

ADV

t

t

CL

CH

t

t

ADH

ADS

t

t

ADH

ADS

t

t

AH

AS

A1

Byte write signals are
ignored for first cycle when
ADSP initiates burst

X

t

t

CEH

CES

CE

A2 A3

t

t

WEH

WES

ADV suspends burst

ADSC extends burst

t

ADS

t

ADH

t

t

ADVS

WES

t

WEH

t

ADVH

OE

Data In (D)

ata Out (Q)

High-Z

BURST READ BURST WRITE

t

OEHZ

Note:

27.

Full width write can be initiated by either GW

t

t

DH

DS

D(A1)

Single WRITE

D(A2) D(A2 + 1) D(A2 + 1)

DON’T CARE

LOW; or by GW HIGH, BWE LOW and BWX LOW.

UNDEFINED

D(A2 + 2)

D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

Extended BURST WRITE

Document #: 38-05383 Rev. *E Page 22 of 31

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Switching Waveforms (continued)

D

Read/Write Cycle Timing

[26, 28, 29]

t

CYC

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

CLK

ADSP

ADSC

ADDRESS

BWE,

BW

X

CE

ADV

OE

Data In (D)

t

t

CL

CH

t

t

ADH

ADS

t

t

AH

AS

High-Z

t

CES

A2

t

CEH

t

CO

t

CLZ

t

OEHZ

t

WES

t

DS

A3

t

D(A3)

A1

A4 A5 A6

t

WEH

DH

t

OELZ

D(A5) D(A6)

ata Out (Q)

Notes:

28.The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP
is HIGH.

29.GW

High-Z

Q(A2)Q(A1)

Single WRITE

DON’T CARE UNDEFINED

Q(A4) Q(A4+1) Q(A4+2)

BURST READBack-to-Back READs

or ADSC

.

Q(A4+3)

Back-to-Back

WRITEs

Document #: 38-05383 Rev. *E Page 23 of 31

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Switching Waveforms (continued)

A

ZZ Mode Timing

[30, 31]

CLK

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

t

ZZ

t

ZZREC

ZZ

I

SUPPLY

LL INPUTS

(except ZZ)

Outputs (Q)

t

ZZI

I

DDZZ

High-Z

t

RZZI

DESELECT or READ Only

DON’T CARE

Notes:

30.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

31.DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05383 Rev. *E Page 24 of 31

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Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

Speed

(MHz) Ordering Code

167 CY7C1440AV33-167AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1442AV33-167AXC
CY7C1440AV33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1442AV33-167BZC
CY7C1440AV33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1442AV33-167BZXC
CY7C1446AV33-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1446AV33-167BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
CY7C1440AV33-167AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial
CY7C1442AV33-167AXI
CY7C1440AV33-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1442AV33-167BZI
CY7C1440AV33-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1442AV33-167BZXI
CY7C1446AV33-167BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1446AV33-167BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

200 CY7C1440AV33-200AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1442AV33-200AXC
CY7C1440AV33-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1442AV33-200BZC
CY7C1440AV33-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1442AV33-200BZXC
CY7C1446AV33-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1446AV33-200BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
CY7C1440AV33-200AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial
CY7C1442AV33-200AXI
CY7C1440AV33-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1442AV33-200BZI
CY7C1440AV33-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1442AV33-200BZXI
CY7C1446AV33-200BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1446AV33-200BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

visit www.cypress.com for actual products offered.

Package
Diagram Part and Package Type

Operating

Range

Document #: 38-05383 Rev. *E Page 25 of 31

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CY7C1442AV33
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Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

Speed

(MHz) Ordering Code

250 CY7C1440AV33-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1442AV33-250AXC
CY7C1440AV33-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1442AV33-250BZC
CY7C1440AV33-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1442AV33-250BZXC
CY7C1446AV33-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1446AV33-250BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
CY7C1440AV33-250AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
CY7C1442AV33-250AXI
CY7C1440AV33-250BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1442AV33-250BZI
CY7C1440AV33-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1442AV33-250BZXI
CY7C1446AV33-250BGI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1446AV33-250BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free

visit www.cypress.com for actual products offered.

Package
Diagram Part and Package Type

Operating

Range

Document #: 38-05383 Rev. *E Page 26 of 31

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Package Diagrams

R 0.08 MIN.

0.20 MAX.

0.25

GAUGE PLANE

0°-7°

0.60±0.15

1.00 REF.

20.00±0.10

22.00±0.20

100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)

16.00±0.20

14.00±0.10

100

1

30

31 50

0° MIN.

R 0.08 MIN.

0.20 MAX.

0.20 MIN.

A

DETAIL

81

80

0.30±0.08

0.65
TYP.

51

STAND-OFF

0.05 MIN.

0.15 MAX.

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

1.40±0.05

12°±1°

(8X)

SEATING PLANE

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

51-85050-*B

SEE DETAIL

0.20 MAX.

1.60 MAX.

0.10

A

Document #: 38-05383 Rev. *E Page 27 of 31

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Package Diagrams (continued)

TOP VIEW

PIN 1 CORNER

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)

1110986754321

1.00

14.00

17.00±0.10

7.00

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

Ø0.05 M C

Ø0.25 M C A B

PIN 1 CORNER

1

2345678910

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

BOTTOM VIEW

11

Ø0.45±0.05(165X)

A

+0.05

0.25 C

0.53±0.05

SEATING PLANE

C

0.36

-0.10

0.15 C

0.35

1.40 MAX.

B

0.15(4X)

5.00

15.00±0.10

1.00

10.00

51-85165-*A

Document #: 38-05383 Rev. *E Page 28 of 31

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Package Diagrams (continued)

209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

i486 is a trademark, and Intel and Pentium are registered trademarks of Intel C orporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05383 Rev. *E Page 29 of 31

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change wi t hou t notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not auth orize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypre ss

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

51-85167-**

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CY7C1442AV33
CY7C1446AV33

Document History Page

Document Title: CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit (1 M x 36/2M x 18/512K x 72) Pipelined Sync

SRAM

Document Number: 38-05383

REV. ECN NO. Issue Date

** 124437 03/04/03 CJM New data sheet

*A 254910 See ECN SYT Part number changed from previous revision. New and old part number differ

*B 306335 See ECN SYT Changed H9 pin from V

*C 332173 See ECN SYT Modified Address Expansion balls in the pinouts for 165 FBGA and 209

*D 417547 See ECN RXU Converted from Preliminary to Final

Orig. of

Change Description of Change

by the letter “A”
Modified Functional Block diagrams
Modified switching waveforms
Added Boundary scan information
Added Footnote #14 (32-Bit Vendor ID Code changed)
Added I
Added t
Removed 119 PBGA package

, IX and ISB values in the DC Electrical Characteristics

DD

specifications in Switching Characteristics table

POWER

Changed 165 FBGA package from BB165C (15 x 17 x 1.20 mm) to BB165
(15 x 17 x 1.40 mm)
Changed 209-Lead PBGA BG209 (14 x 22 x 2.20 mm) to BB209A (14 x 22
x 1.76 mm)

to VSS on the Pin Configuration table for 209
FBGA on Page # 6
Changed tCO from 3.0 to 3.2 ns and t
speed bin on the Switching Characteristics table on Page # 19
Changed Θ
TQFP Package on Pg # 19
Replaced
FBGA Packages on the Thermal Resistance Table

Θ

JA

JA

and Θ
and Θ

SSQ

from 1.3 ns to 1.5 ns for 200 Mhz

DOH

from TBD to 25.21 and 2.58 °C/W respectively for

JC

from TBD to respective Values for 165 BGA and 209

JC

Added lead-free information for 100-pin TQFP, 165 FBGA and 209 FBGA
Packages
Changed IDD from 450, 400 and 350 mA to 475, 425 and 375 mA for
frequencies of 250, 200 and 167 MHz respectively
Changed I

SB1 from 190, 180 and 170 mA to 225 mA for frequencies of 250,

200 and 167 MHz respectively
Changed ISB2 from 80 to 100 mA
Changed I

SB3 from 180, 170 and 160 mA to 200 mA for frequencies of 250,

200 and 167 MHz respectively
Changed ISB4 from 100 to 110 mA

FBGA Package as per JEDEC standards
Modified V
Changed C

OL, VOH

Package
Changed I
Added Industrial Temperature Grade

SB2

IN

, C

and I

CLK

test conditions

and C

SB4

to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA

I/O

from 100 and 110 mA to 120 and 135 mA respectively

Included the missing 100 TQFP Package Diagram
Updated the Ordering Information by Shading and Unshading MPNs as per
availability

Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed I
tively and also Changed I
µA respectively on page# 18
Modified test condition in note# 8 from V
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

current value in MODE from –5 & 30 µA to –30 & 5 µA respec-

X

current value in ZZ from –30 & 5 µA to –5 & 30

X

< V

IH

DD to VIH

Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information

< V

DD

Document #: 38-05383 Rev. *E Page 30 of 31

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Document Title: CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync

SRAM

Document Number: 38-05383

REV. ECN NO. Issue Date

*E 473650 See ECN VKN Added the Maximum Rating for Supply Voltage on V

Orig. of
Change Description of Change

Changed t
AC Switching Characteristics table.
Updated the Ordering Information table.

, t

from 25 ns to 20 ns and t

TH

TL

from 5 ns to 10 ns in TAP

TDOV

Relative to GND.

DDQ

Document #: 38-05383 Rev. *E Page 31 of 31

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