CY7C145, CY7C144
8K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
R/W
L
CE
L
OE
L
A
12L
A
0L
A
0R
A
12R
R/W
R
CE
R
OE
R
CE
R
OE
R
CE
L
OE
L
R/W
L
R/W
R
I/O7L
I/O
0L
I/ O 7R
I/ O
0R
INTERRUPT
SEMAPHORE
ARB I T RAT IO N
CONTROL
I/ O
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
SE M
L
SE M
R
BUSY
L BUS Y
R
INT
L
INT
R
M/S
(7C145) I/O
8L
I/ O
8R
)
[1, 2]
[2]
[1, 2]
[2]
Logic Block Diagram
CY7C144 CY7C1458K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
Features
■ True Dual-Ported memory cells that enable simultaneous
reads of the same memory location
■ 8K x 8 organization (CY7C144)
■ 8K x 9 organization (CY7C145)
■ 0.65-micron CMOS for optimum speed and power
■ High speed access: 15 ns
■ Low operating power: I
■ Fully asynchronous operation
■ Automatic power down
■ TTL compatible
■ Master/Slave select pin enables bus width expansion to
16/18 bits or more
■ Busy arbitration scheme provided
■ Semaphores included to permit software handshaking
between ports
■ INT flag for port-to-port communication
■ Available in 68-pin PLCC, 64-pin and 80-pin TQFP
■ Pb-free packages available
= 160 mA (max.)
CC
Functional Description
The CY7C144 and CY7C145 are high speed CMOS 8K x 8
and 8K x 9 dual-port static RAMs. Various arbitration schemes
are included on the CY7C144/5 to handle situations when
multiple processors access the same piece of data. Two ports
are provided permitting independent, asynchronous access
for reads and writes to any location in memory. The
CY7C144/5 can be used as a standalone 64/72-Kbit dual-port
static RAM or multiple devices can be combined in order to
function as a 16/18-bit or wider master/slave dual-port static
RAM. An M/S
wider memory applications without the need for separate
master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs,
communications status buffering, and dual-port
video/graphics memory.
Each port has independent control pins: chip enable (CE
read or write enable (R/W
and INT, are provided on each port. BUSY signals that
BUSY
the port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from
one port to the other to indicate that a shared resource is in
use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power down feature is
controlled independently on each port by a chip enable (CE
pin or SEM
pin is provided for implementing 16/18-bit or
), and output enable (OE). Two flags,
) permits
pin.
),
)
Notes
1. BUSY
is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06034 Rev. *D Revised December 10, 2008
(7 C 1 4 5
[+] Feedback
CY7C145, CY7C144
Pin Configurations
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
67
60
59
58
57
56
55
54
53
52
51
50
49
48
3132 3334353637383940414243
5 4 3 2 168 666564636261
A
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
A
2728 29 30
98 7 6
47
46
45
44
A
1R
A
2R
A
3R
A
4R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
25
26
6L
7LA8LA9L
A
A
10L
11L
V
CC
NC
NC
CE
L
SEM
L
R/WLOE
L
NC
I/O
I/O
1L
0L
A
A
6R
7RA8RA9R
A
10R
NC
NC
CE
R
SEM
R
R/W
R
OE
R
I/O
7R
GND
A
11R
A
5R
A
5L
NC
A
12L
A
12R
CY7C144/5
[3]
[4]
Notes
3. I/O
8R
on the CY7C145.
4. I/O
8L
on the CY7C145.
Figure 1. 68-Pin PLCC (Top View)
Figure 2. 64-Pin PLCC (Top View)
Document #: 38-06034 Rev. *D Page 2 of 21
[+] Feedback
CY7C145, CY7C144
Pin Configurations (continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
16
18
19
20
2122232425262728293031323334353736
383940
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
44
45
43
42
41
8079787776757473727170696867666465
636261
2L
3L
4L
5L
6L
7L
V
CC
0R
1R
2R
3R
4R
5R
CC
V
CC
OE
L
I/O0LI/O
8L
A
5L
A
12LA11LA10LA9LA8LA7LA6L
CELSEMLR/W
L
A
4L
A
3L
A
2L
A
1L
A
0L
GND
BUSY
L
M/S
A
0R
A
1R
A
2R
A
3R
A
4R
INT
L
GND
OE
R
6R
A
12RA11RA10R
A9RA8RA7RA
6R
NC
CE
R
SEM
R
R/W
R
CY7C145
BUSY
R
INT
R
I/O
8R
NCNCNC
NC
NC
NCNCNC
NC
NC
NC
NC
NC
A
5R
I/O
7R
NC
O
NC
I/O
1L
Figure 3. 80-Pin TQFP
Table 1. Pin Definitions
Left Port Right Port Description
I/O
0L−7L(8L)
A
0L−12L
CE
L
OE
L
R/W
L
SEM
INT
L
BUSY
M/S
V
CC
GND Ground
Table 2. Selection Guide
Maximum Access Time 15 25 35 55 ns
Maximum Operating Current 220 180 160 160 mA
Maximum Standby Current for I
Document #: 38-06034 Rev. *D Page 3 of 21
I/O
A
CE
OE
R/W
SEM
L
INT
BUSY
L
Description
0R−7R(8R)
0R−12R
R
R
R
R
R
Data bus Input/Output
Address Lines
Chip Enable
Output Enable
Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least significant bits of the address lines will determine which semaphore to write or read. The I/O
when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location.
Interrupt Flag. INTL is set when right port writes location 1FFE and is cleared when left port reads
location 1FFE. INT
location 1FFF.
Busy Flag
R
Master or Slave Select
Power
SB1
is set when left port writes location 1FFF and is cleared when right port reads
R
7C144-15
7C145-15
60 40 30 30 mA
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
pin is used
0
Unit
[+] Feedback
CY7C145, CY7C144
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage to Ground Potential .................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .....................................................−0.5V to +7.0V
DC Input Voltage
[6]
..............................................−0.5V to +7.0V
[5]
Electrical Characteristics Over the Operating Range
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial 0°C to +70°C 5V ± 10%
Industrial −40°C to +85°C 5V ± 10%
Ambient
Tem per atur e V
CC
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
I
I
I
OH
OL
IH
IL
IX
OZ
CC
SB1
SB2
SB3
SB4
Output HIGH Voltage VCC = Min., IOH = −4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V
Input HIGH Voltage 2.2 2.2 V
Input LOW Voltage 0.8 0.8 V
Input Leakage Current GND < VI < V
CC
Output Leakage Current Outputs Disabled, GND < VO < V
Operating Current VCC = Max., I
Outputs Disabled
Standby Current
(Both Ports TTL Levels)
Standby Current
(One Port TTL Level)
Standby Current
(Both Ports CMOS Levels)
Standby Current
(One Port CMOS Level)
CEL and CER > VIH,
f = f
CEL or CER > VIH,
f = f
MAX
MAX
[7]
[7]
Both Ports
and CER > VCC – 0.2V,
CE
V
> VCC – 0.2V
IN
or V
< 0.2V, f = 0
IN
One Port
or CER > VCC – 0.2V,
CE
L
V
> VCC – 0.2V or
IN
V
< 0.2V, Active
IN
Port Outputs, f = f
OUT
= 0 mA
[7]
[7]
MAX
7C144-15
7C145-15
7C144-25
7C145-25
Unit
Min Max Min Max
−10 +10 −10 +10 μA
CC
−10 +10 −10 +10 μA
Commercial 220 180 mA
Industrial 190
Commercial 60 40 mA
Industrial 50
Commercial 130 110 mA
Industrial 120
Commercial 15 15 mA
Industrial 30
Commercial 125 100 mA
Industrial 115
Notes
5. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
6. Pulse width < 20 ns.
= 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby
7. f
MAX
I
.
SB3
Document #: 38-06034 Rev. *D Page 4 of 21
[+] Feedback
CY7C145, CY7C144
Electrical Characteristics Over the Operating Range (continued)
Note:
8. Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
I
I
I
OH
OL
IH
IL
IX
OZ
CC
SB1
SB2
SB3
SB4
Output HIGH Voltage VCC = Min., IOH = −4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V
Input HIGH Voltage 2.2 2.2 V
Input LOW Voltage 0.8 0.8 V
Input Leakage Current GND < VI < V
CC
Output Leakage Current Outputs Disabled, GND < VO < V
Operating Current VCC = Max., I
Outputs Disabled
Standby Current
(Both Ports TTL Levels)
Standby Current
(One Port TTL Level)
Standby Current
(Both Ports CMOS Levels)
Standby Current
(One Port CMOS Level)
CEL and CER > VIH,
f = f
CEL or CER > VIH,
f = f
MAX
MAX
[7]
[7]
Both Ports
and CER > VCC – 0.2V,
CE
V
> VCC – 0.2V
IN
or V
< 0.2V, f = 0
IN
One Port
CE
or CER > VCC – 0.2V,
L
> VCC – 0.2V or
V
IN
V
< 0.2V, Active
IN
Port Outputs, f = f
OUT
= 0 mA
[7]
[7]
MAX
7C144-35
7C145-35
7C144-55
7C145-55
Unit
Min Max Min Max
−10 +10 −10 +10 μA
CC
−10 +10 −10 +10 μA
Commercial 160 160 mA
Industrial 180 180
Commercial 30 30 mA
Industrial 40 40
Commercial 100 100 mA
Industrial 110 110
Commercial 15 15 mA
Industrial 30 30
Commercial 90 90 mA
Industrial 100 100
Capacitance
Parameter
C
IN
C
OUT
Document #: 38-06034 Rev. *D Page 5 of 21
[8]
Description Test Conditions Max. Unit
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 5.0V
Output Capacitance 15 pF
CC
10 pF
[+] Feedback
CY7C145, CY7C144
Figure 4. AC Test Loads and Waveforms
3.0V
GND
90%
90%
10%
≤ 3ns
≤ 3 ns
10%
ALL INPUT PULSES
(a) Normal Load (Load1)
5V
OUTPUT
C= 30
pF
V
TH
= 1.4V
OUTPUT
C = 30pF
(b) Th évenin Equivalent (Load 1)
(c) Three-State Delay (Load 3)
C= 30pF
OUTPUT
Load (Load 2)
5V
OUTPUT
C= 5pF
R1 = 893Ω
R2 = 347Ω
R
TH
= 250Ω
R1 = 893Ω
R = 347Ω
Switching Characteristics Over the Operating Range
Parameter Description
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
[10, 11,12]
t
LZOE
[10, 11,12]
t
HZOE
[10, 11,12]
t
LZCE
[10, 11,12]
t
HZCE
[12]
t
PU
[12]
t
PD
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
Notes
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
and 30-pF load capacitance.
OI/IOH
10. At any given temperature and voltage condition for any given device, t
11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested.
Document #: 38-06034 Rev. *D Page 6 of 21
Read Cycle Time 15 25 35 55 ns
Address to Data Valid 15 25 35 55 ns
Output Hold From Address
Change
CE LOW to Data Valid 15 25 35 55 ns
OE LOW to Data Valid 10 15 20 25 ns
OE Low to Low Z 3 3 3 3 ns
OE HIGH to High Z 10 15 20 25 ns
CE LOW to Low Z 3 3 3 3 ns
CE HIGH to High Z 10 15 20 25 ns
CE LOW to Power-Up 0 0 0 0 ns
CE HIGH to Power-Down 15 25 35 55 ns
Write Cycle Time 15 25 35 55 ns
CE LOW to Write End 12 20 30 45 ns
Address Set-Up to Write End 12 20 30 45 ns
Address Hold From Write End 2 2 2 2 ns
Address Set-Up to Write Start 0 0 0 0 ns
Write Pulse Width 12 20 25 40 ns
[9]
7C144-15
7C145-15
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Unit
Min Max Min Max Min Max Min Max
3333ns
HZCE
is less than t
LZCE
and t
is less than t
HZOE
LZOE
.
[+] Feedback
CY7C145, CY7C144
Switching Characteristics Over the Operating Range
7C144-15
Parameter Description
t
SD
t
HD
[11,12]
t
HZWE
[11,12]
t
LZWE
[13]
t
WDD
[13]
t
DDD
BUSY TIMING
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD
INTERRUPT TIMING
t
INS
t
INR
Data Set-Up to Write End 10 15 15 25 ns
Data Hold From Write End 0 0 0 0 ns
R/W LOW to High Z 10 15 20 25 ns
R/W HIGH to Low Z 3 3 3 3 ns
Write Pulse to Data Delay 30 50 60 70 ns
Write Data Valid to Read Data
Valid
[14]
BUSY LOW from Address
Match
BUSY HIGH from Address
Mismatch
BUSY LOW from CE LOW 15202030ns
BUSY HIGH from CE HIGH 15 20 20 30 ns
Port Set-Up for Priority 5 5 5 5 ns
R/W LOW after BUSY LOW 0 0 0 0 ns
R/W HIGH after BUSY HIGH 13 20 30 30 ns
BUSY HIGH to Data Valid 15 25 35 55 ns
[14]
INT Set Time 15 25 25 35 ns
INT Reset Time 15 25 25 35 ns
SEMAPHORE TIMING
t
SOP
t
SWRD
t
SPS
SEM Flag Update Pulse (OE
or SEM
)
SEM Flag Write to Read Time 5 5 5 5 ns
SEM Flag Contention
Window
7C145-15
Min Max Min Max Min Max Min Max
25 30 35 40 ns
15 20 20 30 ns
15 20 20 30 ns
10 10 15 20 ns
5555ns
[9]
(continued)
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Unit
Notes
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
Document #: 38-06034 Rev. *D Page 7 of 21
[+] Feedback
CY7C145, CY7C144
Switching Waveforms
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
DATA OUT
SEM
or CE
OE
t
LZCE
t
PU
I
CC
I
SB
t
PD
VALID
t
DDD
t
WDD
MATCH
MATCH
R/W
R
DATAIN
R
DATA
OUTL
t
WC
ADDRESS
R
t
PWE
VALID
t
SD
t
HD
ADDRESS
L
Figure 5. Read Cycle No. 1 (Either Port Address Access)
[15, 16]
Figure 6. Read Cycle No. 2 (Either Port CE/OE Access)
Figure 7. Read Timing with Port-to-Port Delay (M/S=L)
[15, 17, 18]
[19, 20]
Notes
is HIGH for read cycle.
15. R/W
16. Device is continuously selected CE
17. Address valid prior to or coincident with CE
= L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.
18. CE
L
19. BUSY
20. CE
= HIGH for the writing port.
= CER = LOW.
L
Document #: 38-06034 Rev. *D Page 8 of 21
= LOW and OE = LOW. This waveform cannot be used for semaphore reads.
transition LOW.
[+] Feedback
CY7C145, CY7C144
Switching Waveforms (continued)
t
AW
t
WC
DATA VALID
HIGH IMPEDANCE
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HA
t
HZOE
t
LZOE
SEM OR CE
R/W
ADDRESS
OE
DATA OUT
DATA IN
t
AW
t
WC
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HZWE
t
HA
HIGH IMPEDANCE
SEM
OR CE
R/W
ADDRESS
DATA
OUT
DATA IN
t
LZWE
DATAVALID
Figure 8. Write Cycle No. 1: OE
Three-State Data I/Os (Either Port)
[21, 22, 23]
Figure 9. Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)
[21, 23, 24]
Notes
21. The internal write time of the memory is defined by the overlap of CE
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
22. If OE
be placed on the bus for the required t
pulse can be as short as the specified t
23. R/W
24. Data I/O pins enter high impedance when OE
is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
must be HIGH during all address transitions.
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write
SD
.
PWE
is held LOW during write.
or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal
PWE
or (t
+ tSD) to allow the I/O drivers to turn off and data to
HZWE
Document #: 38-06034 Rev. *D Page 9 of 21
[+] Feedback
CY7C145, CY7C144
Switching Waveforms (continued)
t
SOP
t
AA
SEM
R/W
OE
I/O
0
VALID ADDRESS VALID ADDRESS
t
HD
DATAINVALID
DATA
OUT
VALID
t
OHA
A0−A
2
t
AW
t
HA
t
ACE
t
SOP
t
SCE
t
SD
t
SA
t
PWE
t
SWRD
t
DOE
WRITE CYCLE READ CYCLE
MATCH
t
SPS
A0L−A
2L
MATCH
R/W
L
SEM
L
A0R−A
2R
R/W
R
SEM
R
Figure 10. Semaphore Read After Write Timing, Either Side
[25]
Notes
25. CE
26. I/O
27. Semaphores are reset (available to both ports) at cycle start.
28. If t
Document #: 38-06034 Rev. *D Page 10 of 21
= HIGH for the duration of the above timing (both write and read cycle).
= I/O0L = LOW (request semaphore); CER = CEL = HIGH
0R
is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
SPS
Figure 11. Semaphore Contention
[26, 27, 28]
[+] Feedback
CY7C145, CY7C144
Switching Waveforms (continued)
VALID
t
DDD
t
WDD
MATCH
MATCH
R/W
R
DATAIN
R
DATA
OUTL
t
WC
ADDRESS
R
t
PWE
VALID
t
SD
t
HD
ADDRESS
L
t
PS
t
BLA
t
BHA
t
BDD
BUSY
L
t
PWE
R/W
BUSY
t
WB
t
WH
Figure 12. Read with BUSY
Figure 13. Write Timing with Busy Input (M/S=LOW)
(M/S=HIGH)
[20]
Document #: 38-06034 Rev. *D Page 11 of 21
[+] Feedback
CY7C145, CY7C144
Switching Waveforms (continued)
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS
L,R
BUSY
R
CE
L
CE
R
BUSY
L
CE
R
CE
L
ADDRESS
L,R
CEL Valid First:
CER Valid First:
ADDRESS MATCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMATCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MATCH ADDRESS MISMATCH
t
PS
ADDRESS
L
BUSY
L
tRCor t
WC
t
BLA
t
BHA
ADDRESS
R
Left Address Valid First:
Right Address Valid First:
Figure 14. Busy Timing Diagram No. 1 (CE
Arbitration)
[29]
Figure 15. Busy Timing Diagram No. 2 (Address Arbitration)
Note:
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
29. If t
PS
Document #: 38-06034 Rev. *D Page 12 of 21
[29]
[+] Feedback
CY7C145, CY7C144
Switching Waveforms (continued)
WRITE 1FFF
t
WC
t
HA
Left Side Sets INTR:
ADDRESS
L
R/W
L
CE
L
INT
R
t
INS
[30]
[31]
Right Side Clears INTR:
READ 1FFF
t
RC
t
INR
WRITE 1FFE
t
WC
Right Side Sets INTL:
Left Side Clears INTL:
READ 1FFE
t
INR
t
RC
ADDRESS
R
CE
L
R/W
L
INT
L
OE
L
ADDRESS
R
R/W
R
CE
R
INT
L
ADDRESS
R
CE
R
R/W
R
INT
R
OE
R
t
HA
t
INS
[31]
[30]
[31]
[31]
Figure 16. Interrupt Timing Diagrams
Notes
depends on which enable pin (CEL or R/WL) is deasserted first.
30. t
HA
31. t
or t
INS
Document #: 38-06034 Rev. *D Page 13 of 21
depends on which enable pin (CEL or R/WL) is asserted last.
INR
[+] Feedback
CY7C145, CY7C144
Architecture
The CY7C144/5 consists of a an array of 8K words of 8/9 bits
each of dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes or reads to the same location, a BUSY pin
is provided on each port. Two interrupt (INT
for port-to-port communication. Two semaphore (SEM
) pins can be used
) control
pins are used for allocating shared resources. With the M/S
pin, the CY7C144/5 can function as a Master (BUSY pins are
outputs) or as a slave (BUSY
has an automatic power down feature controlled by CE
port is provided with its own output enable control (OE
pins are inputs). The CY7C144/5
. Each
), which
allows data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W
controlled by either the OE
R/W
to the device t
the falling edge of R/W
operations are summarized in Table 3.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must be met before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port t
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
OE
access a semaphore flag, then the SEM
instead of the CE
Interrupts
The interrupt flag (INT) permits communications between
ports.When the left port writes to location 1FFF, the right port’s
interrupt flag (INTR) is set. This flag is cleared when the right
port reads that same location. Setting the left port’s interrupt
flag (INT
location 1FFE. This flag is cleared when the left port reads
location 1FFE. The message at 1FFF or 1FFE is user-defined.
See Tab le 4 for input requirements for INT
push-pull outputs and do not require pull-up resistors to
operate.
Busy
The CY7C144/5 provides on-chip arbitration to alleviate simultaneous memory location access (contention). If both ports’
CE
each other the Busy logic determines which port has access.
If t
location, but it is not guaranteed which one. BUSY
asserted t
LOW. BUSY
outputs and do not require pull-up resistors to operate.
to guarantee a valid write. A write operation is
pin (see Figure 8 on page 9) or the
pin (see Write Cycle No. 2 waveform). Data can be written
after the OE is deasserted or t
HZOE
after the data is presented on the other port.
DDD
are asserted. If the user of the CY7C144/5 wishes to
. Required inputs for non-contention
after CE or t
ACE
HZWE
DOE
after
after
pin must be asserted
pin.
) is accomplished when the right port writes to
L
. INTR and INTL are
s are asserted and an address match occurs within tPS of
is violated, one port will definitely gain permission to the
PS
after an address match or t
BLA
and BUSYR in master mode are push-pull
L
after CE is taken
BLC
will be
Master/Slave
An M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This enables the device to interface to a master device
with no external components.Writing of slave devices must be
delayed until after the BUSY
input has settled. Otherwise, the
slave chip may begin a write cycle during a contention
situation.When presented a HIGH input, the M/S
device to be used as a master and therefore the BUSY
an output. BUSY
can then be used to send the arbitration
pin allows the
line is
outcome to a slave.
Semaphore Operation
The CY7C144/5 provides eight semaphore latches which are
separate from the dual-port memory locations. Semaphores
are used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is
in use. For example, if the left port wants to request a given
resource, it sets a latch by writing a 0 to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM
deasserted for t
The semaphore value is available t
edge of the semaphore write. If the left port was successful
before attempting to read the semaphore.
SOP
SWRD
(reads a 0), it assumes control over the shared resource,
otherwise (reads a 1) it assumes the right port has control and
continues to poll the semaphore.When the right side has relinquished control of the semaphore (by writing a 1), the left side
will succeed in gaining control of the semaphore. If the left side
no longer requires the semaphore, a 1 is written to cancel its
request.
Semaphores are accessed by asserting SEM
pin functions as a chip enable for the semaphore latches (CE
must remain HIGH during SEM LOW). A
semaphore address. OE
and R/W are used in the same
manner as a normal memory access.When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
written to the left port of an unused semaphore, a 1 appears
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing 0
(the left port in this case). If the left port now relinquishes
control by writing a 1 to the semaphore, the semaphore will be
set to 1 for both sides. However, if the right port had requested
the semaphore (written a 0) while the left port had control, the
right port would immediately own the semaphore as soon as
the left port released it. Table 5 shows sample semaphore
operations.
When reading a semaphore, all eight/nine data lines output the
semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within t
definitely obtained by one side or the other, but there is no
of each other, the semaphore is
SPS
guarantee which side controls the semaphore.
Initialization of the semaphore is not automatic and must be
reset during initialization program at power up. All
Semaphores on both sides should have a one written into
them at initialization from both sides to assure that they are
free when needed.
or OE must be
+ t
after the rising
DOE
LOW. The SEM
represents the
0–2
is used. If a 0 is
0
Document #: 38-06034 Rev. *D Page 14 of 21
[+] Feedback
CY7C145, CY7C144
Table 3. Non-Contending Read/Write
Inputs Outputs
CE R/W OE SEM I/O
0−7/8
H X X H High Z Power-Down
H H L L Data Out Read Data in Semaphore
X X H X High Z I/O Lines Disabled
H X L Data In Write to Semaphore
LHL HData Out Read
LLX HData In Write
L X X L Illegal Condition
Operation
Table 4. Interrupt Operation Example (assumes BUSY
= BUSYR = HIGH)
L
Function Left Port Right Port
R/W CE OE A
0−12
INT R/W CE OE A
0−12
Set Left INT X X X X L L L X 1FFE X
Reset Left INT
Set Right INT
Reset Right INT
XLL1FFEH XL L X X
LLX1FFFX XXX X L
XXXXXXLL1FFFH
Table 5. Semaphore Operation Example
Function I/O
Left I/O
0-7/8
Right Status
0-7/8
No action 1 1 Semaphore free
Left port writes semaphore 0 1 Left port obtains semaphore
Right port writes 0 to semaphore 0 1 Right side is denied access
Left port writes 1 to semaphore 1 0 Right port is granted access to semaphore
Left port writes 0 to semaphore 1 0 No change. Left port is denied access
Right port writes 1 to semaphore 0 1 Left port obtains semaphore
Left port writes 1 to semaphore 1 1 No port accessing semaphore address
Right port writes 0 to semaphore 1 0 Right port obtains semaphore
Right port writes 1 to semaphore 1 1 No port accessing semaphore
Left port writes 0 to semaphore 0 1 Left port obtains semaphore
Left port writes 1 to semaphore 1 1 No port accessing semaphore
INT
Document #: 38-06034 Rev. *D Page 15 of 21
[+] Feedback
CY7C145, CY7C144
Figure 17. Typical DC and AC Characteristics
1.4
1.0
0.4
4.0 4.5 5.0 5.5 6.0
−55 25 125
1.2
1.0
120
80
0 1.0 2.0 3.0 4.0
OUTPUT SOURCE CURRENT (mA)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.0
0.8
0.8
0.6
0.6
NORMALIZED I
CC
, I
SB
V
CC
= 5.0V
V
IN
= 5.0V
0
I
CC
I
CC
1.6
1.4
1.2
1.0
0.8
−55 125
NORMALIZED t
AA
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
1.4
1.3
1.2
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED t
AA
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
80
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
TA = 25°C
0.6
0.8
1.25
1.0
0.75
10
NORMALIZED I
CC
0.50
NORMALIZED I
CC
vs. CYCLE TIME
CYCLE FREQUENCY (MHz)
NORMALIZED t
PC
25.0
30.0
20.0
10.0
5.0
0 200 400 600 800
DELTA t
AA
(ns)
0
15.0
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
1000
28
0.2
0.6
1.2
I
SB3
NORMALIZED I
CC
, I
SB
0.2
0.4
I
SB3
25
1.1
5.0
V
CC
= 5.0V
T
A
= 25°C
40
160
200
5.0
40
66
1.00
0.25
0 1.0 2.0 3.0 5.0
0.0
4.0
0.50
0.75
V
CC
= 5.0V
V
CC
= 5.0V
T
A
= 25°C
V
CC
= 4.5V
T
A
= 25°C
V
IN
= 5.0V
T
A
= 25°C
V
CC
= 5.0V
Document #: 38-06034 Rev. *D Page 16 of 21
[+] Feedback
CY7C145, CY7C144
Ordering Information
8K x8 Dual-Port SRAM
Speed
(ns) Ordering Code
15 CY7C144-15AC A65 64-Pin Thin Quad Flat Pack Commercial
CY7C144-15AXC A65 64-Pin Pb-Free Thin Quad Flat Pack
CY7C144-15JC J81 68-Pin Plastic Leaded Chip Carrier
CY7C144-15JXC J81 68-Pin Pb-Free Plastic Leaded Chip Carrier
CY7C144-15AI A65 64-Pin Thin Quad Flat Pack Industrial
CY7C144-15JXI J81 68-Pin Pb-Free Plastic Leaded Chip Carrier
CY7C144-15AXI A65 64-Pin Pb-Free Thin Quad Flat Pack
25 CY7C144-25AC A65 64-Pin Thin Quad Flat Pack Commercial
CY7C144-25AXC A65 64-Pin Pb-Free Thin Quad Flat Pack
CY7C144-25JC J81 68-Pin Plastic Leaded Chip Carrier
CY7C144-25AI A65 64-Pin Thin Quad Flat Pack Industrial
CY7C144-25JI J81 68-Pin Plastic Leaded Chip Carrier
35 CY7C144-35AC A65 64-Pin Thin Quad Flat Pack Commercial
CY7C144-35JC J81 68-Pin Plastic Leaded Chip Carrier
CY7C144-35AI A65 64-Pin Thin Quad Flat Pack Industrial
CY7C144-35JI J81 68-Pin Plastic Leaded Chip Carrier
55 CY7C144-55AC A65 64-Pin Thin Quad Flat Pack Commercial
CY7C144-55AXC A65 64-Pin Pb-Free Thin Quad Flat Pack
CY7C144-55JC J81 68-Pin Plastic Leaded Chip Carrier
CY7C144-55JXC J81 68-Pin Pb-Free Plastic Leaded Chip Carrier
CY7C144-55AI A65 64-Pin Thin Quad Flat Pack Industrial
CY7C144-55JI J81 68-Pin Plastic Leaded Chip Carrier
Package
Name Package Type
Operating
Range
Document #: 38-06034 Rev. *D Page 17 of 21
[+] Feedback
CY7C145, CY7C144
8K x9 Dual-Port SRAM
Speed
(ns) Ordering Code
15 CY7C145-15AC A80 80-Pin Thin Quad Flat Pack Commercial
CY7C145-15AXC A80 80-Pin Pb-Free Thin Quad Flat Pack
CY7C145-15JC J81 68-Pin Plastic Leaded Chip Carrier
25 CY7C145-25AC A80 80-Pin Thin Quad Flat Pack Commercial
CY7C145-25JC J81 68-Pin Plastic Leaded Chip Carrier
CY7C145-25AI A80 80-Pin Thin Quad Flat Pack Industrial
CY7C145-25JI J81 68-Pin Plastic Leaded Chip Carrier
35 CY7C145-35AC A80 80-Pin Thin Quad Flat Pack Commercial
CY7C145-35JC J81 68-Pin Plastic Leaded Chip Carrier
CY7C145-35JXC J81 68-Pin Pb-Free Plastic Leaded Chip Carrier
CY7C145-35AI A80 80-Pin Thin Quad Flat Pack Industrial
CY7C145-35JI J81 68-Pin Plastic Leaded Chip Carrier
55 CY7C145-55AC A80 80-Pin Thin Quad Flat Pack Commercial
CY7C145-55JC J81 68-Pin Plastic Leaded Chip Carrier
CY7C145-55AI A80 80-Pin Thin Quad Flat Pack Industrial
CY7C145-55JI J81 68-Pin Plastic Leaded Chip Carrier
Package
Name Package Type
Operating
Range
Document #: 38-06034 Rev. *D Page 18 of 21
[+] Feedback
CY7C145, CY7C144
Package Diagrams
51-85046-*C
Figure 18. 64-Pin Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65 (51-85046)
Document #: 38-06034 Rev. *D Page 19 of 21
[+] Feedback
CY7C145, CY7C144
Figure 19. 80-Pin Thin Plastic Quad Flat Pack A80 (51-85065)
51-85065-*B
51-85005-*A
Figure 20. 68-Pin Plastic Leaded Chip Carrier J81 (51-85005)
Document #: 38-06034 Rev. *D Page 20 of 21
[+] Feedback
CY7C145, CY7C144
Document History Page
Document Title: CY7C145, CY7C144 8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Document Number: 38-06034
Rev. ECN No.
Orig. of
Change
Submission
Date
Description of Change
** 110175 SZV 09/29/01 Change from Spec number: 38-00163 to 38-06034
*A 122285 RBI 12/27/02 Power up requirements added to Maximum Ratings Information
*B 236752 YDT See ECN Removed cross information from features section, added CY7C144-15AI to
ordering information section
*C 393320 YIM See ECN Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C144-15AXC, CY7C144-15JXC, CY7C144-15AXI, CY7C144-25AXC,
CY7C144-55AXC, CY7C144-55JXC, CY7C145-15AXC, CY7C145-35JXC
*D 2623658 VKN/PYRS 12/17/08 Added CY7C144-15JXI in the Ordering information table
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
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Document #: 38-06034 Rev. *D Revised December 10, 2008 Page 21 of 21
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