Cypress Semiconductor CY7C1422BV18, CY7C1423BV18, CY7C1429BV18, CY7C1424BV18 Specification Sheet

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36-Mbit DDR-II SIO SRAM 2-Word

Burst Architecture

CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Features

Functional Description

■ 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

■ 300 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ DDR-II operates with 1.5 cycle read latency when the DLL is

enabled

■ Operates similar to a DDR-I device with 1 cycle read latency in

DLL off mode

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

)

Configurations

The CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO (DDR-II SIO) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K

. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K

if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1422BV18, two 9-bit words in the case of CY7C1429BV18, two 18-bit words in the case of CY7C1423BV18, and two 36-bit words in the case of CY7C1424BV18 that burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ

, eliminating the need to capture data separately from each individual DDR-II SIO SRAM in the system design. Output data clocks (C/C

) enable maximum

system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by

the K or K registers controlled by the C or C

input clocks. All data outputs pass through output

(or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

CY7C1422BV18 – 4M x 8 CY7C1429BV18 – 4M x 9 CY7C1423BV18 – 2M x 18 CY7C1424BV18 – 1M x 36

Selection Guide

Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz Maximum Operating Current x8 825 775 700 600 500 mA

x9 845 775 700 600 500 x18 880 815 740 600 500 x36 980 890 800 665 560

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 001-07035 Rev. *D Revised June 16, 2008

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Logic Block Diagram (CY7C1422BV18)

2M x 8 Array

CLK

(20:0)

Gen.

Control

Logic

Address Register

[7:0]

Read Add. Decode

Read Data Reg.

[7:0]

Reg.

NWS

[1:0]

REF

Write Add. Decode

Write Data Reg

R/W

LD R/W

DOFF

2M x 8 Array

Write Data Reg

Control

Logic

2M x 9 Array

CLK

(20:0)

Gen.

Control

Logic

Address Register

[8:0]

Read Add. Decode

Read Data Reg.

[8:0]

Reg.

BWS

[0]

REF

Write Add. Decode

Write Data Reg

R/W

LD R/W

DOFF

2M x 9 Array

Write Data Reg

Control

Logic

Logic Block Diagram (CY7C1429BV18)

Document #: 001-07035 Rev. *D Page 2 of 30

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Logic Block Diagram (CY7C1423BV18)

1M x 18 Array

CLK

(19:0)

Gen.

Control

Logic

Address Register

[17:0]

Read Add. Decode

Read Data Reg.

[17:0]

Reg.

BWS

[1:0]

REF

Write Add. Decode

Write Data Reg

R/W

LD R/W

DOFF

1M x 18 Array

Write Data Reg

Control

Logic

512K x 36 Array

CLK

(18:0)

Gen.

Control

Logic

Address Register

[35:0]

Read Add. Decode

Read Data Reg.

[35:0]

Reg.

BWS

[3:0]

REF

Write Add. Decode

Write Data Reg

R/W

LD R/W

DOFF

512K x 36 Array

Write Data Reg

Control

Logic

Logic Block Diagram (CY7C1424BV18)

Document #: 001-07035 Rev. *D Page 3 of 30

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Pin Configuration

Note

1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

The pin configuration for CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 follow.

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1422BV18 (4M x 8)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/72M A R/W NWS

B NC NC NC A NC/288M K NWS C NC NC NC V D NC D4 NC V E NC NC Q4 V F NC NC NC V G NC D5 Q5 V H DOFF V

REF

DDQ

J NC NC NC V K NC NC NC V L NC Q6 D6 V M NC NC NC V N NC D7 NC V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AAAVSSNC NC D3

AAAVSSNC NC NC

P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C AAATMSTDI

K NC/144M LD AACQ

ANCNCQ3

DDQ

[1]

NC NC NC NC D2 Q2 NC NC NC NC NC NC

DDQ

REF

NC Q1 D1 NC NC NC NC NC Q0 NC NC D0

CY7C1429BV18 (4M x 9)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/72M A R/W NC K NC/144M LD AACQ B NC NC NC A NC/288M K BWS C NC NC NC V D NC D5 NC V E NC NC Q5 V F NC NC NC V G NC D6 Q6 V H DOFF V

REF

DDQ

J NC NC NC V K NC NC NC V L NC Q7 D7 V M NC NC NC V N NC D8 NC V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AAAVSSNC NC D4

AAAVSSNC NC NC

ANCNCQ4

V V V V V V V

DDQ DDQ DDQ DDQ DDQ DDQ DDQ

NC NC NC NC D3 Q3 NC NC NC NC NC NC

DDQ

REF

NC Q2 D2 NC NC NC NC NC Q1 NC NC D1

P NC NC Q8 A A C A A NC D0 Q0 R TDO TCK A A A C AAATMSTDI

Document #: 001-07035 Rev. *D Page 4 of 30

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Pin Configuration (continued)

The pin configuration for CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 follow.

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1423BV18 (2M x 18)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/144M A R/W BWS

B NC Q9 D9 A NC K BWS C NC NC D10 V D NC D11 Q10 V E NC NC Q11 V F NC Q12 D12 V G NC D13 Q13 V H DOFF V

REF

DDQ

J NC NC D14 V K NC NC Q14 V L NC Q15 D15 V M NC NC D16 V N NC D17 Q16 V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AAAVSSNC Q7 D8

AAAVSSNC NC D1

P NC NC Q17 A A C A A NC D0 Q0 R TDO TCK A A A C AAATMSTDI

K NC/288M LD A NC/72M CQ

ANCNCQ8

DDQ

[1]

NC NC D7 NC D6 Q6 NC NC Q5 NC NC D5

DDQ

REF

NC Q4 D4 NC D3 Q3 NC NC Q2 NC Q1 D2

CY7C1424BV18 (1M x 36)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/288M NC/72M R/W BWS B Q27 Q18 D18 A BWS C D27 Q28 D19 V D D28 D20 Q19 V E Q29 D29 Q20 V F Q30 Q21 D21 V G D30 D22 Q22 V H DOFF V

REF

DDQ

J D31 Q31 D23 V K Q32 D32 Q23 V L Q33 Q24 D24 V M D33 Q34 D25 V N D34 D26 Q25 V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AAAVSSD16 Q7 D8

AAAVSSQ10 D9 D1

2 3

K BWS

LD A NC/144M CQ

KBWS0AD17Q17Q8

V V V V V V V

DDQ DDQ DDQ DDQ DDQ DDQ DDQ

Q16 D15 D7 Q15 D6 Q6 D14 Q14 Q5 Q13 D13 D5

DDQ

REF

D12 Q4 D4 Q12 D3 Q3 D11 Q11 Q2 D10 Q1 D2

P Q35 D35 Q26 A A C A A Q9 D0 Q0 R TDO TCK A A A C AAATMSTDI

Document #: 001-07035 Rev. *D Page 5 of 30

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Pin Definitions

Pin Name IO Pin Description

[x:0]

LD Input-

NWS0, NWS

BWS0, BWS

BWS2, BWS

A Input-

[x:0]

R/W Input-

C Input Clock Positive Input Clock for Output Data. C is used in conjunction with C

Input-

Synchronous

Input-

Synchronous

Outputs-

Synchronous

Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. CY7C1422BV18 - D CY7C1429BV18 - D CY7C1423BV18 - D CY7C1424BV18 - D

[7:0] [8:0] [17:0] [35:0]

Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period of bus activity).

Nibble Write Select 0, 1 − Active LOW (CY7C1422BV18 Only). Sampled on the rising edge of the K and K

clocks during Write operations. Used to select which nibble is written into the device during the current portion of the Write operations.Nibbles not written remain unaltered. NWS0 controls D All Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

and NWS1 controls D

[3:0]

[7:4]

ignores the corresponding nibble of data and it is not written into the device. Byte Write Select 0, 1, 2 and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during

write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1429BV18 − BWS CY7C1423BV18 − BWS CY7C1424BV18 − BWS D

[35:27].

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

controls D

[8:0]

, BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[17:9]

,BWS2 controls D

[17:9]

ignores the corresponding byte of data and it is not written into the device. Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These

address inputs are multiplexed for both read and write operations. Internally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1422BV18, 4M x 9 (2 arrays each of 2M x 9) for CY7C1429BV18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1423BV18 and 1M x 36 (2 arrays each of 512K x 36) for CY7C1424BV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1422BV18 and CY7C1429BV18, 20 address inputs for CY7C1423BV18 and 19 address inputs for CY7C1424BV18. These inputs are ignored when the appropriate port is deselected.

Data Output Signals. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the C and C clock mode. When the read port is deselected, Q CY7C1422BV18 − Q CY7C1429BV18 − Q CY7C1423BV18 − Q CY7C1424BV18 − Q

[7:0] [8:0] [17:0] [35:0]

clocks during read operations, or K and K when in single

are automatically tri-stated.

[x:0]

Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read when R/W

is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times

around the edge of K.

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 9 for further details.

and BWS3 controls

[26:18]

to clock out the read data from

Input Clock Negative Input Clock for Output data. C is used in conjunction with C to clock out the read data from

the device. C and C to the controller. See Application Example on page 9 for further details.

K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q edge of K.

Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and

to drive out data through Q

Document #: 001-07035 Rev. *D Page 6 of 30

can be used together to deskew the flight times of various devices on the board back

when in single clock mode. All accesses are initiated on the rising

[x:0]

when in single clock mode.

[x:0]

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Pin Definitions (continued)

Pin Name IO Pin Description

CQ Echo Clock CQ Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock

for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks is shown in the Switching Characteristics on page 23.

ZQ Input Output Impedance Matching Inpu t. This input is used to tune the device outputs to the system data bus

DOFF

TDO Output TDO for JTAG. TCK Input TCK Pin for JTAG. TDI Input TDI Pin for JTAG. TMS Input TMS Pin for JTAG. NC N/A Not Connected to the Die. Can be tied to any voltage level. NC/72M N/A Not Connected to the Die. Can be tied to any voltage level. NC/144M N/A Not Connected to the Die. Can be tied to any voltage level. NC/288M N/A Not Connected to the Die. Can be tied to any voltage level. V

REF

DDQ

Echo Clock CQ Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock

Input DLL Turn Off − Active LOW . Connecting this pin to ground turns off the DLL inside the device. The timing

Input-

Reference

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

for output data (C for the echo clocks is shown in the Switching Characteristics on page 23.

impedance. CQ, CQ, and Q between ZQ and ground. Alternatively, this pin can be connected directly to V minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

in the DLL turned off operation differs from those listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10-Kohm or less pull up resistor. The device behaves in DDR-I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with DDR-I timing.

Reference Voltage In put . Static input used to set the reference level for HSTL inputs, Outputs, and AC measurement points.

) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings

output impedance are set to 0.2 x RQ, where RQ is a resistor connected

[x:0]

, which enables the

DDQ

Document #: 001-07035 Rev. *D Page 7 of 30

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Functional Overview

The CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 are synchronous pipelined Burst SRAMs equipped with a DDR-II Seperate IO interface, which operates with a read latency of one and half cycles when DOFF HIGH. When DOFF

pin is set LOW or connected to VSS the device behaves in DDR-I mode with a read latency of one clock cycle.

Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K

) and all output timing is referenced to the rising edge of the output clocks (C/C when in single clock mode).

All synchronous data inputs (D controlled by the rising edge of the input clocks (K and K synchronous data outputs (Q controlled by the rising edge of the output clocks (C/C

) pass through input registers

[x:0]

) pass through output registers

[x:0]

when in single-clock mode). All synchronous control (R/W

input registers controlled by the rising edge of the input clock (K).

, LD, BWS

) inputs pass through

[0:X]

CY7C1423BV18 is described in the following sections. The same basic descriptions apply to CY7C1422BV18, CY7C1429BV18, and CY7C1424BV18.

Read Operations

The CY7C1423BV18 is organized internally as two arrays of 1M x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in th e read address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the Q

using C as the output timing reference. On the subse-

[17:0]

quent rising edge of C, the next 18-bit data word is driven onto the Q edge of the output clock (C or C

. The requested data is valid 0.45 ns from the rising

[17:0]

, or K and K when in single clock mode, for 200 MHz and 250 MHz device). Read accesses can be initiated on every rising edge of the positive input clock (K). This pipelines the data flow such that data is transferred out of the device on every rising edge of the output clocks, C/C when in single clock mode).

The CY7C1423BV18 first completes the pending read transactions, when read access is deselected. Synchronous internal circuitry automatically tri-states the output following the next rising edge of the positive output clock (C).

Write Operations

Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the write address register. On the following K clock rise the data presented to D provided BWS rising edge of the negative input clock (K presented to D provided BWS

is latched and stored into the 18-bit write data register,

[17:0]

are both asserted active. On the subsequent

[1:0]

is also stored into the write data register,

[17:0]

are both asserted active. The 36 bits of data

[1:0]

) the information

pin is tied

, or K/K

). All

, or K/K

(or K/K

are then written into the memory array at the specified l ocation. Write accesses can be initiated on every rising edge of the positive input clock (K). This pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K

When Write access is deselected, the device ignores all inputs after the pending write operations are completed.

Byte Write Operations

Byte write operations are supported by the CY7C1423BV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS

, which are sampled with each set of 18-bit data words.

Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read/modify/write operations to a byte write operation.

Single Clock Mode

The CY7C1423BV18 can be used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K

and C/C clocks. All timing parameters remain the same

in this mode. T o use this mode of operation, tie C and C

HIGH at power on. This function is a strap option and not alterable during device operation.

DDR Operation

The CY7C1423BV18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation.

If a read occurs after a write cycle, address and data for the write are stored in registers. The write information must be stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a posted write.

Depth Expansion

Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω output impedance is adjusted every 1024 cycles at power up to account for drifts in supply voltage and temperature.

to enable the SRAM to adjust its output

, with V

=1.5V. The

DDQ

Document #: 001-07035 Rev. *D Page 8 of 30

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Echo Clocks

Echo clocks are provided on the DDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C

. These are free-running clocks and are synchronized to the output clock of the DDR-II. In the single clock mode, CQ is generated with respect to K and CQ with respect to K

. The timing for the echo clocks is shown in

is generated

Switching Characteristics on page 23.

Application Example

Figure 1 shows four DDR-II SIO used in an application.

Figure 1. Application Example

DLL

These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K minimum of 30 ns. However, it is not necessary to reset the DLL to lock it to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in DDR-I mode (with one cycle latency and a longer access time). For information refer to the application note AN5062, DLL Considerations in

QDRII/DDRII/QDRII+/DDRII+.

for a

BUS

MASTER

(CPU

ASIC)

DATA IN

DATA OUT

Address

LD#

R/W#

BWS#

SRAM 1 Input CQ

SRAM 1 Input CQ#

SRAM 4 Input CQ

SRAM 4 Input CQ#

Source K

Source K#

Delayed K

Delayed K#

SRAM 1

R=50

Ohms

LD#R/W

R/W

Vt = V

S W

REF

CC#

CQ#

R = 250Ohms

LD#R/W

SRAM 4

CC#K

CQ#

R = 250Ohms

Document #: 001-07035 Rev. *D Page 9 of 30

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

T ruth Table

Notes

2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,

↑represents rising edge.

3. Device powers up deselected with the outputs in a tri-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.

5. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. It is recommended that K = K

and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging

symmetrically.

8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS

, NWS1, BWS0, BWS1, BWS2 and BWS3 can be altered on

different portions of a write cycle, as long as the setup and hold requirements are achieved.

The truth table for CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 follows.

Operation K LD R/W DQ DQ

Write Cycle:

L-H L L D(A + 0) at K(t + 1)↑ D(A + 1) at K(t + 1)↑ Load address; wait one cycle; input write data on consecutive K and K

Read Cycle:

rising edges.

L-H L H Q(A + 0) at C Load address; wait one and a half cycle; read data on consecutive C

and C rising edges. NOP: No Operation L-H H X High-Z High-Z Standby: Clock Stopped Stopped X X Previous State Previous State

[2, 3, 4, 5, 6, 7]

(t + 1)↑ Q(A + 1) at C(t + 2)↑

Write Cycle Descriptions

The write cycle description table for CY7C1422BV18 and CY7C1423BV18 follows.

BWS0/

NWS

BWS1/

NWS

Comments

L L L–H – During the data portion of a write sequence :

CY7C1422BV18 − both nibbles (D CY7C1423BV18 − both bytes (D

) are written into the device,

[7:0]

) are written into the device.

[17:0]

L L – L-H During the data portion of a write sequence :

CY7C1422BV18 − both nibbles (D CY7C1423BV18 − both bytes (D

) are written into the device,

[7:0]

) are written into the device.

[17:0]

L H L–H – During the data portion of a write sequence :

CY7C1422BV18 − only the lower nibble (D CY7C1423BV18 − only the lower byte (D

[3:0]

) is written into the device, D

[8:0]

L H – L–H During the data portion of a write sequence :

CY7C1422BV18 − only the lower nibble (D CY7C1423BV18 − only the lower byte (D

[3:0]

) is written into the device, D

[8:0]

H L L–H – During the data portion of a write sequence :

CY7C1422BV18 − only the upper nibble (D CY7C1423BV18 − only the upper byte (D

[7:4]

[17:9]

H L – L–H During the data portion of a write sequence :

CY7C1422BV18 − only the upper nibble (D CY7C1423BV18 − only the upper byte (D

[7:4]

[17:9]

H H L–H – No data is written into the devices during this portion of a write operation.

[2, 8]

) is written into the device, D

remains unaltered.

[7:4]

remains unaltered.

[17:9]

remains unaltered.

[7:4]

remains unaltered.

[17:9]

remains unaltered.

[3:0]

remains unaltered.

[8:0]

remains unaltered.

[3:0]

remains unaltered.

[8:0]

H H – L–H No data is written into the devices during this portion of a write operation.

Document #: 001-07035 Rev. *D Page 10 of 30

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Write Cycle Descriptions

The write cycle description table for CY7C1429BV18 follows.

[2, 8]

BWS

L L–H – During the Data portion of a write sequence, the single byte (D L – L–H During the Data portion of a write sequence, the single byte (D

K K Comments

) is written into the device.

[8:0]

) is written into the device.

[8:0]

H L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into the device during this portion of a write operation.

Write Cycle Descriptions

The write cycle description table for CY7C1424BV18 follows.

BWS0BWS1BWS2BWS3K K Comments

LLLLL–H–During the Data portion of a write sequence, all four bytes (D

the device.

LLLL–L–HDuring the Data portion of a write sequence, all four bytes (D

the device.

L H H H L–H – During the Data portion of a write sequence, only the lower byte (D

into the device. D

L H H H – L–H During the Data portion of a write sequence, only the lower byte (D

into the device. D

H L H H L–H – During the Data portion of a write sequence, only the byte (D

the device. D

H L H H – L–H Du ring the Data portion of a write sequence, only the byte (D

the device. D

H H L H L–H – During the Data portion of a write sequence, only the byte (D

the device. D

H H L H – L–H During the Data portion of a write sequence, only the byte (D

the device. D

H H H L L–H – During the Data portion of a write sequence, only the byte (D

the device. D

H H H L – L–H During the Data portion of a write sequence, only the byte (D

the device. D HHHHL–H–No data is written into the device during this portion of a write operation. HHHH–L–HNo data is written into the device during this portion of a write operation.

[2, 8]

[35:9]

and D

[8:0]

and D

[8:0]

and D

[17:0]

and D

[17:0]

remains unaltered.

[26:0]

remains unaltered.

[26:0]

remains unaltered.

[35:18]

remains unaltered.

[35:18]

remains unaltered.

[35:27]

remains unaltered.

[35:27]

[35:0]

[17:9]

[26:18]

[35:27]

) are written into

) is written

[8:0]

) is written

[8:0]

) is written into

Document #: 001-07035 Rev. *D Page 11 of 30

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IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA p ackage. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to V unconnected. Upon power up, the device comes up in a reset state, which does not interfere with the operation of the device.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State

Diagram on page 14. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data out from th e registers. The output is active, depending upon the current state of the TAP state machine (see Instruction Codes on page 17). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of th e SRAM and can be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK.

through a pull up resistor. TDO must be left

Instruction Register

Three-bit instructions can be serially loaded into the instructi on register. This register is loaded when it is placed between the TDI and TDO pins, as shown in TAP Controller Block Diagram on page 15. Upon power up, the instruction register i s loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section.

When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path.

Bypass Register

To save time when seri ally shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (V the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all of th e input and output pins on the SRAM. Several No Connect (NC) pins are also included in the scan register to reserve pins for higher density devices.

The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring.

The Boundary Scan Order on page 18 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 17.

) when

TAP Instruction Set

Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Instruction

Codes on page 17. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions are described in this section in detail.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state.

Document #: 001-07035 Rev. *D Page 12 of 30

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IDCODE

The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is supplied during the Update IR state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible.

To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (t correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK

After the data is captured, it is possible to shift out the data by putting the T AP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in.

and tCH). The SRAM clock input might not be captured

captured in the boundary scan register.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state.

EXTEST OUTPUT BUS TRI-ST ATE

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #108. When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is pre-set LOW to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Rese t state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

Document #: 001-07035 Rev. *D Page 13 of 30

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TAP Controller State Diagram

TEST-LOGIC RESET

TEST-LOGIC/ IDLE

SELECT DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDA TE-DR

SELECT IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDA TE-IR

Note

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

The state diagram for the TAP controller follows.

[9]

Document #: 001-07035 Rev. *D Page 14 of 30

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TAP Controller Block Diagram

012..29

3031

Boundary Scan Register

Identification Register

012..

.108

012

Instruction Register

Bypass Register

Selection Circuitry

TA P Controller

TDI

TDO

TCK TMS

Notes

10.These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.

11.Overshoot: V

(AC) < V

DDQ

+ 0.85V (Pulse width less than t

CYC

/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than t

CYC

/2).

12.All Voltage referenced to Ground.

TAP Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Max Unit

OH1

OH2

OL1

OL2

Output HIGH Voltage I Output HIGH Voltage I Output LOW Voltage IOL = 2.0 mA 0.4 V Output LOW Voltage IOL = 100 μA0.2V Input HIGH Voltage 0.65VDDV Input LOW Voltage –0.3 0.35V Input and Output Load Current GND ≤ VI ≤ V

[10, 11, 12]

= −2.0 mA 1.4 V

= −100 μA1.6 V

–5 5 μA

+ 0.3 V

Document #: 001-07035 Rev. *D Page 15 of 30

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TAP AC Switching Characteristics

(a)

TDO

= 20 pF

= 50

GND

0.9V

1.8V

ALL INPUT PULSES

0.9V

Test Clock

Test Mode Select

TCK

TMS

Test Data In TDI

Test Data Out

TCYC

TMSH

TMSS

TDIS

TDIH

TDOV

TDOX

TDO

Notes

13.t

and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

14.Test conditions are specified using the load in TAP AC Test Conditions. t

R/tF

= 1 ns.

Over the Operating Range

Parameter Description Min Max Unit

TCYC

TCK Clock Cycle Time 50 ns TCK Clock Frequency 20 MHz TCK Clock HIGH 20 ns TCK Clock LOW 20 ns

Setup Times

TMSS

TDIS

TMS Setup to TCK Clock Rise 5 ns TDI Setup to TCK Clock Rise 5 ns Capture Setup to TCK Rise 5 ns

Hold Times

TMSH

TDIH

TMS Hold after TCK Clock Rise 5 ns TDI Hold after Clock Rise 5 ns Capture Hold after Clock Rise 5 ns

Output Times

TDOV

TDOX

TCK Clock LOW to TDO Valid 10 ns TCK Clock LOW to TDO Invalid 0 ns

[13, 14]

TAP Timing and Test Conditions

Figure 2 shows the TAP timing and test conditions.

Figure 2. TAP Timing and Test Conditions

[14]

Document #: 001-07035 Rev. *D Page 16 of 30

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Identification Register Definitions

Instruction Field

Revision Number (31:29)

Cypress Device ID (28:12)

Cypress JEDEC ID (11:1)

ID Register Presence (0)

CY7C1422BV18 CY7C1429BV18 CY7C1423BV18 CY7C1424BV18

000 000 000 000 Version number.

11010100010000111 110101000100011 11 11010100010010111 11010100010100111 Defines the type of

00000110100 00000110100 00000110100 00000110100 Allows unique

1111Indicates the

Value

Description

SRAM.

identification of SRAM vendor.

presence of an ID register.

Scan Register Sizes

Instruction 3 Bypass 1 ID 32 Boundary Scan 109

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the input and output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register between TDI

RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

and TDO. Does not affect the SRAM operation.

operation.

Document #: 001-07035 Rev. *D Page 17 of 30

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Boundary Scan Order

Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID

0 6R 28 10G 56 6A 84 1J 16P299G575B852J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 47N329F605C882K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M

9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H

Document #: 001-07035 Rev. *D Page 18 of 30

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Power Up Sequence in DDR-II SRAM

DDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

Power Up Sequence

■ Apply power and drive DOFF either HIGH or LOW (All other

inputs can be HIGH or LOW).

❐ Apply V ❐ Apply V ❐ Drive DOFF HIGH.

■ Provide stable DOFF (HIGH), power and clock (K, K) for 1024

cycles to lock the DLL.

before V

DDQ

or at the same time as V

REF

Figure 3. Power Up Waveforms

DLL Constraints

■ DLL uses K clock as its synchronizing input. The input must

have low phase jitter, which is specified as t

■ The DLL functions at frequencies down to 120 MHz.

■ If the input clock is unstable and the DLL is enabled, then the

DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. T o avoid this, provide1024 cycles stable clock to relock to the desired clock frequency.

KC Var

Unstable Clock

> 1024 Stable clock

Start Normal Operation

Clock Start

DDQDD

(Clock Starts after Stable)

DDQDD

DOFF

DDQ

Stable (< +/- 0.1V DC per 50ns )

Fix High (or tie to V

DDQ

)

Document #: 001-07035 Rev. *D Page 19 of 30

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Maximum Ratings

Notes

15.Power up: assumes a linear ramp from 0V to V

(min) within 200 ms. During this time V

< V

and V

DDQ

< VDD.

16.Outputs are impedance controlled. I

= –(V

DDQ

/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

17.Outputs are impedance controlled. I

= (V

DDQ

/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

18.V

REF

(min) = 0.68V or 0.46V

DDQ

, whichever is larger, V

REF

(max) = 0.95V or 0.54V

DDQ

, whichever is smaller.

19.The operation current is calculated with 50% read cycle and 50% write cycle.

Exceeding maximum ratings may impair the useful life of th e device. These user guidelines are not tested.

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with Power Applied.. –55°C to +125°C

Supply Voltage on VDD Relative to GND........–0.5V to +2.9V

Supply Voltage on V

DC Applied to Outputs in High-Z ........ –0.5V to V

DC Input Voltage

Relative to GND.......–0.5V to +V

DDQ

[11]

..............................–0.5V to VDD + 0.3V

DDQ

+ 0.3V

Electrical Characteristics

Current into Outputs (LOW) ........................................20 mA

Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V

Latch-up Current ................................................... > 200 mA

Operating Range

Range

Temperature (TA) V

Commercial 0°C to +70°C 1.8 ± 0.1V 1.4V to Industrial –40°C to +85°C

Ambient

[15]

DDQ

[15]

DC Electrical Characteristics

Over the Operating Range

[12]

Parameter Description Test Conditions Min Typ Max Unit

DDQ

OH(LOW)

OL(LOW)

REF

[19]

Power Supply Voltage 1.7 1.8 1.9 V IO Supply Voltage 1.4 1.5 V Output HIGH Voltage Note 16 V Output LOW Voltage Note 17 V Output HIGH Voltage I

= −0.1 mA, Nominal Impedance V

Output LOW Voltage IOL = 0.1 mA, Nominal Impedance V Input HIGH Voltage V

/2 – 0.12 V

DDQ

/2 – 0.12 V

DDQ

– 0.2 V

DDQ

+ 0.1 V

REF

Input LOW Voltage –0.3 V Input Leakage Current GND ≤ VI ≤ V Output Leakage Current GND ≤ VI ≤ V Input Reference Voltage VDD Operating Supply V

[18]

Typical Value = 0.75V 0.68 0.75 0.95 V

= Max,

= 0 mA,

OUT

MAX

= 1/t

f = f

DDQ

Output Disabled −5 5 μA

DDQ,

300MHz (x8) 825 mA

CYC

(x9) 845

(x18) 880

−5 5 μA

/2 + 0.12 V

DDQ

/2 + 0.12 V

DDQ

0.2 V + 0.3 V

DDQ

– 0.1 V

REF

(x36) 980

278MHz (x8) 775 mA

(x9) 775 (x18) 815 (x36) 890

250MHz (x8) 700 mA

(x9) 700 (x18) 740 (x36) 800

Document #: 001-07035 Rev. *D Page 20 of 30

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Electrical Characteristics (continued)

DC Electrical Characteristics

Over the Operating Range

[12]

Parameter Description Test Conditions Min Typ Max Unit

VDD Operating Supply V

OUT

f = f

= Max,

= 0 mA,

= 1/t

MAX

CYC

200MHz (x8) 600 mA

(x9) 600 (x18) 600 (x36) 665

167MHz (x8) 500 mA

(x9) 500 (x18) 500 (x36) 560

SB1

Automatic Power down Current

Max VDD, Both Ports Deselected, V

≥ VIH or VIN ≤ VIL

MAX

= 1/t

CYC,

f = f Inputs Static

300MHz (x8) 325 mA

(x9) 325 (x18) 345 (x36) 375

278MHz (x8) 310 mA

(x9) 310 (x18) 325 (x36) 355

250MHz (x8) 300 mA

(x9) 300 (x18) 310 (x36) 330

200MHz (x8) 285 mA

(x9) 285 (x18) 290 (x36) 300

167MHz (x8) 275 mA

(x9) 275 (x18) 275 (x36) 285

AC Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Typ Max Unit

Input HIGH Voltage V Input LOW Voltage – – V

Document #: 001-07035 Rev. *D Page 21 of 30

[11]

+ 0.2 – – V

REF

– 0.2 V

REF

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Capacitance

1.25V

0.25V

R = 50Ω

5pF

INCLUDING

JIG AND

SCOPE

ALL INPUT PULSES

Device

= 50Ω

REF

= 0.75V

REF

= 0.75V

[20]

0.75V

Under Test

0.75V

Device Under Test

OUTPUT

0.75V

REF

OUTPUT

(a)

Slew Rate = 2 V/ns

RQ = 250

(b)

RQ = 250

Note

20.Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V

DDQ

= 1.5V, input

pulse levels of 0.25V to 1.25V, and output loading of the specified I

OL/IOH

and load capacitance shown in (a) of AC Test Loads and Waveforms.

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions

Input Capacitance TA = 25°C, f = 1 MHz, VDD = 1.8V, V

CLK

Clock Input Capacitance 4 pF Output Capacitance 5pF

DDQ

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions

Thermal Resistance

(Junction to Ambient) Thermal Resistance

(Junction to Case)

Test conditi ons follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51.

Figure 4. AC Test Loads and Waveforms

Max

Unit

= 1.5V 5 pF

165 FBGA

Package

Unit

17.2 °C/W

3.2 °C/W

Document #: 001-07035 Rev. *D Page 22 of 30

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Switching Characteristics

Notes

21.When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires th e input timings of the freque ncy range in which it is being operated and outputs data with the output timings of that fre quency range.

22.This part has a voltage regulator internally; t

POWER

is the time that the power must be supplied above VDD minimum initially before a read or write operation can be

initiated.

23.For D2 data signal on CY7C1429BV18 device, t

is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies.

Over the Operating Range

[20, 21]

Cypress

Parameter

POWER

CYC

KHKH

KHCH

Consortium

Parameter

KHKH

KHKL

KLKH

KHKH

KHCH

Setup Times

SCDDR

[23]

AVKH

IVKH

DVKH

Hold Times

HCDDRtKHIX

KHAX

KHIX

KHDX

Description

Unit

Min Max Min Max Min Max Min Max Min Max

300 MHz 278 MHz 250 MHz 200 MHz 167 MHz

VDD(Typical) to the First Access

[22]

11111ms

K Clock and C Clock Cycle Time 3.3 8.4 3.6 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns Input Clock (K/K; C/C) HIGH Input Clock (K/K; C/C) LOW

K Clock Rise to K Clock Rise and C to C

Rise (rising edge to rising edge)

K/K Clock Rise to C/C Clock Rise

1.32 – 1.4 – 1.6 – 2.0 – 2.4 – ns

1.49 – 1.6 – 1.8 – 2.2 – 2.7 – ns

01.4501.5501.802.202.7ns

(rising edge to rising edge)

Address Setup to K Clock Rise 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns Control Setup to K Clock Rise

, R/W)

(LD Double Data Rate Control Setup to

Clock (K/K (BWS

[X:0]

) Rise

, BWS1, BWS2, BWS3)

Setup to Clock (K/K) Rise

Address Hold after K Clock Rise Control Hold after K Clock Rise

0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns

0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns

0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns

(LD, R/W) Double Data Rate Control Hold after

Clock (K/K (BWS

[X:0]

) Rise

, BWS1, BWS2, BWS3)

Hold after Clock (K/K) Rise

0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns

Document #: 001-07035 Rev. *D Page 23 of 30

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Switching Characteristics (continued)

Notes

24.These parameters are extrapolated from the input timing parameters (t

KHKH

- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t

KC Var

) is already

included in the t

KHKH

). These parameters are only guaranteed by design and are not tested in production.

25.t

CHZ

, t

CLZ

, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady-state voltage.

26.At any voltage and temperature t

CHZ

is less than t

CLZ

and t

CHZ

less than tCO.

Over the Operating Range

[20, 21]

Cypress

Parameter

Consortium

Parameter

Output Times

DOH

CCQO

CQOH

CQD

CQDOHtCQHQX

CQH

CQHCQHtCQHCQH

CHZ

CLZ

CHQV

CHQX

CHCQV

CHCQX

CQHQV

CQHCQL

CHQZ

CHQX1

DLL Timing

KC Var

KC lock

KC ResettKC Reset

KC Var

KC lock

Description

Unit

Min Max Min Max Min Max Min Max Min Max

300 MHz 278 MHz 250 MHz 200 MHz 167 MHz

C/C Clock Rise (or K/K in single

– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns

clock mode) to Data Valid Data Output Hold after Output C/C

–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns

Clock Rise (Active to Active) C/C Clock Rise to Echo Clock Valid Echo Clock Hold after C/C Clock

– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns

–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns

Rise Echo Clock High to Data Valid 0.27 0.27 0.30 0.35 0.40 ns Echo Clock High to Data Invalid –0.27 – –0.27 – –0.30 – –0.35 – –0.40 – ns Output Clock (CQ/CQ) HIGH

CQ Clock Rise to CQ Clock Rise (rising edge to rising edge)

Clock (C/C) Rise to High-Z (Active to High-Z)

[25, 26]

Clock (C/C) Rise to Low-Z

[24]

[25, 26]

1.24–1.35–1.55–1.95–2.45– ns

– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns

–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns

Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 – 0.20 ns DLL Lock Time (K, C) 1024 – 1024 – 1024 – 1024 – 1024 – Cycles K Static to DLL Reset 30 30 30 30 30 ns

Document #: 001-07035 Rev. *D Page 24 of 30

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Switching Waveforms

Notes

27.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.

28.Outputs are disabled (High-Z) one clock cycle after a NOP.

29.In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded imme diately as read resu lts. This note applies to t he whole diagram.

Figure 5. Read/Write/Deselect Sequence

[27, 28, 29]

NOP

READ (burst of 2)

WRITE (burst of 2)

READ (burst of 2)

NOP

1234567

R/W

KHCH

SAtHA

CYC

A0 A1 A2

KHCH

KHKH

CLZ

Q00

Q01

CQDOH

A3 A4

D20 D21 D30 D31

Q11Q10

CQD

DOH

CHZ

Q40

Q41

CQ#

CQOH

CCQO

CQOH

CCQO

CQH

DON’T CARE UNDEFINED

CYC

CQHCQH

Document #: 001-07035 Rev. *D Page 25 of 30

KHKH

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Ordering Information

Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed

(MHz)

300 CY7C1422BV18-300BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1429BV18-300BZC CY7C1423BV18-300BZC CY7C1424BV18-300BZC CY7C1422BV18-300BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1429BV18-300BZXC CY7C1423BV18-300BZXC CY7C1424BV18-300BZXC CY7C1422BV18-300BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial CY7C1429BV18-300BZI CY7C1423BV18-300BZI CY7C1424BV18-300BZI CY7C1422BV18-300BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1429BV18-300BZXI CY7C1423BV18-300BZXI CY7C1424BV18-300BZXI

278 CY7C1422BV18-278BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1429BV18-278BZC CY7C1423BV18-278BZC CY7C1424BV18-278BZC CY7C1422BV18-278BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1429BV18-278BZXC CY7C1423BV18-278BZXC CY7C1424BV18-278BZXC CY7C1422BV18-278BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial CY7C1429BV18-278BZI CY7C1423BV18-278BZI CY7C1424BV18-278BZI CY7C1422BV18-278BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1429BV18-278BZXI CY7C1423BV18-278BZXI CY7C1424BV18-278BZXI

Ordering Code

Package Diagram

Package Type

Operating

Range

Document #: 001-07035 Rev. *D Page 26 of 30

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Ordering Information (continued)

Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed

(MHz)

250 CY7C1422BV18-250BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1429BV18-250BZC CY7C1423BV18-250BZC CY7C1424BV18-250BZC CY7C1422BV18-250BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1429BV18-250BZXC CY7C1423BV18-250BZXC CY7C1424BV18-250BZXC CY7C1422BV18-250BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial CY7C1429BV18-250BZI CY7C1423BV18-250BZI CY7C1424BV18-250BZI CY7C1422BV18-250BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1429BV18-250BZXI CY7C1423BV18-250BZXI CY7C1424BV18-250BZXI

200 CY7C1422BV18-200BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1429BV18-200BZC CY7C1423BV18-200BZC CY7C1424BV18-200BZC CY7C1422BV18-200BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1429BV18-200BZXC CY7C1423BV18-200BZXC CY7C1424BV18-200BZXC CY7C1422BV18-200BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial CY7C1429BV18-200BZI CY7C1423BV18-200BZI CY7C1424BV18-200BZI CY7C1422BV18-200BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1429BV18-200BZXI CY7C1423BV18-200BZXI CY7C1424BV18-200BZXI

Ordering Code

Package Diagram

Package Type

Operating

Range

Document #: 001-07035 Rev. *D Page 27 of 30

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Ordering Information (continued)

Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed

(MHz)

167 CY7C1422BV18-167BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1429BV18-167BZC CY7C1423BV18-167BZC CY7C1424BV18-167BZC CY7C1422BV18-167BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1429BV18-167BZXC CY7C1423BV18-167BZXC CY7C1424BV18-167BZXC CY7C1422BV18-167BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial CY7C1429BV18-167BZI CY7C1423BV18-167BZI CY7C1424BV18-167BZI CY7C1422BV18-167BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1429BV18-167BZXI CY7C1423BV18-167BZXI CY7C1424BV18-167BZXI

Ordering Code

Package Diagram

Package Type

Operating

Range

Document #: 001-07035 Rev. *D Page 28 of 30

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Package Diagram



0).#/2.%2

¼

¼





8

-#!"

-#

8

¼

-!8

3%!4).'0,!.%

¼

#

#

0).#/2.%2

4/06)%7

"/44/-6)%7







(





(







 

3/,$%20!$490%./.3/,$%2-!3+$%&).%$.3-$

./4%3

0!#+!'%7%)'(4G

*%$%#2%&%2%.#%-/$%3)'.#

0!#+!'%#/$%""!$

51-85195-*A

Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-85195

Document #: 001-07035 Rev. *D Page 29 of 30

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Document History Page

Document Title: CY7C1422BV18/CY7C1429BV18/CY7C1423BV18/CY7C1424BV18, 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Document Number: 001-07035

REV. ECN NO.

SUBMISSION

DATE

ORIG. OF CHANGE

DESCRIPTION OF CHANGE

** 433267 See ECN NXR New Data Sheet

*A 4620 04 See ECN NXR Changed t

changed t from 20 ns to 10 ns in TAP AC Switching Characteristics table

from 100 ns to 50 ns, changed t

TCYC

, t

TMSS

TDIS

, tCS, t

TMSH

, t

TDIH

and t

, t

from 10 ns to 5 ns and changed t

from 40 ns to 20 ns,

TDOV

Modified Power-Up waveform *B 5036 90 See ECN VKN Minor change: Moved data sheet to web *C 1523289 See ECN VKN/AESA Converted from preliminary to final, Updated Logic Block diagram, Updated I

specs, Changed DLL minimum operating frequency from 80MHz to 120MHz

Changed t

max spec to 8.4ns for all speed bins, Modified footnotes 20 and 28

CYC

DD/ISB

*D 2478647 See ECN VKN/AESA Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to

“–55°C to +125°C” in the “Maximum Ratings “ on page 20, Updated Power-up

sequence waveform and it’s description, Added footnote #19 related to I

Changed JTAG ID [31:29] from 001 to 000.

DD,

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Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States co pyright la ws and inte rnatio na l tre aty prov isi ons. Cyp ress he reby g rant s to lice nsee a p erson al, no n-ex clusi ve, non-tra nsferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpo se of creating custom sof tware and or firm ware in support of licen see product to be use d only in conjunction with a Cypress integrated circuit as specified in th e applicable agreement. Any reproductio n, modification, translation, co mpilation, o r representati on of this Sour ce Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the ap plicati on or u se o f any pr oduct o r circui t descri bed h erein. Cypr ess does not aut horize it s product s for use a s critical compo nent s in life-support systems whe re a malfunction or failure may reasonab ly be expected to resu lt in significant injury t o the user. The inclusion of Cypress’ prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 001-07035 Rev. *D Revised June 16, 2008 Page 30 of 30

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.

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Specifications and Main Features

Frequently Asked Questions

User Manual