2K x 8 Dual-Port Static RAM
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Features
R/W
L
BUSY
L
CE
L
OE
L
A
10L
A
0L
A
0R
A
10R
R/W
R
CE
R
OE
R
CE
R
OE
R
CE
L
OE
L
R/W
L
R/W
R
I/O
7L
I/O
0L
I/O
7R
I/O
0R
BUSY
R
INT
L
INT
R
ARBITRATION
LOGIC
(7C132/7C136 ONLY)
AND
INTERRUPTLOGIC
(7C136/7C146ONLY)
CONTROL
I/O
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
[2]
[3]
[3]
[2]
Logic Block Diagram
Notes
1. CY7C136 and CY7C136A are functionally identical.
2. CY7C132/CY7C136/CY7C136A (Master): BUSY
is open drain output and requires pull up resistor . CY7C142/CY7C146 (Slave): BUSY is input.
3. Open drain outputs; pull up resistor required.
Functional Description
■ True dual-ported memory cells that enable simultaneous reads
of the same memory location
■ 2K x 8 organization
■ 0.65 micron CMOS for optimum speed and power
■ High speed access: 15 ns
■ Low operating power: I
■ Fully asynchronous operation
■ Automatic power down
■ Master CY7C132/CY7C136/CY7C136A
= 110 mA (maximum)
CC
[1]
easily expands data
bus width to 16 or more bits using slave CY7C142/CY7C146
■ BUSY output flag on CY7C132/CY7C136/CY7C136A;
BUSY input on CY7C142/CY7C146
■ INT flag for port to port communication (52-Pin PLCC/PQFP
versions)
■ CY7C136, CY7C136A, and CY7C146 available in 52-pin
PLCC and 52-pin PQFP packages
■ Pb-free packages available
The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146
are high speed CMOS 2K x 8 dual-port static RAMs. Two ports
are provided to permit independent access to any location in
memory. The CY7C132, CY7C136, and CY7C136A can be used
as either a standalone 8-bit dual-port static RAM or as a
MASTER dual-port RAM, in conjunction with the
CY7C142/CY7C146 SLAVE dual-port device. They are used in
systems that require 16-bit or greater word widths. This is the
solution to applications that require shared or buffered data, such
as cache memory for DSP, bit-slice, or multiprocessor designs.
Each port has independent control pins; chip enable (CE
enable (R/W
on each port. In addition, an interrupt flag (INT
each port of the 52-pin PLCC version. BUSY
), and output enable (OE). BUSY flags are provided
) is provided on
signals that the port
), write
is trying to access the same location currently being accessed
by the other port. On the PLCC version, INT
is an interrupt flag
indicating that data is placed in an unique location (7FF for the
left port and 7FE for the right port).
An automatic power down feature is controlled independently on
each port by the chip enable (CE
) pins.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06031 Rev. *E Revised March 24, 2009
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Pinouts
1
V
CC
OE
R
A
0R
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
2122 23 24 25 26 27 28 29 30 31 32 33
7 6 5 4 3 2 52 51 50 49 48 47
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4L5L6L
7L
0R1R2R3R4R5R6R
NC
GND
OE
BUSY
INT
A
R/W
CE
R/W
BUSY
INT
0L
L
L
L
L
L
CE
R
R
R
R
7C136/7C136A
7C146
A
10L
A
10R
46
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
1415 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 45 44 43 42 41 40
V
CC
OE
BUSY
INT
A
R/W
CE
R/W
BUSY
INT
0L
L
L
L
L
LCER
R
R
R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
NC
I/O
7R
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4L5L6L
7L
0R1R2R3R4R5R6R
NC
GND
7C136/7C136A
7C146
A
10L
A
10R
Note:
4. 15 ns and 25 ns version available in PQFP and PLCC packages only.
Figure 1. 52-Pin PLCC (Top View) Figure 2. 52-Pin PQFP (Top View)
Selection Guide
[4]
7C132-30
7C136-30
7C142-30
7C146-30
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
Specification
Maximum Access Time
7C132-25
7C136-15
7C146-15
[4]
7C136-25
7C142-25
7C146-25
15 25 30 35 45 55 ns
Maximum Operating Current Com’l/Ind 190 170 170 120 120 110 mA
Maximum Standby Current Com’l/Ind
Shaded areas contain preliminary information.
75 65 65 45 45 35 mA
7C132-55
7C136-55
7C136A-55
7C142-55
7C146-55
Unit
Document #: 38-06031 Rev. *E Page 2 of 15
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Maximum Ratings
Notes
5. BUSY
and INT pins only.
6. Duration of the short circuit should not exceed 30 seconds.
7. At f = f
MAX
, address and data inputs are cycling at the maximum frequency of read cycle of 1/trc and using AC Test Waveforms input levels of GND to 3V.
Exceeding maximum ratings may impair the useful life of th e
device. These user guidelines are not tested.
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage to Ground Potential
(Pin 48 to Pin 24)................................................. −0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
I
OH
OL
IH
IL
IX
OZ
OS
CC
SB1
Output HIGH
voltage
Output LOW
voltage
Input HIGH
voltage
Input LOW
voltage
Input load current GND < VI < V
Output leakage
current
Output short
circuit current
VCC Operating
Supply Current
Standby current
both ports, TTL
Inputs
I
SB2
Standby Current
One Port,
TTL Inputs
I
SB3
Standby Current
Both Ports,
CMOS Inputs
I
SB4
Standby Current
One Port,
CMOS Inputs
Shaded areas contain preliminary information.
VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 2.4 V
IOL = 4.0 mA 0.4 0.4 0.4 0.4 V
= 16.0 mA
I
OL
[5]
CC
GND < VO < VCC, Output Disabled –5 +5 −5+5−5+5−5+5μA
VCC = Max., V
[6]
= GND –350 −350 −350 −350 mA
OUT
CE = VIL, Outputs Open,
MAX
[7]
f = f
CEL and CER > VIH,
f = f
CE
[7]
MAX
or CER > VIH,
L
Active Port Outputs Open,
f = f
Both Ports CE
CE
or V
One Port CE
V
Active Port Outputs Open, f = f
[7]
MAX
and
> VCC – 0.2V , VIN > VCC – 0.2V
R
< 0.2V , f = 0
IN
> VCC – 0.2V or VIN < 0.2V ,
IN
L
or CER > VCC – 0.2V ,
L
MAX
DC Input Voltage................................................. −3.5V to +7.0V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch up Current.................................................... > 200 mA
Operating Range
Range Ambient Temperature V
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
[4]
7C132-35,45
7C136-35,45
7C142-35,45
7C146-35,45
7C136-15
7C146-15
7C132-30
[4]
7C136-25, 30
7C142-30
7C146-25, 30
Min Max Min Max Min Max Min Max
0.5 0.5 0.5 0.5
2.2 2.2 2.2 2.2 V
0.8 0.8 0.8 0.8 V
–5 +5 −5+5−5+5−5+5μA
Com’l/
190 170 120 110 mA
Ind’l
Com’l/
75 65 45 35 mA
Ind’l
Com’l/
135 115 90 75 mA
Ind’l
Com’l/
15 15 15 15 mA
Ind’l
Com’l/
125 105 85 70 mA
Ind’l
[7]
7C132-55
7C136-55
7C136A-55
7C142-55
7C146-55
CC
Unit
Document #: 38-06031 Rev. *E Page 3 of 15
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
3.0V
5V
OUTPUT
R1 893Ω
R2
347Ω
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
90%
10%
<5ns
<5ns
5V
OUTPUT
R1 893Ω
R2
347Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT 1.4V
Equivalent to: TH ÉVENIN
EQUIVALENT
5V
281Ω
30 pF
BUSY
OR
INT
BUSY Output Load
(CY7C132/CY7C136 Only)
10%
ALL INPUT PULSES
250Ω
Notes
8. Test conditions assume signal transition t imes of 5 ns or le ss, t iming re ference levels of 1. 5V, input pulse levels of 0 to 3.0V and output loading of th e specified I
OL/IOH,
and 30 pF load capacitance.
9. AC test conditions use V
OH
= 1.6V and VOL = 1.4V.
10.At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
11. t
LZCE
, t
LZWE
, t
HZOE
, t
LZOE, tHZCE,
and t
HZWE
are tested with CL = 5pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 500 mV from steady state
voltage.
Capacitance
This parameter is guaranteed but not tested.
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0V 15 pF
Output Capacitance 10 pF
Figure 3. AC Test Loads and Waveforms
Switching Characteristics
Over the Operating Range (Speeds -15, -25, -30)
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Shaded areas contain preliminary information.
Document #: 38-06031 Rev. *E Page 4 of 15
Read Cycle Time 15 25 30 ns
Address to Data Valid
[9]
Data Hold from Address Change 0 00ns
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
[9]
[9]
[7, 10]
[7, 10, 11]
[7, 10]
[7, 10, 11]
[7]
CE HIGH to Power Down
[8]
[7]
[4]
7C132-30
7C136-30
7C142-30
7C146-30
7C136-15
7C146-15
[4]
7C132-25
7C136-25
7C142-25
7C146-25
Min Max Min Max Min Max
15 25 30 ns
15 25 30 ns
10 15 20 ns
3 33ns
10 15 15 ns
3 55ns
10 15 15 ns
0 00ns
15 25 25 ns
Unit
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Characteristics
Notes
12.The internal write time of the memory is defined by the overlap of CE
LOW and R/W LOW. Both signals must be LOW t o initiate a write and eit her signal can terminate
a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.
13.These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.
14.CY7C142/CY7C146 only.
15.A write operation on Port A, where Port A has priority , leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY
on Port B goes HIGH.
Port B’s address toggled.
CE
for Port B is toggled.
R/W
for Port B is toggled during valid read.
16.52-pin PLCC and PQFP versions only.
Over the Operating Range (Speeds -15, -25, -30)
Parameter Description
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Busy/Interrupt Timing
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD
t
DDD
t
WDD
Interrupt Timing
t
WINS
t
EINS
t
INS
t
OINR
t
EINR
t
INR
Shaded areas contain preliminary information.
[12]
Write Cycle Time 15 25 30 ns
CE LOW to Write End 12 20 25 ns
Address Setup to Write End 12 20 25 ns
Address Hold from Write End 2 22ns
Address Setup to Write Start 0 00ns
R/W Pulse Width 12 15 25 ns
Data Setup to Write End 10 15 15 ns
Data Hold from Write End 0 00ns
R/W LOW to High Z
R/W HIGH to Low Z
[7]
[7]
BUSY LOW from Address Match 15 20 20 ns
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW 15 20 20 ns
BUSY HIGH from CE HIGH
[13]
Port Set Up for Priority 5 55ns
R/W LOW after BUSY LOW
[14]
R/W HIGH after BUSY HIGH 13 20 30 ns
BUSY HIGH to Valid Data 15 25 30 ns
Write Data V alid to Read Data Valid Note 15 Note 15 Note 15 ns
Write Pulse to Data Delay Note 15 Note 15 Note 15 ns
[16]
R/W to INTERRUPT Set Time 15 25 25 ns
CE to INTERRUPT Set Time 15 25 25 ns
Address to INTERRUPT Set Time 15 25 25 ns
OE to INTERRUPT Reset Time
CE to INTERRUPT Reset T i me
Address to INTERRUPT Reset Time
[8]
(continued)
[13]
[13]
[13]
[13]
[4]
7C132-30
7C136-30
7C142-30
7C146-30
Unit
7C136-15
7C146-15
[4]
7C132-25
7C136-25
7C142-25
7C146-25
Min Max Min Max Min Max
10 15 15 ns
0 00ns
15 20 20 ns
15 20 20 ns
0 00ns
15 25 25 ns
15 25 25 ns
15 25 25 ns
Document #: 38-06031 Rev. *E Page 5 of 15
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Characteristics
Over the Operating Range (Speeds -35, -45, -55)
Parameter Description
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Busy/Interrupt Timing
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD
t
DDD
t
WDD
Read Cycle Time 35 45 55 ns
Address to Data Valid
[9]
Data Hold from Address Change 0 0 0 ns
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up
CE HIGH to Power Down
[12]
[9]
[9]
[7, 10]
[7, 10, 11]
[7, 10]
[7, 10, 11]
[7]
[7]
Write Cycle Time 35 45 55 ns
CE LOW to Write End 30 35 40 ns
Address Setup to Write End 30 35 40 ns
Address Hold from Write End 2 2 2 ns
Address Setup to Write Start 0 0 0 ns
R/W Pulse Width 25 30 30 ns
Data Setup to Write End 15 20 20 ns
Data Hold from Write End 0 0 0 ns
R/W LOW to High Z
R/W HIGH to Low Z
[7]
[7]
BUSY LOW from Address Match 20 25 30 ns
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW 20 25 30 ns
BUSY HIGH from CE HIGH
[13]
Port Set Up for Priority 5 5 5 ns
R/W LOW after BUSY LOW
[14]
R/W HIGH after BUSY HIGH 30 35 35 ns
BUSY HIGH to Valid Data 35 45 45 ns
Write Data Valid to Read Data Valid Note 15 Note 15 Note 15 ns
Write Pulse to Data Delay Note 15 Note 15 Note 15 ns
[8]
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C136A-55
7C142-55
7C146-55
Unit
Min Max Min Max Min Max
35 45 55 ns
35 45 55 ns
20 25 25 ns
333ns
20 20 25 ns
555ns
20 20 25 ns
000ns
35 35 35 ns
20 20 25 ns
000ns
[13]
20 25 30 ns
20 25 30 ns
000ns
Document #: 38-06031 Rev. *E Page 6 of 15
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Characteristics
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
DATA OUT
CE
OE
t
LZCE
t
PU
I
CC
I
SB
t
PD
Notes
17.R/W
is HIGH for read cycle.
18.Device is continuously selected, CE
= VIL and OE = VIL.
19.Address valid prior to or coincident with CE
transition LOW.
Over the Operating Range (Speeds -35, -45, -55)
Parameter Description
Interrupt Timing
t
WINS
t
EINS
t
INS
t
OINR
t
EINR
t
INR
[16]
R/W to INTERRUPT Set Time 25 35 45 ns
CE to INTERRUPT Set Time 25 35 45 ns
Address to INTERRUPT Set Time 25 35 45 ns
OE to INTERRUPT Reset Time
CE to INTERRUPT Reset T i me
Address to INTERRUPT Reset Time
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port-Address Access)
[8]
(continued)
[13]
[13]
[13]
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C136A-55
7C142-55
7C146-55
Min Max Min Max Min Max
25 35 45 ns
25 35 45 ns
25 35 45 ns
[17, 18]
Unit
Figure 5. Read Cycle No. 2 (Either Port-CE/OE )
Document #: 38-06031 Rev. *E Page 7 of 15
[17, 19]
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Waveforms (continued)
t
BHA
t
BDD
VALID
t
DDD
t
WDD
ADDRESS MATCH
ADDRESS MATCH
R/W
R
ADDRESS
R
D
INR
ADDRESS
L
BUSY
L
DOUT
L
t
PS
t
BLA
t
RC
t
PWE
VALID
t
AW
t
WC
DATA VALID
HIGH IMPEDANCE
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HA
t
HZOE
CE
R/W
ADDRESS
OE
D
OUT
DATA
IN
Note
20.If OE
is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or t
HZWE
+ tSD to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required tSD.
Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136/CY7C136A)
Figure 7. Write Cycle No.1 (OE Three-States Data I/Os—Either Port)
[12, 20]
Document #: 38-06031 Rev. *E Page 8 of 15
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Waveforms (continued)
t
AW
t
WC
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HZWE
t
HA
HIGH IMPEDANCE
CE
R/W
ADDRESS
D
OUT
DATA
IN
t
LZWE
DATAVALID
ADDRESS MATCH
t
PS
CEL Valid First:
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
BUSY
L
CE
R
CE
L
ADDRESS
L,R
BUSY
R
CE
L
CE
R
ADDRESS
L,R
CER Valid First:
Note
21.If the CE
LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high impedance state.
Figure 8. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)
Figure 9. Busy Timing Diagram No. 1 (CE Arbitration)
[12, 21]
Document #: 38-06031 Rev. *E Page 9 of 15
[+] Feedback
CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Waveforms (continued)
Left Address Valid First:
ADDRESS MATCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMATCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MATCH ADDRESS MISMATCH
t
PS
ADDRESS
L
BUSY
L
tRCor t
WC
t
BLA
t
BHA
ADDRESS
R
Right Address Valid First:
t
PWE
t
WB
t
WH
BUSY
R/W
CE
Figure 10. Busy Timing Diagram No. 2 (Address Arbitration)
Figure 11. Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146)
Document #: 38-06031 Rev. *E Page 10 of 15
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CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Waveforms (continued)
WRITE 7FF
t
INS
ADDRESS
L
R/W
L
t
WC
t
EINS
CE
L
t
HA
t
SA
t
WINS
INT
R
READ 7FF
t
RC
t
EINR
t
HA
t
INR
t
OINR
ADDRESS
R
CE
R
R/W
R
INT
R
OE
R
WRITE 7FE
t
INS
ADDRESS
R
R/W
R
t
WC
t
EINS
CE
R
t
HA
t
SA
t
WINS
INT
L
READ 7FE
t
EINR
t
HA
t
INR
t
OINR
ADDRESS
L
CE
L
R/
W
L
INT
L
OE
L
t
RC
Interrupt Timing Diagrams
[16]
Figure 12. Left Side Sets INT
R
Figure 13. Right Side Clears INT
Figure 14. Right Side Sets INT
R
L
Document #: 38-06031 Rev. *E Page 11 of 15
Figure 15. Right Side Clears INT
L
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CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Figure 16. Typical DC and AC Characteristics
1.4
1.0
0.4
4.0 4.5 5.0 5.5 6.0
–55 25 125
1.2
1.0
120
100
80
60
40
20
0 1.0 2.0 3.0 4.0
OUTPUT SOURCE CURRENT (mA)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.0
0.8
0.8
0.6
0.6
NORMALIZED I
CC
, I
SB
V
CC
= 5.0V
V
IN
= 5.0V
TA= 25°C
0
I
CC
I
CC
1.6
1.4
1.2
1.0
0.8
–55 125
NORMALIZED t
AA
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
1.4
1.3
1.2
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED t
AA
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
80
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.6
0.8
1.25
1.0
0.75
10 40
NORMALIZED I
CC
0.50
NORMALIZED I
CC
vs. CYCLE TIME
CYCLE FREQUENCY (MHz)
3.0
2.5
2.0
1.5
0.5
0 1.0 2.0 3.0 5.0
NORMALIZED t
PC
25.0
30.0
20.0
10.0
5.0
0 200 400 600 800
DELTA t
AA
(ns)
0
15.0
0.0
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
4.0
1000
1.0
20 30
0.2
0.6
1.2
I
SB3
0.2
0.4
I
SB3
25
1.1
V
IN
= 0.5V
NORMALIZED I
CC
, I
SB
V
CC
= 5.0V
TA= 25°C
V
CC
= 5.0V
V
CC
= 5.0V
TA= 25°C
T
A
= 25°C
V
CC
= 4.5V
V
CC
= 5.0V
TA= 25°C
Document #: 38-06031 Rev. *E Page 12 of 15
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CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Ordering Information
Speed
(ns)
15 CY7C136-15JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial
25 CY7C136-25JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial
30 CY7C136-30JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial
35 CY7C136-35JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial
45 CY7C136-45JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial
55 CY7C136-55JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial
15 CY7C146-15JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial
25 CY7C146-25JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial
30 CY7C146-30JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial
35 CY7C146-35JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial
45 CY7C146-45JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial
55 CY7C146-55JC 51-85004 52-Pin Plastic Leaded Chip Carrier Commercial
Ordering Code
CY7C136-15NC 51-85042 52-Pin Plastic Quad Flatpack
CY7C136-25JXC 52-Pin Plastic Leaded Chip Carrier (Pb-Free)
CY7C136-25NC 51-85042 52-Pin Plastic Quad Flatpack
CY7C136-25NXC 52-Pin Plastic Quad Flatpack (Pb-Free)
CY7C136-25JXI 51-85004 52-Pin Plastic Leaded Chip Carrier (Pb-Free) Industrial
CY7C136-30NC 51-85042 52-Pin Plastic Quad Flatpack
CY7C136-30JI 51-85004 52-Pin Plastic Leaded Chip Carrier Industrial
CY7C136-35NC 51-85042 52-Pin Plastic Quad Flatpack
CY7C136-35JI 51-85004 52-Pin Plastic Leaded Chip Carrier Industrial
CY7C136-45NC 51-85042 52-Pin Plastic Quad Flatpack
CY7C136-45JI 51-85004 52-Pin Plastic Leaded Chip Carrier Industrial
CY7C136-55JXC 52-Pin Plastic Leaded Chip Carrier (Pb-Free)
CY7C136-55NC 51-85042 52-Pin Plastic Quad Flatpack
CY7C136-55NXC 52-Pin Plastic Quad Flatpack (Pb-Free)
CY7C136-55JI 51-85004 52-Pin Plastic Leaded Chip Carrier Industrial
CY7C136A-55JXI 52-Pin Plastic Leaded Chip Carrier (Pb-Free)
CY7C136-55NI 51-85042 52-Pin Plastic Quad Flatpack
CY7C136A-55NXI 52-Pin Plastic Quad Flatpack (Pb-Free)
CY7C146-15NC 51-85042 52-Pin Plastic Quad Flatpack
CY7C146-25JXC 52-Pin Plastic Leaded Chip Carrier (Pb-Free)
CY7C146-25NC 51-85042 52-Pin Plastic Quad Flatpack
CY7C146-30NC 51-85042 52-Pin Plastic Quad Flatpack
CY7C146-30JI 51-85004 52-Pin Plastic Leaded Chip Carrier Industrial
CY7C146-35NC 51-85042 52-Pin Plastic Quad Flatpack
CY7C146-35JI 51-85004 52-Pin Plastic Leaded Chip Carrier Industrial
CY7C146-45NC 51-85042 52-Pin Plastic Quad Flatpack
CY7C146-45JI 51-85004 52-Pin Plastic Leaded Chip Carrier Industrial
CY7C146-55JXC 52-Pin Plastic Leaded Chip Carrier (Pb-Free)
CY7C146-55NC 51-85042 52-Pin Plastic Quad Flatpack
CY7C146-55JI 51-85004 52-Pin Plastic Leaded Chip Carrier Industrial
Package
Diagram
Package Type
Operating
Range
Document #: 38-06031 Rev. *E Page 13 of 15
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CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Package Diagrams
51-85004-*A
51-85042-**
Figure 17. 52-Pin Plastic Leaded Chip Carrier, 51-85004
Figure 18. 52-Pin Plastic Quad Flatpack, 51-85042
Document #: 38-06031 Rev. *E Page 14 of 15
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CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Document History Page
Document Title: CY7C132, CY7C136, CY7C136A, CY7C142, CY7C146 2K x 8 Dual-Port Static RAM
Document Number: 38-06031
Revision ECN
Submission
Date
Orig. of
Change
Description of Change
** 110171 10/21/01 SZV Change from Spec number: 38-06031
*A 128959 09/03/03 JFU Added CY7C136-55NI to Order Information
*B 236748 See ECN YDT Removed cross information from features section
*C 393184 See ECN YIM Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C136-25JXC, CY7C136-25NXC, CY7C136-55JXC, CY7C136-55NXC,
CY7C136-55JXI, CY7C136-55NXI, CY7C146-25JXC, CY7C146-55JXC
*D 2623658 12/17/08 VKN/PYRS A dded CY7C136-25JXI part
Removed CY7C132/142 from the Ordering information table
Removed 48-Pin DIP and 52-Pin Square LCC package from the data sheet
*E 2678221 03/24/2009 VKN/AESA Added CY7C136A-55JXI, and CY7C136A-55NXI parts.
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Document #: 38-06031 Rev. *E Revised March 24, 2009 Page 15 of 15
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