32K x 8 3.3V Static RAM
CY7C1399B
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05071 Rev. *A Revised June 19, 2001
399B
Features
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed
—10/12/15 ns
• Low active power
—216 mW (max.)
• Low-power alpha immune 6T cell
• Plastic SOJ and TSOP packaging
Functional Description
The CY7C1399B is a high-performance 3.3V CMOS Static
RAM organize d as 3 2,7 68 wo rd s b y 8 bi ts. E asy me m or y expansion is provided by an active LOW Chip Enable (CE
) and
active LOW Output Enable (OE
) and three-state drivers. The
device has an automatic power-down feature, reducing the
power consumption by more than 95% when deselected.
An active LOW Write Enab le signal (WE
) controls the writing/
reading operation of the memor y . When CE and WE inputs are
both LOW, data on the eight data input/output pins (I/O
0
through I/O7) is written into the memory locati on addressed by
the address present on the address pins (A0 through A14).
Reading th e device is ac complished by selectin g the device
and enabling the outputs, CE
and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address
pins is present on the eight data input/output pins.
The input/output pi ns remain in a hig h-impedance sta te unless
the chip is selected, outputs are enabled, and Write Enable
(WE
) is HIGH. The CY7C1399B is availab le in 28-pin standard
300-mil-wide SOJ and TSOP Type I packages.
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
SOJ
12
13
25
28
27
26
GND
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
WE
V
CC
A
4
A
3
A
2
A
1
I/O
7
I/O
6
I/O
5
I/O
4
A
14
A
5
I/O
0
I/O
1
I/O
2
CE
OE
A
0
I/O
3
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
32K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
9
A
0
A
11A13A12
A
14
A
10
Selection Guide
1399B-10 1399B-12 1399B-15 1399B-20
Maximum Access Time (ns) 10 12 15 20
Maximum Operating Current (mA) 60 55 50 45
Maximum CMOS Standby Current (µA) 500 500 500 500
L50
50 50 50
CY7C1399B
Document #: 38-05071 Rev. *A Page 2 of 10
Maximum Ratings
(Above which the useful life may be im pai red. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
....–0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to VCC + 0.5V
DC Input Voltage
[1]
................................–0.5V to VCC + 0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Pin Configuration
22
23
24
25
26
27
28
1
2
5
10
11
15
14
13
12
16
19
18
17
Top View
TSOP
3
4
20
21
7
6
8
9
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A7
A
8
A
9
A
0
CE
I/O
7
I/O
6
I/O
5
GND
I/O
2
I/O
1
I/O
4
I/O
0
A
14
A
10
A
11
A
13
A
12
I/O
3
Operating Range
Range
Ambient
Temperature V
CC
Commercial 0°C to +70°C 3.3V ±300 mV
Industrial –40°C to +85°C 3.3V ±300 mV
Electrical Characteristics Ov er the Op erat ing Range
[1]
7C1399B-10 7C1399B-12
Parameter Description Test Conditions Min. Max. Min. Max. Unit
V
OH
Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 2.4 V
V
OL
Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 V
CC
+0.3V
2.2 V
CC
+0.3V
V
V
IL
Input LOW Voltage –0.3 0.8 –0.3 0.8 V
I
IX
Input Load Current –1+1–1 +1 µA
I
OZ
Output Leakage
Current
GND ≤ VI ≤ VCC,
Output Dis abled
–5+5–5 +5 µA
I
OS
Output Short
Circuit Current
[2]
VCC = Max., V
OUT
= GND –300 –300 mA
I
CC
VCC Operatin g
Supply Current
VCC = Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
60 55 mA
I
SB1
Automatic CE Power-Down
Current — TTL Inputs
Max. VCC, CE ≥ VIH,
V
IN
≥ VIH, or V
IN
≤ VIL,f = f
MAX
5 5 mA
L44 mA
I
SB2
Automatic CE Power-Down
Current — CMOS Inputs
[3]
Max. VCC, CE ≥ V
CC
– 0.3V , VIN ≥ VCC
– 0.3V , or V
IN
≤ 0.3V ,
WE ≥V
CC
– 0.3V or WE ≤0.3V, f= f
MAX
500 500 µA
L5050 µA
Notes:
1. Minimum voltage is equal to –2.0V for pulse durations of less than 20 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. Device draws low standby current regardless of switching on the addresses.
CY7C1399B
Document #: 38-05071 Rev. *A Page 3 of 10
Electrical Characteristics Over the Operating Range (continued)
1399B-15 1399B-20
Parameter Description Test Conditions Min. Max. Min. Max. Unit
V
OH
Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 2.4 V
V
OL
Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 V
CC
+0.3V
2.2 V
CC
+0.3V
V
V
IL
Input LOW Voltage –0.3 0.8 –0.3 0.8 V
I
IX
Input Load Current –1 +1 –1 +1 µA
I
OZ
Output Leakage Current GND ≤ VI ≤ VCC,
Output Disabled
–5 +5 –5 +5 µA
I
OS
Output Short Circuit
Current
[2]
VCC = Max., V
OUT
= GND –300 –300 mA
I
CC
VCC Operating
Supply Current
VCC = Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
50 45 mA
I
SB1
Automatic CE Power-Down
Current — TTL Inputs
Max. VCC, CE ≥ VIH,
V
IN
≥ VIH, or V
IN
≤ VIL,
f = f
MAX
5 5 mA
L 4 4 mA
I
SB2
Automatic CE Power-Down
Current — CMOS Inputs
[3]
Max. VCC, CE ≥ VCC–0.3V , VIN ≥
V
CC
– 0.3V , or VIN ≤ 0. 3V,
WE≥V
CC
–0.3V or WE≤ 0.3V,
f=f
MAX
500 500 µA
L 50 50 µA
Capacitance
[4]
Parameter Description Test Conditions Max. Unit
CIN: Address es Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 5 pF
CIN: Controls 6 pF
C
OUT
Output Capacitance 6 pF
AC Test Loads and Waveforms
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
3.0V
3.3V
OUTPUT
R1 317
Ω
R2
351
Ω
C
L
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤ 3ns
≤ 3 ns
OUTPUT 1.73V
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
167
Ω
CY7C1399B
Document #: 38-05071 Rev. *A Page 4 of 10
Switching Characteristics O ver the Operating Range
[5]
1399B–10 1399B–12
Parameter Description Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Read Cycle Time 10 12 ns
t
AA
Address to Data Valid 10 12 ns
t
OHA
Data Hold from Address Change 3 3 ns
t
ACE
CE LOW to Data Valid 10 12 ns
t
DOE
OE LOW to Data Valid 5 5 ns
t
LZOE
OE LOW to Low Z
[6]
00ns
t
HZOE
OE HIGH to High Z
[6, 7]
55ns
t
LZCE
CE LOW to Low Z
[6]
33ns
t
HZCE
CE HIGH to High Z
[6, 7]
56ns
t
PU
CE LOW to Power-Up 0 0 ns
t
PD
CE HIGH to Power-Down 10 12 ns
WRITE CYCLE
[8, 9]
t
WC
Write Cycle Time 10 12 ns
t
SCE
CE LOW to Write End 8 8 ns
t
AW
Address Set-Up to Write End 7 8 ns
t
HA
Address Hold from Write End 0 0 ns
t
SA
Address Set-Up to Write Start 0 0 ns
t
PWE
WE Pulse Width 7 8 ns
t
SD
Data Set-Up to Write End 5 7 ns
t
HD
Data Hold from Write End 0 0 ns
t
HZWE
WE LOW to High Z
[8]
77ns
t
LZWE
WE HIGH to Low Z
[6]
33ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL/IOH
and capacitance CL = 30 pF .
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZCE
, t
HZWE
are specified wi th CL = 5 pF as in AC T est Loads. T ransit ion is measured ±50 0 mV from steady state vo ltage.
8. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW . Bot h signals must be L OW to initi ate a writ e and eit her signal can terminat e
a write by going HIGH. The data input set -up and hold timing sho uld be referenced to the rising edge of the sign al that termin ates the write.
9. The minimum write cycle time for write cycle #3 (WE
controlled, OE LOW) is the sum of t
HZWE
and tSD.
CY7C1399B
Document #: 38-05071 Rev. *A Page 5 of 10
Switching Characteristics O ver the Operating Range
[5]
(Continued)
1399B–15 1399B–20
Parameter Description Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Read Cycle Time 15 20 ns
t
AA
Address to Data Valid 15 20 ns
t
OHA
Data Hold from Address Change 3 3 ns
t
ACE
CE LOW to Data Valid 15 20 ns
t
DOE
OE LOW to Data Valid 6 7 ns
t
LZOE
OE LOW to Low Z
[6]
0 0 ns
t
HZOE
OE HIGH to High Z
[6, 7]
6 6 ns
t
LZCE
CE LOW to Low Z
[6]
3 3 ns
t
HZCE
CE HIGH to High Z
[6, 7]
7 7 ns
t
PU
CE LOW to Power-Up 0 0 ns
t
PD
CE HIGH to Power-Down 15 20 ns
WRITE CYCLE
[8, 9]
t
WC
Write Cycle Time 15 20 ns
t
SCE
CE LOW to Write End 10 12 ns
t
AW
Address Set-Up to Write End 10 12 ns
t
HA
Address Hold from Write End 0 0 ns
t
SA
Address Set-Up to Write Start 0 0 ns
t
PWE
WE Pulse Width 10 12 ns
t
SD
Data Set-Up to Write End 8 10 ns
t
HD
Data Hold from Write End 0 0 ns
t
HZWE
WE LOW to High Z
[8]
7 7 ns
t
LZWE
WE HIGH to Low Z
[6]
3 3 ns
Data Retention Characteristics (Over the Operating Range - L version only)
Parameter Description Conditions Min. Max. Unit
V
DR
VCC for Data Retention 2.0 V
I
CCDR
Data Retention Current Com’l VCC = VDR = 2.0V ,
CE > VCC – 0.3V ,
V
IN
> VCC – 0.3V or
V
IN
< 0.3V
0 20 uA
t
CDR
Chip Deselect to Data
Retention Time
0 ns
t
R
Operation Recovery Time t
RC
ns
CY7C1399B
Document #: 38-05071 Rev. *A Page 6 of 10
Data Retention Waveform
3.0V3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
Switching Waveforms
Notes:
10. Device is continuously selected. OE
, CE = VIL.
11. WE
is HIGH for read cycle .
12. Address valid prior to or coi ncident with CE
transition LOW .
ADDRESS
DATA OUT PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
Read Cycle No. 1
[10, 11]
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
Read Cycle No. 2
[11, 12 ]
CY7C1399B
Document #: 38-05071 Rev. *A Page 7 of 10
Notes:
13. Data I/O is high impedance if OE
= VIH.
14. If C E
goes HIGH simultaneousl y with WE HIGH, the ou tput r emains in a hi gh-impeda nce s tate.
15. During this period, the I/Os are in the output state and input signals should not be applied.
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
DATA I/O
ADDRESS
CE
WE
OE
t
HZOE
DATAINVALID
Write Cycle No. 1 (WE Controlled)
[8, 13, 14]
NOTE 15
t
WC
t
AW
t
SA
t
HA
t
HD
t
SD
t
SCE
WE
DATA I/O
ADDRESS
CE
DATAINVALID
Write Cycle No. 2 (C E Controlle d)
[8, 13, 14]
DATA I/O
ADDRESS
t
HD
t
SD
t
LZWE
t
SA
t
HA
t
AW
t
WC
CE
WE
t
HZWE
DATAINVALID
Write Cycle No. 3 (WE Controlled, OE LOW)
[9, 14]
NOTE 15
CY7C1399B
Document #: 38-05071 Rev. *A Page 8 of 10
Truth Table
CE WE OE Input/Output Mode Power
H X X High Z Deselect/Power-Down Standby (ISB)
L H L Data Out Read Active (ICC)
L L X Data In Write Active (ICC)
L H H High Z Deselect, Output Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
10 CY7C1399B-10VC V21 28-Lead Molded SOJ Commercial
CY7C1399B-10ZC Z28 28-Lead Thin Small Outline Package
CY7C1399BL-10VC V21
28-Lead Molded SOJ
CY7C1399BL-10ZC Z28 28-Lead Thin Small Outline Package
12 CY7C1399B–12V C V21 28-Lead Molded SOJ
CY7C1399B–12ZC Z28 28-Lead Thin Small Outline Package
CY7C1399BL-12VC V21 28-Lead Molded SOJ
CY7C1399BL-12ZC Z28 28-Lead Thin Small Outline Package
CY7C1399B–12VI V21 28-Lead Mo lde d SOJ Industrial
CY7C1399B–12ZI Z28 28-Lead Thin Small Outline Package
15 CY7C1399B–15VC V21 28-Lead Molded SOJ Commercial
CY7C1399B–15ZC Z28 28-Lead Thin Small Outline Package
CY7C1399BL-15VC V21 28-Lead Molded SOJ
CY7C1399BL-15ZC Z28 28-Lead Thin Small Outline Package
CY7C1399B–15VI V21 28-Lead Molded SOJ Industrial
CY7C1399B–15ZI Z28 28-Lead Thin Small Outline Package
20 CY7C1399B–20VC V21 28-Lead Molded SOJ Commercial
CY7C1399B–20ZC Z28 28-Lead Thin Small Outline Package
CY7C1399BL-20VC V21 28-Lead Molded SOJ
CY7C1399BL-20ZC Z28 28-Lead Thin Small Outline Package
CY7C1399B–20VI V21 28-Lead Molded SOJ Industrial
CY7C1399B–20ZI Z28 28-Lead Thin Small Outline Package
CY7C1399B
Document #: 38-05071 Rev. *A Page 9 of 10
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. No r does it convey or imply any license under patent or other rights. Cypress Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
28-Lead Thin Small Outline Package Type 1 (8x13.4 mm) Z28
51-85071-*G
CY7C1399B
Document #: 38-05071 Rev. *A Page 10 of 10
Revision History
Document Title: CY7C1399B 32K x 8 3.3V Static RAM
Document Number: 38-05071
REV. ECN NO. ISSUE DATE
ORIG. OF
CHANGE DESCRIPTION OF CHANGE
** 107264 05/25/01 SZV Change from Spec #: 38-01102 to 38-05071
*A 107533 06/28/01 MAX Add Low Power
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