Cypress Semiconductor CY7C1386DV25, CY7C1387DV25, CY7C1386FV25, CY7C1387FV25 Specification Sheet

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200, and 167 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

• Depth expansion without wait state

•2.5V +

• Fast clock-to-output times, 2.6 ns (for 250 MHz device)

• Provides high-performance 3-1-1-1 access rate

• User selectable burst counter supporting Intel

• Separate processor and controller address strobes

• Synchronous self timed writes

• Asynchronous output enable

• CY7C1386DV25/CY7C1387DV25 available in

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• ZZ sleep mode option

5% power supply (VDD)

®

Pentium®

interleaved or linear burst sequences

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 165-ball FBGA package.
CY7C1386FV25/CY7C1387FV25 available in Pb-free and
non Pb-free 119-ball BGA package

Functional Description

[1]

The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 SRAM integrates 512K x 36 and 1M x 18
SRAM cells with advanced synchronous peripheral circuitry
and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive edge triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
chip enable (CE

[2]

), burst control inputs (ADSC, ADSP, and ADV), write

CE

3

enables (BW
Asynchronous inputs include the output enable (OE

), depth expansion chip enables (CE2 and

1

, and BWE), and global write (GW).

X

) and the

ZZ pin.

Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP
address strobe controller (ADSC

) are active. Subsequent

) or

burst addresses can be internally generated as controlled by
the advance pin (ADV).

Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see Pin Definitions on page 6 and Truth Table

5, 6, 7, 8, 9]

on page 9 for further details). Write cycles can be

one to four bytes wide as controlled by the byte write control
inputs. GW

active

causes all bytes to be written.

LOW

This
device incorporates an additional pipelined enable register
which delays turning off the output buffers an additional cycle
when a deselect is executed.This feature allows depth
expansion without penalizing system performance.

The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 operates from a +2.5V power supply. All
inputs and outputs are JEDEC-standard and
JESD8-5-compatible.

[4,

Selection Guide

Maximum Access Time 2.6 3.0 3.4 ns

Maximum Operating Current 350 300 275 mA

Maximum CMOS Standby Current 70 70 70 mA

Notes

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05548 Rev. *E Revised Feburary 15, 2007

are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.

3, CE2

250 MHz 200 MHz 167 MHz Unit

[+] Feedback

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

Logic Block Diagram – CY7C1386DV25/CY7C1386FV25

DQD,DQP

BYTE

DQc,DQP

BYTE

DQB,DQP

BYTE

DQA,DQP

BYTE

ENABLE

REGISTER

CONTROL

ADDRESS
REGISTER

D

C

B

A

2

BURST

COUNTER AND

LOGIC

CLR

PIPELINED

ENABLE

A[1:0]

Q1

Q0

DQD,DQP

D

BYTE

WRITE DRIVER

DQc,DQP

C

BYTE

WRITE DRIVER

DQB,DQP

B

BYTE

WRITE DRIVER

DQA,DQP

A

BYTE

WRITE DRIVER

A0,A1,A

MODE

ADV

CLK

ADSC

ADSP

BW

BW

BW

BW

BWE

GW

D

C

B

A

CE

1

CE

2

CE

3

OE

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

ZZ

[3]

(512K x 36)

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQs
DQP
DQP
DQP

DQP

A

B

C

D

Logic Block Diagram – CY7C1387DV25/CY7C1387FV25

A0, A1, A

MODE

ADV

CLK

ADSC

ADSP

BW

BW

BWE

B

A

CE

1

CE

2

CE

3

OE

ADDRESS
REGISTER

DQB,DQP

B

BYTE

WRITE REGISTER

A ,

DQ

DQP

BYTE

WRITE REGISTER

ENABLE

REGISTER

SLEEP

CONTROL

2

BURST

COUNTER AND

CLR

PIPELINED

ENABLE

[1:0]

A

Q1

Q0

DQ

B ,

DQP

B

BYTE

DQA,DQP

A

BYTE

[3]

(1M x 18)

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQ
DQP
DQP

s,

A

B

Note

3. CY7C1386FV25 and CY7C1387FV25 have only 1 chip enable (CE

Document Number: 38-05548 Rev. *E Page 2 of 30

).

1

[+] Feedback

Pin Configurations

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

100-pin TQFP Pinout (3 Chip Enables)

DQP
DQ
DQ

V

V

DQ
DQ
DQ
DQ

V

V

DQ
DQ

DQ
DQ

V

V

DQ
DQ
DQ
DQ

V

V

DQ
DQ
DQP

DDQ

SSQ

SSQ

DDQ

V

V

DDQ

SSQ

SSQ

DDQ

NC

NC

1CE2

A

A

CE

100999897969594939291908988878685848382

C

1

C

2

C

3
4
5

C

6

C

7

C

8

C

9
10
11

C

12

C

13
14

DD

15
16

SS

17

D

18

D

19
20
21

D

22

D

23

D

24

D

25
26
27

D

28

D

29

D

30

31323334353637383940414243444546474849

AAA

MODE

A

BWDBWCBWBBW

CE3VDDV

CY7C1386DV25

(512K X 36)

1A0

A

A

SS

V

NC/72M

NC/36M

SS

CLKGWBWEOEADSC

A

A

AAAAA

DD

V

ADSP

ADV

A

A

81

DQP

80

DQ

79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ
DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
DQP

B

B

B

B

B

B

B

B

A

A

A

A

A

A

A

A

NC

B

NC
NC

V

DDQ

V

SSQ

NC
NC

DQ

B

DQ

B

V

SSQ

V

DDQ

DQ

B

DQ

B

NC

V

DD

NC

V

SS

DQ

B

DQ

B

V

DDQ

V

SSQ

DQ

B

DQ

B

DQP

B

NC

V

SSQ

V

DDQ

NC
NC
NC

A

50

A

A

1CE2

A

A

NCNCBWBBWA

CE

100999897969594939291908988878685848382

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CY7C1387DV25

31323334353637383940414243444546474849

AAA

1A0

A

A

MODE

SS

CE3VDDV

(1M x 18)

SS

DD

V

V

NC/72M

NC/36M

CLKGWBWEOEADSC

A

A

ADSP

AAAAA

ADV

A

A

81

A

80

NC

79

NC

78

V

77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DDQ

V

SSQ

NC
DQP
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ
DQ
V

DDQ

V

SSQ

DQ
DQ
NC
NC
V

SSQ

V

DDQ

NC
NC
NC

A

A

A

A

A

A

A

A

A

50

A

A

Document Number: 38-05548 Rev. *E Page 3 of 30

[+] Feedback

Pin Configurations (continued)

V

A

NC/288M

B

NC/144M

C

D

G
H

K

M

N

R

U

DQ

DQ

E

V

F

DQ
DQ

V

J

DQ

DQ

L

V

DQ

DQ

P

NC

T

NC

V

DDQ

DDQ

DDQ

DDQ

DDQ

119-Ball BGA (1 Chip Enable)

CY7C1386FV25 (512K x 36)

2345671

AA AA

A

A

AA

DQP

C

DQ

C

DQ

DQ

C

DQ

C

V

DD

DQ

D

DQ

D

DQ

DQ

D

DQP

D

A

V

C

C

C

C

C

V

V

BW

V

SS

SS

SS

SS

NC V

V

BW

V

V

V

SS

SS

SS

SS

D

D

D

D

D

MODE

AAA

ADSP

ADSC

V

NC

CE

OE

ADV

C

GW

CLK

D

NC

BWE

V

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

V

DDQ

NC/576M

DQP

DQ

DQ

DQ
DQ

DQ

DQ

DQ

DQ

DQP

NC/36MNC/72M

V

NC

A

AA

DD

A

NC/1G

DQ

DQ

V

DQ
DQ

V

DQ

DQ

V

DQ

DQ

B

B

DDQ

B

B

DDQ

A

A

DDQ

A

A

B

B

B

B

B

A

A

A

A

A

NC

ZZ

V

DDQ

A1

A0

DD

DD

DD

A

V

SS

V

1

V

BW

V

SS

SS

B

SS

NC

V

SS

BW

A

V

SS

V

SS

V

SS

NC

TDOTCKTDITMS

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

DDQ

NC/288M

NC/144M

B

NC

V

DDQ

NC

DQ

B

V

DDQ

NC

DQ

B

V

DDQ

DQ

B

NC

NC

NC/72M

V

DDQ

CY7C1387FV25 (1M x 18)

2

AA AA

A

NCDQ

DQ

B

NC

DQ

B

NC

V

DD

DQ

B

NC

DQ

B

NC

DQP

B

A

345671

ADSP

A

AA

V

SS

V

SS

V

SS

BW

V

SS

NC V

V

SS

NC

V

SS

V

SS

V

SS

MODE

ADSC

V

DD

NC

CE

1

OE

ADV

B

GW

DD

CLK

NC

BWE

A1

A0

V

DD

A NC/36M A

V

V

V

NC

V

NC

V

BW

V

V

V

NC

TDOTCKTDITMS

A

SS

SS

SS

SS

SS

SS

SS

SS

A

AA

DQP

A

NC

DQ

A

NC

DQ

A

V

DD

NC

DQ

A

A

NC

DQ

A

NC

A

AA

NC

V

DDQ

NC/576M

NC/1G

NC

DQ

A

V

DDQ

DQ

A

NC

V

DDQ

DQ

A

NC

V

DDQ

NC

DQ

A

NC

ZZ

V

DDQ

Document Number: 38-05548 Rev. *E Page 4 of 30

[+] Feedback

Pin Configurations (continued)

234 5671

NC/288M

A

B
C
D

E
F
G

H

J
K
L

M

N
P

R

NC/144M

DQP

C

DQ

C

DQ

C

DQ

C

DQ

C

NC

DQ

D

DQ

D

DQ

D

DQ

D

DQP

D

NC

MODE

A

A

NC

DQ

DQ

DQ

DQ

NC

DQ

DQ

DQ

DQ

NC

NC/72M

NC/36M

CE

CE

V

DDQ

V

C

C

C

C

V

V

V

DDQ

DDQ

DDQ

DDQ

NC

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

D

D

D

D

A

A

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

165-Ball FBGA Pinout (3 Chip Enable)

CY7C1386DV25 (512K x 36)

BW

1

BW

2

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

BW

C

BW

D

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

CE

B

CLK

A

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A

A1

A0

BWE

3

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCK

891011

ADSC

ADV

OE ADSP

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

V

V

V

V

V

V

V

V

V

A

A

DDQ

DDQ

DDQ

DDQ

DDQ

NC

DDQ

DDQ

DDQ

DDQ

DDQ

A

A

A

A

NC/1G DQP

DQ

B

DQ

B

DQ

B

DQ

B

NC

DQ

A

DQ

A

DQ

A

DQ

A

NC

A

NC

NC/576M

B

DQ

B

DQ

B

DQ

B

DQ

B

ZZ

DQ

A

DQ

A

DQ

A

DQ

A

DQP

A

A

AA

A

B
C
D

E

F
G
H

J
K

L
M

N

P

R

CY7C1387DV25 (1M x 18)

234 5671

NC/288M

NC/144M

NC

NC

NC V

NC

NC
NC

DQ

B

DQ

B

DQ

B

DQ

B

DQP

B

NC

MODE

A

A

NC

DQ

B

DQ

B

DQ

B

DQ

B

NC

NC

NC

NC

NC

NC

NC/72M

NC/36M

CE
CE

V

V

V

V

V

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

NC

DDQ

DDQ

DDQ

DDQ

DDQ

A

A

BW

1

2

B

NC BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

NC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

‘V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

A

CE

CLK

V

SS

V

SS

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A

A1

891011

BWE

3

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCKA0

ADSC

OE ADSP

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

DD

V

DD

V

SS

A

A

ADV

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

A

A

NC/1G DQP

NC

NC

NC

NC
NC

DQ

A

DQ

A

DQ

A

DQ

A

NC

A

A

NC/576M

DQ

A

DQ

A

DQ

A

DQ

A

ZZ

NCV

NC

NC

NC

NC

A

AA

A

Document Number: 38-05548 Rev. *E Page 5 of 30

[+] Feedback

Pin Definitions

Name IO Description

, A1, A Input-

A

0

BW

, BW

A

BWC, BW

B

D

GW Input-

BWE

CLK Input-

CE

1

[2]

CE

2

[2]

CE

3

OE Input-

ADV Input-

ADSP Input-

ADSC

ZZ Input-

DQs, DQPs

V

DD

Synchronous

Input-

Synchronous

Synchronous

Input-

Synchronous

Clock

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Asynchronous

Synchronous

Synchronous

Input-

Synchronous

Asynchronous

IO-

Synchronous

Power Supply Power supply inputs to the core of the device.

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

Address inputs used to select one of the address locations. Sampled at the

rising edge of the CLK if ADSP
are sampled active. A1: A0 are fed to the two-bit counter.

or ADSC is active LOW, and CE1, CE2, and CE

.

Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.

Global write enable input, active LOW. When asserted LOW on the rising edge
of CLK, a global write is conducted (all bytes are written, regardless of the values
on BW

and BWE).

X

Byte write enable input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.

Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV

is asserted LOW, during a burst operation.

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
if CE

is HIGH. CE1 is sampled only when a new external address is loaded.

1

and CE

2

[2]

to select or deselect the device. ADSP is ignored

3

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE

and CE

1

[2]

to select or deselect the device. CE2 is sampled

3

only when a new external address is loaded.

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
BGA. Where referenced, CE

and CE2 to select or deselect the device. Not connected for

1

[2]

is assumed active throughout this document for

3

BGA. CE3 is sampled only when a new external address is loaded.

Output enable, asynchronous input, active LOW. Controls the direction of the
IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, DQ
pins are tri-stated, and act as input data pins. OE

is masked during the first clock

of a read cycle when emerging from a deselected state.

Advance input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.

Address strobe from processor, sampled on the rising edge of CLK, active
LOW. When asserted LOW, addresses presented to the device are captured in the

address registers. A1: A0 are also loaded into the burst counter. When ADSP
ADSC

are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is

deasserted HIGH.

Address strobe from controller, sampled on the rising edge of CLK, active
LOW. When asserted LOW, addresses presented to the device are captured in the

address registers. A1: A0 are also loaded into the burst counter. When ADSP
ADSC

are both asserted, only ADSP is recognized.

ZZ sleep input, active HIGH. When asserted HIGH places the device in a
non-time-critical sleep condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull down.

Bidirectional data IO lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE

. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are
placed in a tri-state condition.

3

and

and

[2]

Document Number: 38-05548 Rev. *E Page 6 of 30

[+] Feedback

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

Pin Definitions (continued)

Name IO Description

V

SS

V

SSQ

V

DDQ

MODE Input-

TDO JTAG serial output

TDI JTAG serial input

TMS JTAG serial input

TCK JTAG-

NC – No Connects. Not internally connected to the die

NC/(36M, 72M, 144M,
288M, 576M, 1G)

Ground Ground for the core of the device.

IO Ground Ground for the IO circuitry.

IO Power Supply Power supply for the IO circuitry.

Selects burst order. When tied to GND selects linear burst sequence. When tied

Stat ic

to VDD or left floating selects interleaved burst sequence. This is a strap pin and
must remain static during device operation. Mode pin has an internal pull up.

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

Synchronous

If the JTAG feature is not used, this pin must be disconnected. This pin is not
available on TQFP packages.

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

Synchronous

feature is not used, this pin can be disconnected or connected to V
not available on TQFP packages.

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

Synchronous

feature is not used, this pin can be disconnected or connected to V
not available on TQFP packages.

Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must

Clock

be connected to V

. This pin is not available on TQFP packages.

SS

– These pins are not connected. They will be used for expansion to the 36M, 72M,

144M, 288M, 576M, and 1G densities.

. This pin is

DD

. This pin is

DD

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.

The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 supports secondary cache in systems using
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium
linear burst sequence is suited for processors that use a linear
burst sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can
initiated with either the processor address strobe (ADSP)
the controller address strobe (ADSC
through the burst sequence is controlled by the ADV
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.

Byte write operations are qualified with the byte write enable

) and byte write select (BWX) inputs. A global write

(BWE
enable (GW

) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self timed write circuitry.

Synchronous chip selects CE
asynchronous output enable (OE) provide for easy bank
selection and

output tri-state control.

is HIGH.

®

and i486™ processors. The

). Address advancement

input. A

, CE2, CE

1

ADSP

[2]

and an

3

is ignored if CE

be

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP

or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the address
register while being presented to the memory core. The
corresponding data is allowed to propagate to the input of the
output registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within t
occurs when the SRAM is emerging from a deselected state

or

if OE is active LOW. The only exception

CO

to a selected state, its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE

signal. Consecutive single

read cycles are supported.

The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 is a double-cycle deselect part. Once the
SRAM is deselected at clock rise by the chip select and either

or ADSC signals, its output will tri-state immediately

ADSP
after the next clock rise.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP

1

chip select is asserted active. The address presented is

is asserted LOW, and (2)

loaded into the address register and the address
advancement logic while being delivered to the memory core.

1

Document Number: 38-05548 Rev. *E Page 7 of 30

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The write signals (GW
ignored during this first cycle.

triggered write accesses require two clock cycles to

ADSP

, BWE, and

) and ADV inputs are

BW

X

complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ
corresponding address location in the memory core. If GW

inputs is written into the

x

is
HIGH, then the write operation is controlled by BWE and BW
signals.

The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 provides byte write capability that is
described in the write cycle description table. Asserting the
byte write enable input (BWE

) with the selected byte write
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self timed write mechanism has been provided
to simplify the write operations.

The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 is a common IO device, the output enable

) must be deasserted HIGH before presenting data to the

(OE

inputs. Doing so will tri-state the output drivers. As a safety

DQ
precaution, DQ are automatically tri-stated whenever a write
cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following
conditions are satisfied: (1) ADSC

is asserted LOW, (2) ADSP
is deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and
byte(s). ADSC triggered write accesses require a single clock

) are asserted active to conduct a write to the desired

BW

X

cycle to complete. The address presented is loaded into the
address register and the address advancement logic while
being delivered to the memory core. The ADV

input is ignored
during this cycle. If a global write is conducted, the data
presented to the DQ

is written into the corresponding address

X

location in the memory core. If a byte write is conducted, only
the selected bytes are written. Bytes not selected during a byte
write operation will remain unaltered. A synchronous self
timed write mechanism has been provided to simplify the write
operations.

The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 is a common IO device, the output enable

) must be deasserted HIGH before presenting data to the

(OE

inputs. Doing so will tri-state the output drivers. As a

DQ

X

safety precaution, DQ

are automatically tri-stated whenever

X

a write cycle is detected, regardless of the state of OE.

Burst Sequences

The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 provides a two-bit wraparound counter, fed
by A

, that implements either an interleaved or linear burst

[1:0]

sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow

X

a linear burst sequence. The burst sequence is user selectable
through the MODE input.

Asserting ADV

LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the sleep mode. CE
for the duration of t

s, ADSP, and ADSC must remain inactive

after the ZZ input returns LOW

ZZREC

Interleaved Burst Address Table
(MODE = Floating or VDD)

First

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Second

Address

A1: A0

Third

Address

A1: A0

Linear Burst Address Table (MODE = GND)

First

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

Second

Address

A1: A0

Third

Address

A1: A0

.

Fourth

Address

A1: A0

Fourth

Address

A1: A0

Document Number: 38-05548 Rev. *E Page 8 of 30

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ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Truth Table

Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State

Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State

Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State

Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State

Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State

Sleep Mode, Power Down None X X X H X X X X X X Tri-State

READ Cycle, Begin Burst External L H L L L X X X L L-H Q

READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-State

WRITE Cycle, Begin Burst External L H L L H L X L X L-H D

READ Cycle, Begin Burst External L H L L H L X H L L-H Q

READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State

READ Cycle, Continue Burst Next X X X L H H L H L L-H Q

READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State

READ Cycle, Continue Burst Next H X X L X H L H L L-H Q

READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State

WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D

WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D

READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q

READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State

READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q

READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State

WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D

WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D

Sleep mode standby current ZZ > VDD – 0.2V 80 mA

Device operation to ZZ ZZ > VDD – 0.2V 2t

ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ Active to sleep current This parameter is sampled 2t

CYC

CYC

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

[4, 5, 6, 7, 8, 9]

ns

ns

ns

Notes

4. X = Don't Care, H = Logic HIGH, L = Logic LOW.

5. WRITE

6. The DQ pins are controlled by the current cycle and the

7. CE

8. The SRAM always initiates a read cycle when ADSP

9. OE

= L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.

, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.

1

the ADSP
care for the remainder of the write cycle.

inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is

Document Number: 38-05548 Rev. *E Page 9 of 30

signal. OE is asynchronous and is not sampled with the clock.

OE

is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after

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Partial Truth Table for Read/Write

Function (CY7C1386DV25/CY7C1386FV25) GW BWE BW

[5, 10]

D

BW

C

BW

B

BW

A

Read HHXXXX

Read HLHHHH

Write Byte A – (DQ

Write Byte B – (DQ

and DQPA) H L HHHL

A

and DQPB)HLHHLH

B

Write Bytes B, A H L H H L L

Write Byte C – (DQ

and DQPC) HLHLHH

C

Write Bytes C, A H L H L H L

Write Bytes C, B H L H L L H

Write Bytes C, B, A H L H L L L

Write Byte D – (DQ

and DQPD) HL LHHH

D

Write Bytes D, A H L L H H L

Write Bytes D, B H L L H L H

Write Bytes D, B, A H L L H L L

Write Bytes D, C H L L L H H

Write Bytes D, C, A H L L L H L

Write Bytes D, C, B HLLLLH

Write All Bytes HLLLLL

Write All Bytes LXXXXX

Truth Table for Read/Write

Function (CY7C1387DV25/CY7C1387FV25) GW BWE BW

[5, 10]

B

BW

Read H H X X

Read H L H H

Write Byte A – (DQ

Write Byte B – (DQ

and DQPA)HLHL

A

and DQPB)HLLH

B

Write All Bytes H L L L

Write All Bytes L X X X

A

Note

10. Table only lists a partial listing of the byte write combinations. Any combination of BW

Document Number: 38-05548 Rev. *E Page 10 of 30

is valid appropriate write will be done based on which byte write is active.

X

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Bypass Register

0

Instruction Register

012

Identification Register

012293031 ...

Boundary Scan Register

012..x ...

S

election

Circuitr

y

Selection

Circuitry

TCK

TMS

TAP CONTROLLER

TDI TDO

CY7C1387DV25, CY7C1387FV25

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 incorporates a serial boundary scan test
access port (TAP).This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 3.3V or 2.5V IO logic
levels.

The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW

) to prevent clocking of the device. TDI and TMS are

(V

SS

internally pulled up and may be unconnected. They may
alternately be connected to V

through a pull up resistor.

DD

TDO should be left unconnected. Upon power up, the device
will come up in a reset state which will not interfere with the
operation of the device.

TAP Controller State Diagram

TEST-LOGIC

1

RESET

0

IDLE

1

SELECT

DR-SCAN

1 1

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

0 0

EXIT2-DR

UPDATE-DR

1 0

0

RUN-TEST/

The 0 or 1 next to each state represents the value of TMS at
the rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left

1

0

0

0 0

1

1 1

0 0

0

1

1

SELECT

IR-SCAN

0

CAPTURE-IR

0

SHIFT-IR

1

EXIT1-IR

PAUSE-IR

1

EXIT2-IR

1

UPDATE-IR

1

0

unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See TAP Controller Block Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See TAP Controller State Diagram.)

TAP Controller Block Diagram

1

0

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (V
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.

At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.

) for five

DD

Document Number: 38-05548 Rev. *E Page 11 of 30

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Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the TAP Controller Block

Diagram. Upon power up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.

When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary ‘01’ pattern to
allow for fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW

) when the BYPASS instruction is executed.

(V

SS

Boundary Scan Register

The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO balls when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z
instructions can be used to capture the contents of the input
and output ring.

The boundary scan order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register

Definitions on page 15.

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Identification

Codes on page 15. Three of these instructions are listed as

RESERVED and should not be used. The other five
instructions are described in detail below.

Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.

To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.

EXTEST

The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the Shift-DR controller
state.

IDCODE

The IDCODE instruction causes a vendor specific 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command
places all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is
captured in the boundary scan register.

The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. As there is
a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus
hold times (t
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK
boundary scan register.

Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells pri­or to the selection of another boundary scan test operation.

and tCH). The SRAM clock input might not be

CS

captured in the

Document Number: 38-05548 Rev. *E Page 12 of 30

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The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required; that is, while data
captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.

EXTEST Output Bus Tri-State

IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-fBGA package).
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in

TAP Timing

123456

Test Clock

(TCK)

t

TMSS

t

t

TH

TMSH

t

the TAP controller, it will directly control the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it will enable the output buffers to
drive the output bus. When LOW, this bit will place the output
bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the Shift-DR state. During Update-DR, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is powered
up, and also when the TAP controller is in the Test-Logic-Reset
state.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

t

TL

CYC

Test Mode Select

(TMS)

Test Data-In

Test Data-Out

(TDO)

(TDI)

t

TDIS

t

TDIH

DON’T CARE UNDEFINED

t

TDOX

t

TDOV

Document Number: 38-05548 Rev. *E Page 13 of 30

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TAP AC Switching Characteristics

Over the Operating Range

Parameter Description Min. Max. Unit

Clock

t

TCYC

t

TF

t

TH

t

TL

TCK Clock Cycle Time 50 ns

TCK Clock Frequency 20 MHz

TCK Clock HIGH time 20 ns

TCK Clock LOW time 20 ns

Output Times

t

TDOV

t

TDOX

TCK Clock LOW to TDO Valid 10 ns

TCK Clock LOW to TDO Invalid 0 ns

Setup Times

t

TMSS

t

TDIS

t

CS

TMS Setup to TCK Clock Rise 5 ns

TDI Setup to TCK Clock Rise 5 ns

Capture Setup to TCK Rise 5 ns

Hold Times

t

TMSH

t

TDIH

t

CH

TMS Hold after TCK Clock Rise 5 ns

TDI Hold after Clock Rise 5 ns

Capture Hold after Clock Rise 5 ns

[11, 12]

TAP AC Test Conditions

Input pulse levels .................................................VSS to 2.5V

TAP AC Output Load Equivalent

1.25V

Input rise and fall time..................................................... 1 ns

Input timing reference levels.........................................1.25V

Output reference levels.................................................1.25V

Test load termination supply voltage.............................1.25V

TDO

Z = 50 Ω

O

50Ω

20pF

TAP DC Electrical Characteristics And Operating Conditions

DDQ

[13]

–5 5 µA

(0°C < TA < +70°C; VDD = 2.5V ±0.165V unless otherwise noted)

Parameter Description Test Conditions Min. Max. Unit

V

V

V

V

V

V

I

OH1

OH2

OL1

OL2

IH

IL

X

Output HIGH Voltage IOH = –1.0 mA 1.7 V

Output HIGH Voltage IOH = –100 µA 2.1 V

Output LOW Voltage IOL = 1.0 mA 0.4 V

Output LOW Voltage IOL = 100 µA 0.2 V

Input HIGH Voltage 1.7 VDD + 0.3 V

Input LOW Voltage –0.3 0.7 V

Input Load Current GND < VIN < V

Note

and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

11. t

CS

12. Test conditions are specified using the load in TAP AC test conditions. t

13. All voltages referenced to V

(GND).

SS

Document Number: 38-05548 Rev. *E Page 14 of 30

R/tF

= 1ns.

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Identification Register Definitions

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CY7C1387DV25, CY7C1387FV25

Instruction Field

Revision Number (31:29) 000 000 Describes the version number.

Device Depth (28:24) 01011 01011 Reserved for internal use

Device Width (23:18) 119-BGA 101110 101110 Defines the memory type and

Device Width (23:18) 165-FBGA 000110 000110 Defines the memory type and

Cypress Device ID (17:12) 100101 010101 Defines the width and density

Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of SRAM

ID Register Presence Indicator (0) 1 1 Indicates the presence of an ID register.

CY7C1386DV25/

CY7C1386FV25

CY7C1387DV25/

CY7C1387FV25

Description

architecture.

architecture.

vendor.

Scan Register Sizes

Register Name Bit Size (x18) Bit Size (x36)

Instruction 3 3

Bypass 1 1

ID 32 32

Boundary Scan Order (119-ball BGA package) 85 85

Boundary Scan Order (165-ball fBGA package) 89 89

Identification Codes

Instruction Code Description

EXTEST 000 Captures IO ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and

SAMPLE Z 010 Captures IO ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 011 Do Not Use. This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures IO ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 101 Do Not Use. This instruction is reserved for future use.

RESERVED 110 Do Not Use. This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

TDO. This operation does not affect SRAM operations.

Forces all SRAM output drivers to a High-Z state.

Does not affect SRAM operation.

operations.

Document Number: 38-05548 Rev. *E Page 15 of 30

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CY7C1387DV25, CY7C1387FV25

119-Ball BGA Boundary Scan Order

Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID

1

2T424E746A468M2

3T5 25 D7 47 G3 69 N1

4T626H748C370P1

5R5 27 G6 49 B2 71 K1

6L528E650B372L2

7R6 29 D6 51 A3 73

8U630C752C274P2

9R731B753A275R3

10 T7 32 C6 54 B1 76 T1

11 P6 33 A6 55 C1 77 R1

12 N7 34 C5 56 D2 78 T2

13 M6 35 B5 57 E1 79 L3

14 L7 36 G5 58 F2 80 R2

15 K6 37 B6 59 G1 81 T3

16 P7 38 D4 60 H2 82 L4

17 N6 39 B4 61 D1 83 N4

18 L6 40 F4 62 E2 84 P4

19 K7 41 M4 63 G2 85 Internal

20 J5 42 A5 64 H1

21 H6 43 K4 65 J3

22 G7 44 E4 66 2K

H4

23 F6 45 G4 67 L1

[14, 15]

N2

Notes

14. Balls that are NC (No Connect) are preset LOW.

15. Bit #85 is preset HIGH.

Document Number: 38-05548 Rev. *E Page 16 of 30

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CY7C1387DV25, CY7C1387FV25

165-Ball BGA Boundary Scan Order

Bit # Ball ID Bit # Ball ID Bit # Ball ID

1N6 31D10 61 G1

2N7 32C11 62 D2

3N10 33A11 63 E2

4P11 34B11 64 F2

5P8 35A10 65 G2

6R8 36B10 66 H1

7R9 37A9 67 H3

8P9 38B9 68 J1

9P10 39C10 69 K1

10 R10 40 A8 70 L1

11 R11 41 B8 71 M1

12 H11 42 A7 72 J2

13 N11 43 B7 73 K2

14 M11 44 B6 74 L2

15 L11 45 A6 75 M2

16 K11 46 B5 76 N1

17 J11 47 A5 77 N2

18 M10 48 A4 78 P1

19 L10 49 B4 79 R1

20 K10 50 B3 80 R2

21 J10 51 A3 81 P3

22 H9 52 A2 82 R3

23 H10 53 B2 83 P2

24 G11 54 C2 84 R4

25 F11 55 B1 85 P4

26 E11 56 A1 86 N5

27 D11 57 C1 87 P6

28 G10 58 D1 88 R6

29 F10 59 E1 89 Internal

30 E10 60 F1

[14, 16]

Note

16. Bit #89 is preset HIGH.

Document Number: 38-05548 Rev. *E Page 17 of 30

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CY7C1387DV25, CY7C1387FV25

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of
the device. For user guidelines, not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V

Supply Voltage on V

DC Voltage Applied to Outputs

in Tri-State........................................... –0.5V to V

Relative to GND ....... –0.5V to +3.6V

DD

Relative to GND ...... –0.5V to +V

DDQ

DDQ

DD

+ 0.5V

DC Input Voltage ................................... –0.5V to V

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current .................................................... >200 mA

Operating Range

Range

Commercial 0°C to +70°C 2.5V ±5% 2.5V –5%
Industrial –40°C to +85°C

Ambient

Tem per atu re

V

DD

+ 0.5V

DD

V

to V

DDQ

DD

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min. Max. Unit

V

V

V

V

V

V

I

DD

DDQ

OH

OL

IH

IL

X

Power Supply Voltage 2.375 2.625 V

IO Supply Voltage for 2.5V IO 2.375 V

Output HIGH Voltage for 2.5V IO, I

Output LOW Voltage for 2.5V IO, I

Input HIGH Voltage

Input LOW Voltage

Input Leakage Current
except ZZ and MODE

Input Current of MODE Input = V

Input Current of ZZ Input = V

I

OZ

I

DD

I

SB1

Output Leakage Current GND ≤ VI ≤ V

VDD Operating Supply
Current

Automatic CE
Power Down
Current—TTL Inputs

I

SB2

Automatic CE
Power Down
Current—CMOS Inputs

I

SB3

Automatic CE
Power Down
Current—CMOS Inputs

I

SB4

Automatic CE
Power Down
Current—TTL Inputs

[17, 18]

= –1.0 mA 2.0 V

OH

= 1.0 mA 0.4 V

SS

DD

SS

DD

= 1/t

OL

DDQ

–5 5 µA

–30 µA

–5 µA

Output Disabled –5 5 µA

DDQ,

OUT

CYC

= 0 mA,

4.0-ns cycle, 250 MHz 350 mA

5-ns cycle, 200 MHz 300 mA

[17]

for 2.5V IO 1.7 VDD + 0.3V V

[17]

for 2.5V IO –0.3 0.7 V

GND ≤ VI ≤ V

Input = V

Input = V

V

= Max., I

DD

f = f

MAX

6-ns cycle, 167 MHz 275 mA

V

= Max, Device Deselected,

DD

V

≥ VIH or VIN ≤ V

IN

f = f

V
V
f = 0

V
or V
f = f

V
V

= 1/t

MAX

= Max, Device Deselected,

DD

≤ 0.3V or VIN > V

IN

= Max, Device Deselected,

DD

≤ 0.3V or VIN > V

IN

= 1/t

MAX

= Max, Device Deselected,

DD

≥ VIH or VIN ≤ VIL, f = 0

IN

IL

CYC

DDQ

CYC

– 0.3V,

DDQ

– 0.3V

4.0-ns cycle, 250 MHz 160 mA

5-ns cycle, 200 MHz 150 mA

6-ns cycle, 167 MHz 140 mA

All speeds 70 mA

4.0-ns cycle, 250 MHz 135 mA

5-ns cycle, 200 MHz 130 mA

6-ns cycle, 167 MHz 125 mA

All Speeds 80 mA

DD

5 µA

30 µA

V

Notes

17. Overshoot: V

18. T

power up

(AC) < VDD +1.5V (pulse width less than t

IH

: assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and V

Document Number: 38-05548 Rev. *E Page 18 of 30

/2), undershoot: VIL(AC) > –2V (pulse width less than t

CYC

DDQ

< V

DD.

CYC

/2).

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CY7C1387DV25, CY7C1387FV25

Capacitance

[19]

Parameter Description Test Conditions

CIN Input Capacitance TA = 25°C, f = 1 MHz,

C

CLK

C

IO

Clock Input Capacitance 5 8 9 pF

Input/Output Capacitance 5 8 9 pF

Thermal Resistance

[19]

V

DD/VDDQ

= 2.5V

Parameter Description Test Conditions

Θ

Θ

Thermal Resistance

JA

(Junction to Ambient)

Thermal Resistance

JC

(Junction to Case)

Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA/JESD51.

AC Test Loads and Waveforms

2.5V IO Test Load

OUTPUT

Z

= 50Ω

0

V

(a)

T

R

= 1.25V

= 50Ω

L

2.5V

OUTPUT

5pF

INCLUDING

JIG AND

SCOPE

R = 1667Ω

(b)

R = 1538Ω

100 TQFP

Package

119 BG A

Package

165 FBGA

Package

5 8 9 pF

100 TQFP

Package

119 BG A

Package

165 FBGA

Package

28.66 23.8 20.7 °C/W

4.08 6.2 4.0 °C/W

V

DDQ

GND

≤ 1 ns

ALL INPUT PULSES

10%

90%

90%

(c)

Unit

Unit

10%

≤ 1 ns

Note

19. Tested initially and after any design or process change that may affect these parameters.

Document Number: 38-05548 Rev. *E Page 19 of 30

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Switching Characteristics

Over the Operating Range

Parameter Description

t

POWER

Clock

t

CYC

t

CH

t

CL

Output Times

t

CO

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Setup Times

t

AS

t

ADS

t

ADVS

t

WES

t

DS

t

CES

Hold Times

t

AH

t

ADH

t

ADVH

t

WEH

t

DH

t

CEH

[20, 21]

VDD(Typical) to the first Access

Clock Cycle Time 4.0 5.0 6.0 ns

Clock HIGH 1.7 2.0 2.2 ns

Clock LOW 1.7 2.0 2.2 ns

Data Output Valid After CLK Rise 2.6 3.0 3.4 ns

Data Output Hold After CLK Rise 1.0 1.3 1.3 ns

Clock to Low-Z

Clock to High-Z

[23, 24, 25]

[23, 24, 25]

OE LOW to Output Valid 2.6 3.0 3.4 ns

OE LOW to Output Low-Z

OE HIGH to Output High-Z

Address Setup Before CLK Rise 1.2 1.4 1.5 ns

ADSC, ADSP Setup Before CLK Rise 1.2 1.4 1.5 ns

ADV Setup Before CLK Rise 1.2 1.4 1.5 ns

GW, BWE, BWX Setup Before CLK Rise 1.2 1.4 1.5 ns

Data Input Setup Before CLK Rise 1.2 1.4 1.5 ns

Chip Enable SetUp Before CLK Rise 1.2 1.4 1.5 ns

Address Hold After CLK Rise 0.3 0.4 0.5 ns

ADSP, ADSC Hold After CLK Rise 0.3 0.4 0.5 ns

ADV Hold After CLK Rise 0.3 0.4 0.5 ns

GW, BWE, BWX Hold After CLK Rise 0.3 0.4 0.5 ns

Data Input Hold After CLK Rise 0.3 0.4 0.5 ns

Chip Enable Hold After CLK Rise 0.3 0.4 0.5 ns

[22]

[23, 24, 25]

[23, 24, 25]

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

250 MHz 200 MHz 167 MHz

Min. Max. Min. Max. Min. Max.

1 11ms

1.0 1.3 1.3 ns

2.6 3.0 3.4 ns

0 0 0 ns

2.6 3.0 3.4 ns

Unit

Notes

20. Timing reference level is 1.25V when V

21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

22. This part has a voltage regulator internally; t
can be initiated.

, t

23. t

CHZ

mV from steady-state voltage.

24. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.

25. This parameter is sampled and not 100% tested.

CLZ,tOELZ

, and t

are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 19. Transition is measured ± 200

OEHZ

DDQ

OEHZ

= 2.5V.

POWER

is less than t

Document Number: 38-05548 Rev. *E Page 20 of 30

is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation

and t

OELZ

is less than t

CHZ

to eliminate bus contention between SRAMs when sharing the same

CLZ

[+] Feedback

Switching Waveforms

Read Cycle Timing

[26]

t

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

CYC

CLK

ADSP

ADSC

ADDRESS

GW, BWE,BW

X

CE

ADV

OE

Data Out (DQ)

t

ADS

t

t

AS

CES

A1

t

t

CL

CH

t

ADH

t

t

ADH

ADS

t

AH

A2 A3

t

t

WEH

WES

t

CEH

t

t

ADVH

ADVS

ADV suspends burst

High-Z

t

CLZ

t

OEV

OEHZ

t

OELZ

t

Q(A1)

t

CO

Q(A2)

t

DOH

t

CO

Q(A2 + 1)

Single READ BURST READ

Q(A2 + 2)

Q(A2 + 3)

Burst continued with
new base address

Deselect
cycle

Q(A2)

Q(A2 + 1)

Burst wraps around
to its initial state

t

CHZ

Q(A3)

Note

26. On this diagram, when CE

is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document Number: 38-05548 Rev. *E Page 21 of 30

DON’T CARE

UNDEFINED

[+] Feedback

Switching Waveforms (continued)

Write Cycle Timing

[26, 27]

t

CYC

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

CLK

ADSP

ADSC

ADDRESS

BWE,

BW

GW

CE

ADV

t

t

CL

CH

t

t

ADH

ADS

t

t

ADH

ADS

t

t

AH

AS

A1

Byte write signals are ignored for first cycle when
ADSP initiates burst

X

t

t

CEH

CES

A2 A3

t

t

WEH

WES

ADV suspends burst

ADSC extends burst

t

ADS

t

ADH

t

WES

t

ADVS

t

WEH

t

ADVH

OE

t

t

DH

DS

Data in (D)

High-Z

t

OEHZ

D(A1)

D(A2)

D(A2 + 1)

D(A2 + 3)

D(A3)

D(A3 + 1)

ata Out (Q)

BURST READ BURST WRITE

Single WRITE

Extended BURST WRITE

DON’T CARE UNDEFINED

Note

27.

Full width write can be initiated by either GW

LOW, or by GW HIGH, BWE LOW and BWX LOW.

Document Number: 38-05548 Rev. *E Page 22 of 30

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Switching Waveforms (continued)

Read/Write Cycle Timing

[26, 28, 29]

t

CYC

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

CLK

ADSP

ADSC

ADDRESS

BWE, BW

CE

ADV

OE

Data In (D)

t

t

CL

CH

t

t

ADH

ADS

t

t

AH

AS

t

CES

High-Z

A2

t

CEH

A3

t

WES

t

OEHZ

t

DS

D(A3)

t

CO

t

CLZ

A1

X

A4 A5 A6

t

WEH

t

DH

t

OELZ

D(A5) D(A6)

Data Out (Q)

High-Z

Q(A2)Q(A1)

Back-to-Back READs

Notes

28. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP

29. GW

is HIGH.

Document Number: 38-05548 Rev. *E Page 23 of 30

Single WRITE

DON’T CARE

Q(A4)

UNDEFINED

BURST READ

or ADSC.

Q(A4+3)

Back-to-Back

WRITEs

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Switching Waveforms (continued)

ZZ Mode Timing

[30, 31]

CLK

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

t

ZZ

t

ZZREC

I

SUPPLY

ALL INPUTS

(except ZZ)

Outputs (Q)

ZZ

t

ZZI

I

DDZZ

High-Z

t

RZZI

DESELECT or READ Only

DON’T CARE

Notes

30. Device must be deselected when entering ZZ sleep mode. See cycle descriptions table for all possible signal conditions to deselect the device.

31. DQs are in high-Z when exiting ZZ sleep mode.

Document Number: 38-05548 Rev. *E Page 24 of 30

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Ordering Information

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code

167 CY7C1386DV25-167AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1387DV25-167AXC

CY7C1386FV25-167BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1387FV25-167BGC

CY7C1386FV25-167BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1387FV25-167BGXC

CY7C1386DV25-167BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1387DV25-167BZC

CY7C1386DV25-167BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1387DV25-167BZXC

CY7C1386DV25-167AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Industrial

CY7C1387DV25-167AXI

CY7C1386FV25-167BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1387FV25-167BGI

CY7C1386FV25-167BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1387FV25-167BGXI

CY7C1386DV25-167BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1387DV25-167BZI

CY7C1386DV25-167BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1387DV25-167BZXI

200 CY7C1386DV25-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1387DV25-200AXC

CY7C1386FV25-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1387FV25-200BGC

CY7C1386FV25-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1387FV25-200BGXC

CY7C1386DV25-200BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1387DV25-200BZC

CY7C1386DV25-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1387DV25-200BZXC

CY7C1386DV25-200AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Industrial

CY7C1387DV25-200AXI

CY7C1386FV25-200BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1387FV25-200BGI

CY7C1386FV25-200BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1387FV25-200BGXI

CY7C1386DV25-200BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1387DV25-200BZI

CY7C1386DV25-200BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1387DV25-200BZXI

Package
Diagram

Part and Package Type

Operating

Range

Document Number: 38-05548 Rev. *E Page 25 of 30

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Ordering Information (continued)

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.

250 CY7C1386DV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1387DV25-250AXC

CY7C1386FV25-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1387FV25-250BGC

CY7C1386FV25-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1387FV25-250BGXC

CY7C1386DV25-250BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1387DV25-250BZC

CY7C1386DV25-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1387DV25-250BZXC

CY7C1386DV25-250AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Industrial

CY7C1387DV25-250AXI

CY7C1386FV25-250BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1387FV25-250BGI

CY7C1386FV25-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1387FV25-250BGXI

CY7C1386DV25-250BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1387DV25-250BZI

CY7C1386DV25-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1387DV25-250BZXI

Document Number: 38-05548 Rev. *E Page 26 of 30

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Package Diagrams

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

Figure 1. 100-Pin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050)

16.00±0.20

14.00±0.10

20.00±0.10

22.00±0.20

100

1

30

31 50

81

80

0.30±0.08

0.65
TYP.

51

12°±1°

(8X)

1.40±0.05

0.20 MAX.

SEE DETAIL

A

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

0° MIN.

R 0.08 MIN.

0.20 MIN.

0.20 MAX.

DETAIL

1.60 MAX.

0.10

51-85050-*B

STAND-OFF

0.05 MIN.

0.15 MAX.

SEATING PLANE

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

A

Document Number: 38-05548 Rev. *E Page 27 of 30

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Package Diagrams (continued)

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

Document Number: 38-05548 Rev. *E Page 28 of 30

51-85115-*B

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Package Diagrams (continued)

Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)

TOP VIEW

TOP VIEW

PIN 1 CORNER

PIN 1 CORNER

A

A

B

B

C

C

D

D

E

E

F

F

G

G

H

H

15.00±0.10

A

0.53±0.05

0.25 C

0.36

B

J

K

L

M

N

P

R

B

0.53±0.05

C

0.36

J

K

L

M

N

P

R

SEATING PLANE

C

13.00±0.10

13.00±0.10

SEATING PLANE

15.00±0.10

A

0.25 C

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

1110986754321

1110986754321

14.00

15.00±0.10

15.00±0.10

A

A

0.15(4X)

1.40 MAX.

0.15 C

0.15 C

1.40 MAX.

0.35±0.06

0.35±0.06

11

11

1.00

1.00

14.00

7.00

7.00

5.00

B

B

0.15(4X)

NOTES :

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE WEIGHT : 0.475g

PACKAGE CODE : BB0AC

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

BOTTOM VIEW

BOTTOM VIEW

Ø0.05 M C

Ø0.25MCAB

Ø0.50 (165X)

5.00

10.00

13.00±0.10

13.00±0.10

PIN 1 CORNER

Ø0.05 M C

-0.06

Ø0.25 M C A B

+0.14

Ø0.50 (165X)

1.00

10.00

51-85180-*A

PIN 1 CORNER

-0.06

2345678910

1

+0.14

1.00

51-85180-*A

2345678910

1

A

A

B

B

C

C

D

D

E

E

F

F

G

G

H

H

J

J

K

K

L

L

M

M

N

N

P

P

R

R

i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Document Number: 38-05548 Rev. *E Page 29 of 30

© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress prod ucts are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25

Document History Page

Document Title: CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/ CY7C1387FV25 18-Mb it (512K x 36/1M x 18) Pipelined
DCD Sync SRAM
Document Number: 38-05548

REV. ECN NO. Issue Date

** 254550 See ECN RKF New data sheet

*A 288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

*B 326078 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as

*C 418125 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from

*D 475009 See ECN VKN Converted from Preliminary to Final.

*E 793579 See ECN VKN Added Part numbers CY7C1386FV25 and CY7C1387FV25

Orig. of
Change

Description of Change

non-compliance with 1149.1
Removed 225 Mhz Speed Bin
Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA
Packages
Added comment of ‘Pb-free BG packages availability’ below the Ordering
Information

per JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed Device Width (23:18) for 119-BGA from 000110 to 101110
Added separate row for 165 -FBGA Device Width (23:18)
Changed Θ

4.08 °C/W respectively
Changed Θ
°C/W respectively
Changed Θ

4.0 °C/W respectively
Modified V
Removed shading on DC Table for 200 MHz speed bin

and Θ

JA

and Θ

JA

and Θ

JA

OL, VOH

for TQFP Package from 31 and 6 °C/W to 28.66 and

JC

for BGA Package from 45 and 7 °C/W to 23.8 and 6.2

JC

for FBGA Package from 46 and 3 °C/W to 20.7 and

JC

test conditions

Removed comment of ‘Pb-free BG packages availability’ below the Ordering
Information

“3901 North First Street” to “198 Champion Court”
Changed the description of I
Current on page# 18

from Input Load Current to Input Leakage

X

Changed the IX current values of MODE on page # 18 from –5 µA and 30 µA
to –30 µA and 5 µA
Changed the IX current values of ZZ on page # 18 from –30 µA and 5 µA
to °5 µA and 30 µA
Changed V
Updated Ordering Information Table

Added the Maximum Rating for Supply Voltage on V
Changed t
AC Switching Characteristics table.

< V

IH

TH

to VIH < VDDon page # 18

DD

, t

from 25 ns to 20 ns and t

TL

Relative to GND

DDQ

from 5 ns to 10 ns in TAP

TDOV

Updated the Ordering Information table.

Added footnote# 3 regarding Chip Enable
Updated Ordering Information table

Document Number: 38-05548 Rev. *E Page 30 of 30

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