Cypress Semiconductor CY7C1381DV25, CY7C1383DV25, CY7C1381FV25, CY7C1383FV25 Specification Sheet

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Features

• Supports 133 MHz bus operations

• 512K x 36/1M x 18 common IO

• 2.5V core power supply (V

• 2.5V IO supply (V

DDQ

• Fast clock-to-output times, 6.5 ns (133 MHz version)

• Provides high-performance 2-1-1-1 access rate

• User selectable burst counter supporting Intel
interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self timed write

• Asynchronous output enable

• CY7C1381DV25/CY7C1383DV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 165-ball FBGA package.
CY7C1381FV25/CY7C1383FV25 available in Pb-free and
non Pb-free 119-ball BGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• ZZ sleep mode option

)

DD

)

®

Pentium®

Functional Description

[1]

The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 is a 2.5V, 512K x 36 and 1M x 18
synchronous flow through SRAMs, designed to interface with
high-speed microprocessors with minimum glue logic.
Maximum access delay from clock rise is 6.5 ns (133 MHz
version). A 2-bit on-chip counter captures the first address in
a burst and increments the address automatically for the rest
of the burst access. All synchronous inputs are gated by
registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining chip enable (CE
chip enables (CE2 and CE

[2]

), burst control inputs (ADSC,

3

), depth expansion

1

ADSP, and ADV), write enables (BWx, and BWE), and global
write (GW

). Asynchronous inputs include the output enable

(OE) and the ZZ pin.

The
CY7C1383FV25

CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/

allows interleaved or linear burst sequences,
selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor

) or the cache controller address strobe

address strobe

(ADSP
(ADSC) inputs. Address advancement is controlled by the
address advancement (ADV) input.

Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP

) or
address strobe controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the advance pin (ADV

).

The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 operates from a +2.5V core power supply
while all outputs also operate with a +2.5 supply. All inputs and
outputs are JEDEC-standard and JESD8-5-compatible.

Selection Guide

Maximum Access Time 6.5 8.5 ns

Maximum Operating Current 210 175 mA

Maximum CMOS Standby Current 70 70 mA

Notes

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05547 Rev. *E Revised Feburary 14, 2007

are for TQFP and 165 FBGA package only. 119 BGA is offered only in 1 chip enable.

3, CE2

133 MHz 100 MHz Unit

[+] Feedback

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

Logic Block Diagram – CY7C1381DV25/CY7C1381FV25

A0, A1, A

MODE

ADSC

ADSP

BW

BWE

ADV

BW

BW

CLK

D

C

BW

B

A

GW

CE1

CE2

CE3

OE

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

SLEEP

ADDRESS
REGISTER

BURST

COUNTER

AND LOGIC

CLR

D

D

,

DQP

DQ

BYTE

BYTE

C

C

DQ

,

DQP

B

B

DQ

,

DQP

A

A

DQ

,

DQP

BYTE

ENABLE

REGISTER

[1:0]

A

Q1

Q0

DQ

WRITE REGISTER

DQ

WRITE REGISTER

DQ

WRITE REGISTER

DQ

WRITE REGISTER

[3]

(512K x 36)

D

D

,

DQP

BYTE

C

C

,

DQP

B

B

,

DQP

A

,

DQP

BYTE

MEMORY

ARRAY

SENSE
AMPS

OUTPUT
BUFFERS

INPUT

REGISTERS

DQP

DQP

DQP

DQP

DQs

A

B

C

D

Logic Block Diagram – CY7C1383DV25/CY7C1383FV25

A0,A1,A

MODE

ADV

BW

BW A

BWE

GW

CE

CE 2
CE 3

OE

B

1

ADDRESS
REGISTER

DQ B,DQP B

DQ A,DQP A

ENABLE

SLEEP

CONTROL

Q1

BURST

COUNTER AND

Q0

A[1:0]

DQ B,DQP B

WRITE DRIVER

A,DQP A

DQ

WRITE DRIVER

[3]

(1M x 18)

MEMORY

ARRAY

SENSE
AMPS

OUTPUT
BUFFERS

INPUT

REGISTERS

DQs
DQP
DQP

A

B

Note

3. CY7C1381FV25 and CY7C1383FV25 have only 1 chip enable (CE

Document #: 38-05547 Rev. *E Page 2 of 28

).

1

[+] Feedback

Pin Configurations

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

100-pin TQFP Pinout (3 Chip Enable)

DQP
DQ

DQ
V
V

DQ

DQ

DQ

DQ
V
V

DQ

DQ

V

DQ

DQ
V
V

DQ

DQ

DQ

DQ
V
V

DQ

DQ

DQP

DDQ

SSQ

SSQ

DDQ

NC

V

DDQ

SSQ

SSQ

DDQ

NC

DD

1CE2

A

A

BWD

BWC

CE

100999897969594939291908988878685848382

C

1

C

2

C

3
4
5

C

6

C

7

C

8

C

9
10
11

C

12

C

13
14
15
16

SS

17

D

18

D

19
20
21

D

22

D

23

D

24

D

25
26
27

D

28

D

29

D

30

BWB

CY7C1381DV25

(512K x 36)

31323334353637383940414243444546474849

AAA

1A0

A

A

MODE

BWA

NC

CE3VDDV

SS

NC

V

V

SS

CLKGWBWEOEADSC

A

A

AAAAA

DD

ADSP

ADV

A

A

81

DQP

80

DQ

79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ
DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
DQP

B

B

B

B

B

B

B

B

A

A

A

A

A

A

A

A

NC

B

NC
NC

V

DDQ

V

SSQ

NC
NC

DQ

B

DQ

B

V

SSQ

V

DDQ

DQ

B

DQ

B

NC

V

DD

NC

V

SS

DQ

B

DQ

B

V

DDQ

V

SSQ

DQ

B

DQ

B

DQP

B

NC

V

SSQ

V

DDQ

NC
NC
NC

A

50

A

A

1CE2

A

A

NCNCBWBBWA

CE

100999897969594939291908988878685848382

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CY7C1383DV25

(1 Mbit x 18)

CE3VDDV

SS

CLKGWBWEOEADSC

ADSP

31323334353637383940414243444546474849

MODE

AAA

1A0

A

A

NC

NC

A

AAAAA

A

SS

DD

V

V

ADV

A

A

81

A

80

NC

79

NC

78

V

77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DDQ

V

SSQ

NC
DQP
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ
DQ
V

DDQ

V

SSQ

DQ
DQ
NC
NC
V

SSQ

V

DDQ

NC
NC
NC

A

A

A

A

A

A

A

A

A

50

A

A

Document #: 38-05547 Rev. *E Page 3 of 28

[+] Feedback

Pin Configurations (continued)

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

A

B

C

D

E

F

G
H

J

K

L

M

N

P

R

T

U

V

DDQ

NC/288M

NC/144M

DQ

C

DQ

C

V

DDQ

DQ

C

DQ

C

V

DDQ

DQ

D

DQ

D

V

DDQ

DQ

D

DQ

D

NC

NC

V

DDQ

119-Ball BGA

Pinout

CY7C1381FV25 (512K x 36)

2345671

AA AA

AA

AA

DQP

DQ

DQ

DQ
DQ

V

DD

DQ

DQ

DQ

DQ

DQP

A

V

C

C

C

C

C

V

V

BW

V

SS

SS

SS

SS

NC V

V

BW

V

V

V

SS

SS

SS

SS

D

D

D

D

D

MODE

AAA

ADSP

A

AA

DQP

DQ

DQ

DQ
DQ

V

DD

DQ

DQ

DQ

DQ

DQP

A

B

B

B

B

B

A

A

A

A

A

V

V

V

BW

V

NC

V

BW

V

V

V

NC

A

SS

SS

SS

B

SS

SS

A

SS

SS

SS

ADSC

V

DD

NC

CE

1

OE

ADV

C

GW

DD

CLK

D

NC

BWE

A1

A0

V

DD

NC/36MNC/72M

TDOTCKTDITMS

NC

V

DDQ

NC/576M

NC/1G

DQ

B

DQ

B

V

DDQ

DQ

B

DQ

B

V

DDQ

DQ

A

DQ

A

V

DDQ

DQ

A

DQ

A

NC

ZZ

V

DDQ

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

DDQ

NC/288M

NC/144M

B

NC

V

DDQ

NC

DQ

B

V

DDQ

NC

DQ

B

V

DDQ

DQ

B

NC

NC

NC/72M

V

DDQ

CY7C1383FV25 (1M x 18)

2

AA AA

AA

NCDQ

DQ

B

NC

DQ

B

NC

V

DD

DQ

B

NC

DQ

B

NC

DQP

B

A

345671

ADSP

ADSC

AA

V

SS

V

SS

V

SS

BW

V

SS

NC V

V

SS

NC

V

SS

V

SS

V

SS

MODE

V

DD

NC

CE

1

OE

ADV

B

GW

DD

CLK

NC

BWE

A1

A0

V

DD

A NC/36M A

V

V

V

NC

V

NC

V

BW

V

V

V

NC

TDOTCKTDITMS

A

SS

SS

SS

SS

SS

SS

SS

SS

A
AA

DQP

A

NC

DQ

A

NC

DQ

A

V

DD

NC

DQ

A

A

NC

DQ

A

NC

A

AA

NC

V

DDQ

NC/576M

NC/1G

NC

DQ

A

V

DDQ

DQ

A

NC

V

DDQ

DQ

A

NC

V

DDQ

NC

DQ

A

NC

ZZ

V

DDQ

Document #: 38-05547 Rev. *E Page 4 of 28

[+] Feedback

Pin Configurations (continued)

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

165-Ball FBGA Pinout (3 Chip Enable)

CY7C1381DV25 (512K x 36)

A

B
C
D

E
F
G

H
J
K
L

M

N
P

R

A

B
C
D

E

F
G
H

J
K

L
M

N
P

R

234 5671

NC/288M

NC/144M

DQP

C

DQ

C

DQ

C

DQ

C

DQ

C

NC

DQ

D

DQ

D

DQ

D

DQ

D

DQP

D

NC

MODE

A

A

NC

DQ

C

DQ

C

DQ

C

DQ

C

NC

DQ

D

DQ

D

DQ

D

DQ

D

NC

NC/72M

NC/36M

V

V

V

V

V

V

V

V

V

V

CE

CE

DDQ

DDQ

DDQ

DDQ

DDQ

NC

DDQ

DDQ

DDQ

DDQ

DDQ

A

A

BW

1

BW

2

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

BW

BW

V

V

V

V

V
V
V

V

V

V

B

A

SS

SS

SS

SS

SS

SS

SS

SS

SS

SS

C

D

NC

TDI

TMS

CY7C1383DV25 (1Mx 18)

234 5671

NC/288M

NC/144M

NC

NC

NC V

NC

NC

V

SS

DQ

B

DQ

B

DQ

B

DQ

B

DQP

B

NC

MODE

ACE

A

NC

DQ

DQ

DQ

DQ

NC

NC

NC

NC

NC

NC

NC/72M

NC/36M

CE

V

DDQ

V

B

B

B

B

V

V

V

DDQ

DDQ

DDQ

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

BW

1

2

B

NC BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

NC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

A

CE

CLK

V

SS

V

SS

V

SS

V

SS

V

SS

V

V

SS

V

SS

V

SS

V

SS

A

A1

A0

CE

CLK

V

SS

V

SS

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A

A1

SS

891011

BWE

3

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCK

OE ADSP

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

ADV

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

AADSC

A

NC

NC/576M

NC/1G DQP

DQ

DQ

DQ

DQ

NC

DQ

DQ

DQ

DQ

NC

A

DQ

B

DQ

B

DQ

B

DQ

B

ZZ

DQ

A

DQ

A

DQ

A

DQ

A

DQP

A

AA

B

B

B

B

B

A

A

A

A

A

891011

BWE

3

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCKA0

OE ADSP

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

DD

V

DD

V

SS

A

A

ADV

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

AADSC

A

A

NC/576M

NC/1G DQP

NC

NC

NC

NC
NC

DQ

DQ

DQ

DQ

NC

A

DQ

DQ

DQ

DQ

ZZ

A

A

A

A

NCV

NC

NC

NC

NC

A

AA

A

A

A

A

A

Document #: 38-05547 Rev. *E Page 5 of 28

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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

Pin Definitions

Name IO Description

, A1, A Input-

A

0

Synchronous

, BW

BW

A

BWC, BW

B

D

Input-

Synchronous

GW Input-

Synchronous

CLK Input-

Clock

CE

1

Input-

Synchronous

CE

2

Input-

Synchronous

[2]

CE

3

Input-

Synchronous

OE Input-

Asynchronous

ADV Input-

Synchronous

ADSP Input-

Synchronous

ADSC

Input-

Synchronous

BWE

Input-

Synchronous

ZZ Input-

Asynchronous

DQ

s

IO-

Synchronous

DQP

X

IO-

Synchronous

Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP
A

feed the 2-bit counter.

[1:0]

or ADSC is active LOW, and CE1, CE2, and CE

Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.

Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BW

Clock input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE

and CE

2

[2]

to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1

3

is sampled only when a new external address is loaded.

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE

and CE

1

[2]

to select or deselect the device. CE2 is sampled only when a new

3

external address is loaded.

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE

and CE2 to select or deselect the device. CE3 is sampled only when a new external

1

address is loaded.

Output enable, asynchronous input, active LOW. Controls the direction of the IO pins.
When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,
and act as input data pins. OE

is masked during the first clock of a read cycle when emerging

from a deselected state.

Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.

Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers.
A

are also loaded into the burst counter. When ADSP and ADSC are both asserted, only

[1:0]

ADSP

is recognized. ASDP is ignored when CE1 is deasserted HIGH.

Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers.
A

are also loaded into the burst counter. When ADSP and ADSC are both asserted, only

[1:0]

ADSP

is recognized

.

Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.

ZZ sleep input. This active HIGH input places the device in a non-time critical sleep
condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull down.

Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE
outputs. When HIGH, DQ

and DQPX are placed in a tri-state condition.The outputs are

s

. When OE is asserted LOW, the pins behave as

automatically tri-stated during the data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the device is deselected, regardless of
the state of OE

.

Bidirectional data parity IO lines. Functionally, these signals are identical to DQs. During
write sequences, DQP

is controlled by BWX correspondingly.

X

[2]

are sampled active.

3

and BWE).

[A:D]

Document #: 38-05547 Rev. *E Page 6 of 28

[+] Feedback

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

Pin Definitions (continued)

Name IO Description

MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to V

left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode pin has an internal pull up.

V

DD

V

DDQ

V

SS

V

SSQ

TDO JTAG serial output

TDI JTAG serial input

TMS JTAG serial input

TCK JTAG-

NC, NC/(36M,
72M, 144M,
288M, 576M,
1G)

V

/DNU Ground/DNU This pin can be connected to ground or can be left floating.

SS

Power Supply Power supply inputs to the core of the device.

IO Power Supply Power supply for the IO circuitry.

Ground Ground for the core of the device.

IO Ground Ground for the IO circuitry.

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG

Synchronous

feature is not used, this pin can be left unconnected. This pin is not available on TQFP
packages.

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

Synchronous

is not used, this pin can be left floating or connected to V
pin is not available on TQFP packages.

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

Synchronous

is not used, this pin can be disconnected or connected to V
TQFP packages.

Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be

Clock

connected to V

. This pin is not available on TQFP packages.

SS

- No Connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G
are address expansion pins and are not internally connected to the die.

through a pull up resistor. This

DD

. This pin is not available on

DD

DD

or

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t

The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 supports secondary cache in systems using
a linear or interleaved burst sequence. The interleaved burst
order supports Pentium
burst sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the processor address strobe (ADSP
the controller address strobe (ADSC
through the burst sequence is controlled by the ADV
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.

Byte write operations are qualified with the byte write enable

) and byte write select (BWX) inputs. A global write

(BWE
enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self timed write circuitry.

Three synchronous chip selects (CE
asynchronous output enable (OE

) is 6.5 ns (133 MHz device).

CDV

®

and i486™ processors. The linear

). Address advancement

, CE2, CE

1

) provide for easy bank

[2]

3

) or

input. A

) and an

selection and output tri-state control. ADSP is ignored if CE
is HIGH.

Single Read Accesses

A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP
the access is initiated by ADSC

, CE2, and CE

1

or ADSC is asserted LOW (if

, the write inputs must be

[2]

3

are all

deserted during this first cycle). The address presented to the
address inputs is latched into the address register and the
burst counter and/or control logic, and presented to the
memory core. If the OE

input is asserted LOW, the requested

data will be available at the data outputs with a maximum to

after clock rise. ADSP is ignored if CE1 is HIGH.

t

CDV

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, and (2) ADSP

, CE2, CE

1

is asserted LOW. The addresses

[2]

are all asserted

3

presented are loaded into the address register and the burst
inputs (GW
cycle. If the write inputs are asserted active (see Truth Table

for Read/Write

, BWE, and BWX) are ignored during this first clock

[4, 9]

on page 10 for appropriate states that

indicate a write) on the next clock rise, the appropriate data will
be latched and written into the device. Byte writes are allowed.
All IOs are tri-stated during a byte write. As this is a common
IO device, the asynchronous OE

input signal must be deserted

1

Document #: 38-05547 Rev. *E Page 7 of 28

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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

and the IOs must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE
asserted active, (2) ADSC

is asserted LOW, (3) ADSP is

deserted HIGH, and (4) the write input signals (GW

[2]

are all

3

, BWE, and
BWX) indicate a write access. ADSC is ignored if ADSP is
active LOW.

The addresses presented are loaded into the address register
and the burst counter, the control logic, or both, and delivered
to the memory core. The information presented to DQ

will be

X

written into the specified address location. Byte writes are
allowed. All IOs are tri-stated when a write is detected, even a
byte write. Since this is a common IO device, the
asynchronous OE

input signal must be deasserted and the IOs
must be tri-stated prior to the presentation of data to DQs. As
a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless of the state of OE

.

Burst Sequences

The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 provides an on-chip two-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A

[1:0]

and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the sleep mode. CE

, CE2, CE

1

remain inactive for the duration of t

[2]

, ADSP, and ADSC must

3

after the ZZ input

ZZREC

returns LOW.

Interleaved Burst Address Table
(MODE = Floating or V

First

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Second

Address

A1: A0

DD

)

Third

Address

A1: A0

Linear Burst Address Table (MODE = GND)

First

,

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

Fourth

Address

A1: A0

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Document #: 38-05547 Rev. *E Page 8 of 28

Sleep mode standby current ZZ > VDD – 0.2V 80 mA

Device operation to ZZ ZZ > VDD – 0.2V 2t

ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ active to sleep current This parameter is sampled 2t

CYC

CYC

ns

ns

ns

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

[+] Feedback

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

Truth Table

Cycle Description

Deselected Cycle, Power

[4, 5, 6, 7, 8]

Address

Used

CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

None H X X L X L X X X L-H Tri-State

Down

Deselected Cycle, Power

None L L X L L X X X X L-H Tri-State

Down

Deselected Cycle, Power

None L X H L L X X X X L-H Tri-State

Down

Deselected Cycle, Power

None L L X L H L X X X L-H Tri-State

Down

Deselected Cycle, Power

None X X X L H L X X X L-H Tri-State

Down

Sleep Mode, Power Down None X X X H X X X X X X Tri-State

Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L-H D
Read Cycle, Begin Burst External L H L L H L X H L L-H Q
Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q

Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State

Write Cycle, Continue Burst Next X X X L H H L L X L-H D

Write Cycle, Continue Burst Next H X X L X H L L X L-H D

Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q

Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State

Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q

Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State

Write Cycle, Suspend Burst Current X X X L H H H L X L-H D

Write Cycle, Suspend Burst Current H X X L X H H L X L-H D

Notes

4. X = Don't Care, H = Logic HIGH, L = Logic LOW.

5. WRITE

6. The DQ pins are controlled by the current cycle and the OE

7. The SRAM always initiates a read cycle when ADSP

8. OE

= L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.

the ADSP
care for the remainder of the write cycle.

inactive or when the device is deselected, and all data bits behave as output when OE

or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is

Document #: 38-05547 Rev. *E Page 9 of 28

signal. OE is asynchronous and is not sampled with the clock.

is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after

is active (LOW).

[+] Feedback

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

Truth Table for Read/Write

Function (CY7C1381DV25/CY7C1381FV25) GW BWE BW

[4, 9]

D

BW

C

BW

B

BW

Read H H X X X X

Read H L H H H H

Write Byte A (DQ

Write Byte B (DQ

Write Bytes A, B (DQ

Write Byte C (DQ

Write Bytes C, A (DQ

Write Bytes C, B (DQ

Write Bytes C, B, A (DQ

, DQPA)

DQP

B

Write Byte D (DQ

Write Bytes D, A (DQ

Write Bytes D, B (DQ

Write Bytes D, B, A (DQ
DQP

, DQPA)

B

Write Bytes D, B (DQ

Write Bytes D, B, A (DQ
DQP

, DQPA)

C

Write Bytes D, C, A (DQ

, DQPA)

DQP

B

, DQPA)HLHHHL

A

, DQPB)HLHHLH

B

, DQB, DQPA, DQPB)H L H H L L

A

, DQPC) HLHLHH

C

, DQ

C

C

, DQPD)HLLHHH

D

D

D

D

DQPC, DQPA)HLHLHL

A,

, DQ

DQPC, DQPB)H L H L L H

B,

, DQB, DQ

C

, DQ

DQPD, DQPA)H L L H H L

A,

, DQ

DQPD, DQPA)H L L H L H

A,

, DQB, DQ

D

, DQ

DQPD, DQPB)H L L L H H

B,

, DQC, DQ

D

, DQB, DQA, DQPD,

D

DQPC,

A,

DQPD,

A,

DQPD,

A,

HLHLL L

HLLHL L

HLLLHL

HLLL LH

Write All Bytes H L L L L L

Write All Bytes L X X X X X

A

Truth Table for Read/Write

Function (CY7C1383DV25/CY7C1383FV25) GW BWE BW

[4, 9]

B

BW

Read H H X X

Read H L H H

Write Byte A – (DQ

Write Byte B – (DQ

and DQPA)HLHL

A

and DQPB)HLLH

B

Write All Bytes H L L L

Write All Bytes L X X X

Note

9. Table only lists a partial listing of the byte write combinations. Any combination of BW

is valid. Appropriate write will be done based on which byte write is active.

X

A

Document #: 38-05547 Rev. *E Page 10 of 28

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CY7C1381DV25, CY7C1381FV25

Bypass Register

0

Instruction Register

012

Identification Register

012293031 ...

Boundary Scan Register

012..x ...

S

election

Circuitr

y

Selection

Circuitry

TCK

TMS

TAP CONTROLLER

TDI TDO

CY7C1383DV25, CY7C1383FV25

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1381DV25/CY7C1383DV25 incorporates a serial
boundary scan test access port (TAP). This part is fully
compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3V or 2.5V IO logic levels.

The CY7C1381DV25/CY7C1383DV25 contains a TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V

) to prevent clocking of the device. TDI and TMS are

SS

internally pulled up and may be unconnected. They may
alternately be connected to V
TDO may be left unconnected. Upon power up, the device will

through a pull up resistor.

DD

come up in a reset state, which will not interfere with the
operation of the device.

TAP Controller State Diagram

TEST-LOGIC

1

RESET

0

IDLE

1

SELECT

DR-SCAN

1 1

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

0 0

EXIT2-DR

UPDATE-DR

1 0

0

RUN-TEST/

The 0 or 1 next to each state represents the value of TMS at
the rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.

1

0

0

0 0

1

1 1

0 0

0

1

1

SELECT
IR-SCAN

0

CAPTURE-IR

0

SHIFT-IR

1

EXIT1-IR

PAUSE-IR

1

EXIT2-IR

1

UPDATE-IR

1

0

Test Data-In (TDI)

The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See TAP Controller Block Diagram).

Test Data-Out (TDO)

The TDO output ball is used to serially clock data out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See TAP Controller State Diagram.)

TAP Controller Block Diagram

1

0

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (V
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and
allow data to be scanned in and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI ball on
the rising edge of TCK. Data is output on the TDO ball on the
falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the TAP Controller Block

Diagram. Upon power up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.

) for five rising

DD

Document #: 38-05547 Rev. *E Page 11 of 28

[+] Feedback

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary ‘01’ pattern to
allow for fault isolation of the board level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V

) when the BYPASS instruction is executed.

SS

Boundary Scan Register

The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD, and SAMPLE Z instructions can be used
to capture the contents of the input and output ring.

The boundary scan order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.

(ID) Register

The ID register is loaded with a vendor specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register

Definitions on page 14.

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Identification

Codes on page 15. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions
are described in detail below.

Instructions are loaded into the TAP controller during the
Shift-IR state, when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.

EXTEST

The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the Shift-DR controller
state.

IDCODE

The IDCODE instruction causes a vendor specific 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows

the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command
places all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.

The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus
hold times (t
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK
boundary scan register.

Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required; that is, while data
captured is shifted out, the preloaded data is shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.

EXTEST Output Bus Tri-State

IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-fBGA package).
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in

and tCH). The SRAM clock input might not be

CS

captured in the

Document #: 38-05547 Rev. *E Page 12 of 28

[+] Feedback

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

the TAP controller, it will directly control the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it will enable the output buffers to
drive the output bus. When LOW, this bit will place the output
bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the Shift-DR state. During Update-DR, the value
loaded into that shift-register cell will latch into the preload

TAP Timi ng

123456

Test Clock

(TCK)

Test Mode Select

(TMS)

Test Data-In

Test Data-Out

(TDO)

(TDI)

t

t

TMSS

TDIS

t

t

TMSH

t

TDIH

t

TH

TL

register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is powered
up, and also when the TAP controller is in the Test-Logic-Reset
state.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

t

CYC

t

TDOV

t

TDOX

DON’T CARE UNDEFINED

TAP AC Switching Characteristics

Over the Operating Range

Parameter Description Min. Max. Unit

Clock

t

TCYC

t

TF

t

TH

t

TL

Output Times

t

TDOV

t

TDOX

Setup Times

t

TMSS

t

TDIS

t

CS

Hold Times

t

TMSH

t

TDIH

t

CH

[10, 11]

TCK Clock Cycle Time 50 ns

TCK Clock Frequency 20 MHz

TCK Clock HIGH time 20 ns

TCK Clock LOW time 20 ns

TCK Clock LOW to TDO Valid 10 ns

TCK Clock LOW to TDO Invalid 0 ns

TMS Setup to TCK Clock Rise 5 ns

TDI Setup to TCK Clock Rise 5 ns

Capture Setup to TCK Rise 5 ns

TMS Hold after TCK Clock Rise 5 ns

TDI Hold after Clock Rise 5 ns

Capture Hold after Clock Rise 5 ns

Notes

10. t

and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

CS

11. Test conditions are specified using the load in TAP AC test conditions. t

Document #: 38-05547 Rev. *E Page 13 of 28

R/tF

= 1 ns.

[+] Feedback

CY7C1381DV25, CY7C1381FV25

TDO

1.25V

20pF

Z = 50 Ω

O

50Ω

CY7C1383DV25, CY7C1383FV25

2.5V TAP AC Test Conditions

2.5V TAP AC Output Load Equivalent

Input pulse levels .................................................VSS to 2.5V

Input rise and fall time..................................................... 1 ns

Input timing reference levels.........................................1.25V

Output reference levels.................................................1.25V

Test load termination supply voltage.............................1.25V

TAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)

Parameter Description Test Conditions Min. Max. Unit

V

V

V

V

V

V

I

OH1

OH2

OL1

OL2

IH

IL

X

Output HIGH Voltage IOH = –1.0 mA, V

Output HIGH Voltage IOH = –100 µA, V

Output LOW Voltage IOL = 8.0 mA, V

Output LOW Voltage IOL = 100 µA V

Input HIGH Voltage V

Input LOW Voltage V

Input Load Current GND < VIN < V

[12]

= 2.5V 2.0 V

DDQ

= 2.5V 2.1 V

DDQ

= 2.5V 0.4 V

DDQ

= 2.5V 0.2 V

DDQ

= 2.5V 1.7 VDD + 0.3 V

DDQ

= 2.5V –0.3 0.7 V

DDQ

DDQ

–5 5 µA

Identification Register Definitions

Instruction Field

CY7C1381FV25

(512K x 36)

Revision Number (31:29) 000 000 Describes the version number

Device Depth (28:24) 01011 01011 Reserved for internal use.

Device Width (23:18) 119-BGA 101001 101001 Defines the memory type and architecture

Device Width (23:18) 165-FBGA 000001 000001 Defines the memory type and architecture

Cypress Device ID (17:12) 100101 010101 Defines the width and density

Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor

ID Register Presence Indicator (0) 1 1 Indicates the presence of an ID register

CY7C1381DV25/

CY7C1383DV25/

CY7C1383FV25

(1 Mbit x 18)

Description

Scan Register Sizes

Register Name Bit Size (x36) Bit Size (x18)

Instruction Bypass 3 3

Bypass 1 1

ID 32 32

Boundary Scan Order (119-ball BGA package) 85 85

Boundary Scan Order (165-ball FBGA package) 89 89

Note

12. All voltages referenced to V

Document #: 38-05547 Rev. *E Page 14 of 28

(GND).

SS

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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

Identification Codes

Instruction Code Description

EXTEST 000 Captures IO ring contents. Places the boundary scan register between TDI and TDO.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and

SAMPLE Z 010 Captures IO ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 011 Do Not Use. This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures IO ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 101 Do Not Use. This instruction is reserved for future use.

RESERVED 110 Do Not Use. This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

Forces all SRAM outputs to High-Z state.

TDO. This operation does not affect SRAM operations.

Forces all SRAM output drivers to a High-Z state.

Does not affect SRAM operation.

operations.

119-Ball BGA Boundary Scan Order

Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID

1

2T424E746A468M2

3T5 25 D7 47 G3 69 N1

4T626H748C370P1

5R5 27 G6 49 B2 71 K1

6L528E650B372L2

7R6 29 D6 51 A3 73

8U630C752C274P2

9R731B753A275R3

10 T7 32 C6 54 B1 76 T1

11 P6 33 A6 55 C1 77 R1

12 N7 34 C5 56 D2 78 T2

13 M6 35 B5 57 E1 79 L3

14 L7 36 G5 58 F2 80 R2

15 K6 37 B6 59 G1 81 T3

16 P7 38 D4 60 H2 82 L4

17 N6 39 B4 61 D1 83 N4

18 L6 40 F4 62 E2 84 P4

19 K7 41 M4 63 G2 85 Internal

20 J5 42 A5 64 H1

21 H6 43 K4 65 J3

22 G7 44 E4 66 2K

H4

23 F6 45 G4 67 L1

[13, 14]

N2

Notes

13. Balls that are NC (No Connect) are preset LOW.

14. Bit #85 is preset HIGH.

Document #: 38-05547 Rev. *E Page 15 of 28

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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

165-Ball BGA Boundary Scan Order

Bit # Ball ID Bit # Ball ID Bit # Ball ID

1 N6 31 D10 61 G1

2N7 32C11 62 D2

3 N10 33 A11 63 E2

4P11 34B11 64 F2

5 P8 35 A10 65 G2

6 R8 36 B10 66 H1

7R9 37A9 67 H3

8P9 38B9 68 J1

9P10 39C10 69 K1

10 R10 40 A8 70 L1

11 R 11 4 1 B8 71 M1

12 H11 42 A7 72 J2

13 N11 43 B7 73 K2

14 M11 44 B6 74 L2

15 L11 45 A6 75 M2

16 K11 46 B5 76 N1

17 J11 47 A5 77 N2

18 M10 48 A4 78 P1

19 L10 49 B4 79 R1

20 K10 50 B3 80 R2

21 J10 51 A3 81 P3

22 H9 52 A2 82 R3

23 H10 53 B2 83 P2

24 G11 54 C2 84 R4

25 F11 55 B1 85 P4

26 E11 56 A1 86 N5

27 D11 57 C1 87 P6

28 G10 58 D1 88 R6

29 F10 59 E1 89 Internal

30 E10 60 F1

[13, 15]

Note

15. Bit #89 is preset HIGH.

Document #: 38-05547 Rev. *E Page 16 of 28

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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of
the device. For user guidelines, not tested.

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V

Supply Voltage on V

DC Voltage Applied to Outputs

in Tri-State........................................... –0.5V to V

Relative to GND ....... –0.3V to +3.6V

DD

Relative to GND ...... –0.3V to +V

DDQ

+ 0.5V

DDQ

DD

DC Input Voltage ................................... –0.5V to V

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current ................................................... > 200 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 2.5V ± 5% 2.5V – 5%

Industrial –40°C to +85°C

DD

+ 0.5V

DD

V

to V

DDQ

DD

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min. Max. Unit

V

V

V

V

V

V

I

DD

DDQ

OH

OL

IH

IL

X

Power Supply Voltage 2.375 2.625 V

IO Supply Voltage for 2.5V IO 2.375 V

Output HIGH Voltage for 2.5V IO, I

Output LOW Voltage for 2.5V IO, I

Input HIGH Voltage

Input LOW Voltage

Input Leakage Current
except ZZ and MODE

Input Current of MODE Input = V

Input Current of ZZ Input = V

I

OZ

I

DD

I

SB1

Output Leakage Current GND ≤ VI ≤ V

VDD Operating Supply
Current

Automatic CE
Power Down
Current—TTL Inputs

I

SB2

Automatic CE
Power Down
Current—CMOS Inputs

I

SB3

Automatic CE
Power Down
Current—CMOS Inputs

I

SB4

Automatic CE
Power Down
Current—TTL Inputs

[16, 17]

= –1.0 mA 2.0 V

OH

= 1.0 mA 0.4 V

[16]

for 2.5V IO 1.7 VDD + 0.3V V

[16]

for 2.5V IO –0.3 0.7 V

GND ≤ VI ≤ V

Input = V

Input = V

V

= Max., I

DD

f = f

MAX

Max. VDD, Device Deselected,
V

≥ VIH or VIN ≤ VIL, f = f

IN

inputs switching

Max. VDD, Device Deselected,

≥ VDD – 0.3V or VIN ≤ 0.3V,

V

IN

f = 0, inputs static

Max. V
V

≥ V

IN

f = f

MAX

Max. V
V

≥ V

IN

f = 0, inputs static

OL

DDQ

SS

DD

SS

DD

Output Disabled –5 5 µA

DD,

= 0 mA,

OUT

= 1/t

CYC

, Device Deselected,

DD

– 0.3V or VIN ≤ 0.3V,

DDQ

, inputs switching

, Device Deselected,

DD

– 0.3V or VIN ≤ 0.3V,

DD

MAX,

–5 5 µA

–30 µA

–5 µA

7.5-ns cycle, 133 MHz 210 mA

10-ns cycle, 100 MHz 175 mA

7.5-ns cycle, 133 MHz 140 mA

10-ns cycle, 100 MHz 120

All speeds 70 mA

7.5-ns cycle, 133 MHz 130 mA

10-ns cycle, 100 MHz 110 mA

All speeds 80 mA

DD

5 µA

30 µA

V

Notes

16. Overshoot: V

17. T

power up

(AC) < VDD +1.5V (Pulse width less than t

IH

: assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and V

Document #: 38-05547 Rev. *E Page 17 of 28

/2), undershoot: VIL(AC) > –2V (Pulse width less than t

CYC

DDQ

< VDD.

CYC

/2).

[+] Feedback

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

Capacitance

[18]

Parameter Description Test Conditions

CIN Input Capacitance TA = 25°C, f = 1 MHz,

C

CLK

C

IO

Clock Input Capacitance 5 8 9 pF

Input/Output Capacitance 5 8 9 pF

Thermal Resistance

[18]

V

DD/VDDQ

= 2.5V

Parameter Description Test Conditions

Θ

JA

Θ

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, in
accordance with
EIA/JESD51.

AC Test Loads and Waveforms

2.5V IO Test Load

OUTPUT

Z

2.5V

= 50Ω

0

V

T

R

= 1.25V

(a) (b)

= 50Ω

L

OUTPUT

INCLUDING

JIG AND

5pF

SCOPE

R = 1667Ω

R = 1538Ω

100 TQFP

Package

119 BGA
Package

165 FBGA

Package

Unit

589pF

100 TQFP

Package

119 BGA

Package

165 FBGA

Package

Unit

28.66 23.8 20.7 °C/W

4.08 6.2 4.0 °C/W

V

GND

DDQ

≤ 1 ns

ALL INPUT PULSES

10%

90%

90%

10%

≤ 1 ns

(c)

Note

18. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05547 Rev. *E Page 18 of 28

[+] Feedback

Switching Characteristics

Over the Operating Range

Parameter Description

t

POWER

Clock

t

CYC

t

CH

t

CL

Output Times

t

CDV

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Setup Times

t

AS

t

ADS

t

ADVS

t

WES

t

DS

t

CES

Hold Times

t

AH

t

ADH

t

WEH

t

ADVH

t

DH

t

CEH

[19, 20]

VDD(Typical) to the first Access

Clock Cycle Time 7.5 10 ns

Clock HIGH 2.1 2.5 ns

Clock LOW 2.1 2.5 ns

Data Output Valid After CLK Rise 6.5 8.5 ns

Data Output Hold After CLK Rise 2.0 2.0 ns

Clock to Low-Z

Clock to High-Z

OE LOW to Output Valid 3.2 3.8 ns

OE LOW to Output Low-Z

OE HIGH to Output High-Z

Address Setup Before CLK Rise 1.5 1.5 ns

ADSP, ADSC Setup Before CLK Rise 1.5 1.5 ns

ADV Setup Before CLK Rise 1.5 1.5 ns

GW, BWE, BW

Data Input Setup Before CLK Rise 1.5 1.5 ns

Chip Enable Setup 1.5 1.5 ns

Address Hold After CLK Rise 0.5 0.5 ns

ADSP, ADSC Hold After CLK Rise 0.5 0.5 ns

GW, BWE, BW

ADV Hold After CLK Rise 0.5 0.5 ns

Data Input Hold After CLK Rise 0.5 0.5 ns

Chip Enable Hold After CLK Rise 0.5 0.5 ns

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

133 MHz 100 MHz

Min. Max. Min. Max.

[21]

[22, 23, 24]

[22, 23, 24]

[22, 23, 24]

[22, 23, 24]

Setup Before CLK Rise 1.5 1.5 ns

[A:D]

Hold After CLK Rise 0.5 0.5 ns

[A:D]

11ms

2.0 2.0 ns

0 4.0 0 5.0 ns

00ns

4.0 5.0 ns

Unit

Notes

19. Timing reference level is 1.25V.

20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

21. This part has a voltage regulator internally; t
can be initiated.

, t

22. t

CHZ

23. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.

24. This parameter is sampled and not 100% tested.

CLZ,tOELZ

, and t

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

OEHZ

POWER

is less than t

OEHZ

Document #: 38-05547 Rev. *E Page 19 of 28

is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation

and t

OELZ

is less than t

CHZ

to eliminate bus contention between SRAMs when sharing the same

CLZ

[+] Feedback

Timing Diagrams

Read Cycle Timing

[25]

t

CYC

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

CLK

ADSP

ADSC

ADDRESS

GW, BWE,BW

X

CE

ADV

OE

Data Out (Q)

t

ADS

t

t

High-Z

AS

A1

CES

t

t

CH

t

ADH

t

AH

t

WES

t

CEH

t

OEV

t

CLZ

t

CDV

Single READ

CL

t

WEH

t

Q(A1)

OEHZ

t

ADS

A2

t

ADH

t

OELZ

t

ADVS

Q(A2)

t

ADVH

t

CDV

t

DOH

Q(A2 + 1)

DON’T CARE

ADV suspends burst

Q(A2 + 2)

BURST

READ

UNDEFINED

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

Burst wraps around
to its initial state

Deselect Cycle

t

CHZ

Q(A2 + 2)

Note

25. On this diagram, when CE

is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05547 Rev. *E Page 20 of 28

[+] Feedback

Timing Diagrams (continued)

Write Cycle Timing

[25, 26]

t

CYC

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

CLK

ADSP

ADSC

ADDRESS

BWE,

BW

X

GW

CE

t

t

CL

CH

t

t

ADH

ADS

t

t

ADH

ADS

t

t

AH

AS

A1

Byte write signals are ignored for first cycle when
ADSP initiates burst

t

t

CEH

CES

A2 A3

t

WES

t

WEH

ADSC extends burst

t

ADS

t

ADH

t

t

ADVS

WES

t

WEH

t

ADVH

ADV

ADV suspends burst

OE

t

t

DH

DS

Data in (D)

Data Out (Q)

High-Z

BURST READ BURST WRITE

t

OEHZ

D(A1)

Single WRITE

D(A2)

D(A2 + 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

Extended BURST WRITE

D(A3 + 1)

D(A3 + 2)

DON’T CARE UNDEFINED

Note

26.

Full width write can be initiated by either GW

LOW, or by GW HIGH, BWE LOW and BWX LOW.

Document #: 38-05547 Rev. *E Page 21 of 28

[+] Feedback

Timing Diagrams (continued)

Read/Write Cycle Timing

[25, 27, 28]

t

CYC

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

ADSP

ADSC

ADDRESS

BWE, BW

ADV

Data In (D)

Data Out (Q)

CLK

A1 A5 A6

X

t

t

CL

CH

t

t

ADH

ADS

t

t

AH

AS

A2

t

t

CEH

CES

A3 A4

t

t

WEH

WES

CE

OE

t

t

DH

High-Z

Q(A1)

Back-to-Back READs

Q(A2)

t

OEHZ

DS

D(A3)

Single WRITE

t

OELZ

t

CDV

Q(A4) Q(A4+1)

BURST READ

Q(A4+2)

Q(A4+3)

DON’T CARE UNDEFINED

D(A5) D(A6)

Back-to-Back

WRITEs

Notes

27. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP

28. GW

is HIGH.

Document #: 38-05547 Rev. *E Page 22 of 28

or ADSC.

[+] Feedback

Timing Diagrams (continued)

ZZ Mode Timing

[29, 30]

CLK

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

t

ZZ

t

ZZREC

I

SUPPLY

ALL INPUTS

(except ZZ)

Outputs (Q)

ZZ

t

ZZI

I

DDZZ

High-Z

DON’T CARE

t

RZZI

DESELECT or READ Only

Notes

29. Device must be deselected when entering ZZ sleep mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

30. DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05547 Rev. *E Page 23 of 28

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CY7C1383DV25, CY7C1383FV25

Ordering Information

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit

www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code

133 CY7C1381DV25-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1383DV25-133AXC

CY7C1381FV25-133BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1383FV25-133BGC

CY7C1381FV25-133BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1383FV25-133BGXC

CY7C1381DV25-133BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1383DV25-133BZC

CY7C1381DV25-133BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1383DV25-133BZXC

CY7C1381DV25-133AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial

CY7C1383DV25-133AXI

CY7C1381FV25-133BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1383FV25-133BGI

CY7C1381FV25-133BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1383FV25-133BGXI

CY7C1381DV25-133BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1383DV25-133BZI

CY7C1381DV25-133BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1383DV25-133BZXI

100 CY7C1381DV25-100AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1383DV25-100AXC

CY7C1381FV25-100BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1383FV25-100BGC

CY7C1381FV25-100BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1383FV25-100BGXC

CY7C1381DV25-100BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1383DV25-100BZC

CY7C1381DV25-100BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1383DV25-100BZXC

CY7C1381DV25-100AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial

CY7C1383DV25-100AXI

CY7C1381FV25-100BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1383FV25-100BGI

CY7C1381FV25-100BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1383FV25-100BGXI

CY7C1381DV25-100BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1383DV25-100BZI

CY7C1381DV25-100BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1383DV25-100BZXI

Package
Diagram

Part and Package Type

Operating

Range

Document #: 38-05547 Rev. *E Page 24 of 28

[+] Feedback

Package Diagrams

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050)

16.00±0.20

14.00±0.10

20.00±0.10

22.00±0.20

100

1

30

31 50

81

80

0.30±0.08

0.65
TYP.

51

12°±1°

(8X)

1.40±0.05

0.20 MAX.

SEE DETAIL

A

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

0° MIN.

R 0.08 MIN.

0.20 MIN.

0.20 MAX.

DETAIL

1.60 MAX.

0.10

51-85050-*B

STAND-OFF

0.05 MIN.

0.15 MAX.

SEATING PLANE

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

A

Document #: 38-05547 Rev. *E Page 25 of 28

[+] Feedback

Package Diagrams (continued)

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

51-85115-*B

Document #: 38-05547 Rev. *E Page 26 of 28

[+] Feedback

Package Diagrams (continued)

TOP VIEW

TOP VIEW

PIN 1 CORNER

PIN 1 CORNER

A

A

B

B

C

C

D

D

E

E

F

F

G

G

H

H

15.00±0.10

A

0.53±0.05

0.25 C

0.36

B

J

K

L

M

N

P

R

B

0.53±0.05

C

0.36

J

K

L

M

N

P

R

SEATING PLANE

C

13.00±0.10

13.00±0.10

SEATING PLANE

15.00±0.10

A

0.25 C

CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

BOTTOM VIEW

1110986754321

1110986754321

14.00

15.00±0.10

15.00±0.10

A

A

0.15(4X)

1.40 MAX.

0.15 C

0.15 C

1.40 MAX.

0.35±0.06

0.35±0.06

11

11

1.00

1.00

14.00

7.00

7.00

5.00

5.00

B

B

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

13.00±0.10

NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

PACKAGE CODE : BB0AC

BOTTOM VIEW

Ø0.05 M C

Ø0.25MCAB

Ø0.50 (165X)

10.00

13.00±0.10

PIN 1 CORNER

Ø0.05 M C

-0.06

Ø0.25 M C A B

+0.14

Ø0.50 (165X)

1.00

10.00

51-85180-*A

PIN 1 CORNER

-0.06

2345678910

1

+0.14

1.00

51-85180-*A

2345678910

1

A

A

B

B

C

C

D

D

E

E

F

F

G

G

H

H

J

J

K

K

L

L

M

M

N

N

P

P

R

R

Intel and Pentium are registered trademarks, and i486 is a trademark of Intel Corporation. All product and company names
mentioned in this document are the trademarks of their respective holders.

Document #: 38-05547 Rev. *E Page 27 of 28

© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25

Document History Page

Document Title: CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/CY7C1383FV25, 18-Mbit (512K x 36/1M x 18)
Flow-Through SRAM
Document Number: 38-05547

REV. ECN NO. Issue Date

** 254518 See ECN RKF New data sheet

*A 288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

*B 326078 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as

*C 416321 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from

*D 475009 See ECN VKN Converted from Preliminary to Final.

*E 793579 See ECN VKN Added Part numbers CY7C1381FV25 and CY7C1383FV25

Orig. of
Change

Description of Change

non-compliance with 1149.1
Removed 117Mhz Speed Bin
Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA
Packages
Added comment of ‘Pb-free BG packages availability’ below the Ordering
Information

per JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed Device Width (23:18) for 119-BGA from 000001 to 101001
Added separate row for 165 -FBGA Device Width (23:18)
Changed Θ

4.08 °C/W respectively
Changed Θ
°C/W respectively
Changed Θ

4.0 °C/W respectively
Modified V
Removed comment of ‘Pb-free BG packages availability’ below the Ordering

and Θ

JA

and Θ

JA

and Θ

JA

OL, VOH

for TQFP Package from 31 and 6 °C/W to 28.66 and

JC

or BGA Package from 45 and 7 °C/W to 23.8 and 6.2

Jc

for FBGA Package from 46 and 3 °C/W to 20.7 and

Jc

test conditions

Information
Updated Ordering Information Table

“3901 North First Street” to “198 Champion Court”
Changed the description of I
Current on page# 17

from Input Load Current to Input Leakage

X

Changed the IX current values of MODE on page # 18 from –5 µA and 30 µA
to –30 µA and 5 µA
Changed the IX current values of ZZ on page # 18 from –30 µA and 5 µA
to –5 µA and 30 µA
Changed V
Replaced Package Name column with Package Diagram in the Ordering

IH

< V

to VIH < VDDon page # 18

DD

Information table

Added the Maximum Rating for Supply Voltage on V
Changed t
AC Switching Characteristics table.

, t

from 25 ns to 20 ns and t

TH

TL

from 5 ns to 10 ns in TAP

TDOV

Relative to GND

DDQ

Updated the Ordering Information table.

Added footnote# 3 regarding Chip Enable
Updated Ordering Information table

Document #: 38-05547 Rev. *E Page 28 of 28

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