Cypress Semiconductor CY7C1380D, CY7C1382D, CY7C1380F, CY7C1382F User Manual

CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

18-Mbit (512K x 36/1M x 18)

Pipelined SRAM

Features

Notes

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE

3, CE2

are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.

■ Supports bus operation up to 250 MHz

■ Available speed grades are 250, 200, and 167 MHz

■ Registered inputs and outputs for pipelined operation

■ 3.3V core power supply

■ 2.5V or 3.3V I/O power supply

■ Fast clock-to-output times
❐ 2.6 ns (for 250 MHz device)

■ Provides high performance 3-1-1-1 access rate

■ User selectable burst counter supporting Intel

leaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self-timed write

■ Asynchronous output enable

■ Single cycle chip deselect

■ CY7C1380D/CY7C1382D is available in JEDEC-standard

Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA
package; CY7C1380F/CY7C1382F is available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 119-ball BGA and 165-ball FBGA package

■ IEEE 1149.1 JTAG-Compatible Boundary Scan

■ ZZ sleep mode option

Pentium® inter-

Functional Description

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive edge triggered clock
input (CLK). The synchronous inputs include all addresses, all
data inputs, address-pipelining chip enable (CE
depth-expansion chip enables (CE

and CE

2

[2]

), burst control

3

inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE),
and global write (GW). Asynchronous inputs include the output
enable (OE

) and the ZZ pin.

Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP

) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as they are controlled by the advance pin

).

(ADV

Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Ta ble 1 on page 6 and “Truth Table” on page 10
for further details). Write cycles can be one to two or four bytes
wide as controlled by the byte write control inputs. GW
active LOW causes all bytes to be written.

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
operates from a +3.3V core power supply while all outputs
operate with a +2.5 or +3.3V power supply. All inputs and outputs
are JEDEC-standard and JESD8-5-compatible.

[1]

1

when

),

Selection Guide

Description 250 MHz 200 MHz 167 MHz Unit

Maximum Access Time 2.6 3.0 3.4 ns

Maximum Operating Current 350 300 275 mA

Maximum CMOS Standby Current 70 70 70 mA

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05543 Rev. *F Revised January 12, 2009

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Logic Block Diagram – CY7C1380D/CY7C1380F

ADDRESS
REGISTER

ADV

CLK

BURST

COUNTER

AND

LOGIC

CLR

Q1

Q0

ADSP

ADSC

MODE

BWE

GW

CE

1

CE

2

CE

3

OE

ENABLE

REGISTER

OUTPUT

REGISTERS

SENSE
AMPS

OUTPUT
BUFFERS

E

PIPELINED

ENABLE

INPUT

REGISTERS

A0, A1, A

BW

B

BW

C

BW

D

BW

A

MEMORY

ARRAY

DQs

DQP

A

DQP

B

DQP

C

DQP

D

SLEEP

CONTROL

ZZ

A

[1:0]

2

DQ

A ,

DQP

A

BYTE

WRITE REGISTER

DQ

B ,

DQP

B

BYTE

WRITE REGISTER

DQ

C ,

DQP

C

BYTE

WRITE REGISTER

DQ

D ,

DQP

D

BYTE

WRITE REGISTER

DQ

A ,

DQP

A

BYTE

WRITE DRIVER

DQ

B ,

DQP

B

BYTE

WRITE DRIVER

DQ

C ,

DQP

C

BYTE

WRITE DRIVER

DQ

D

,DQP

D

BYTE

WRITE DRIVER

A0, A1, A

ADDRESS
REGISTER

ADV

CLK

BURST

COUNTER AND

LOGIC

Q1

ADSC

BW

B

BW

A

CE

1

DQB,DQP

B

WRITE REGISTER

DQA,DQP

A

WRITE REGISTER

ENABLE

REGISTER

OE

SENSE

MEMORY

ARRAY

2

CE2
CE3

GW

BWE

PIPELINED

ENABLE

DQs
DQP

A

DQP

B

OUTPUT

INPUT

DQA,DQP

A

WRITE DRIVER

OUTPUT
BUFFERS

DQB,DQP

B

WRITE DRIVER

ZZ

SLEEP

CONTROL

Note

3. CY7C1380F and CY7C1382F in 119-ball BGA package have only 1 chip enable (CE

1

).

[3]

(512K x 36)

Logic Block Diagram – CY7C1382D/CY7C1382F

Document #: 38-05543 Rev. *F Page 2 of 34

[3]

(1M x 18)

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Pin Configurations

100-Pin TQFP Pinout (3-Chip Enable)

Figure 1. CY7C1380D, CY7C1380F(512K X 36) Figure 2. CY7C1382D, CY7C1382F (1M X 18)

Document #: 38-05543 Rev. *F Page 3 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

119-Ball BGA Pinout

2345671

A

B

C

D

E

F

G
H
J

K

L

M

N

P

R

T

U

V

DDQ

NC/288M

NC/144M

DQP

C

DQ

C

DQ

D

DQ

C

DQ

D

AA AA

ADSP

V

DDQ

AA

DQ

C

V

DDQ

DQ

C

V

DDQ

V

DDQ

V

DDQ

DQ

D

DQ

D

NC

NC

V

DDQ

V

DD

CLK

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC/576M

NC/1G

NC

NC

TDOTCKTDITMS

NC/36MNC/72M

NC

V

DDQ

V

DDQ

V

DDQ

AAA

A

A

AA

A

AA

A

A0

A1

DQ

A

DQ

C

DQ

A

DQ

A

DQ

A

DQ

B

DQ

B

DQ

B

DQ

B

DQ

B

DQ

B

DQ

B

DQ

A

DQ

A

DQ

A

DQ

A

DQ

B

V

DD

DQ

C

DQ

C

DQ

C

V

DD

DQ

D

DQ

D

DQ

D

DQ

D

ADSC

NC

CE

1

OE

ADV

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

DQP

A

MODE

DQP

D

DQP

B

BW

B

BW

C

NC V

DD

NC

BW

A

NC

BWE

BW

D

ZZ

2

345671

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

DDQ

NC/288M

NC/144M

NCDQ

B

DQ

B

DQ

B

DQ

B

AA AA

ADSP

V

DDQ

AA

NC

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

NC

NC

NC

NC/72M

V

DDQ

V

DD

CLK

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC/576M

NC/1G

NC

NC

TDOTCKTDITMS

AA

NC

V

DDQ

V

DDQ

V

DDQ

A NC/36M A

A

A

AA

A

AA

A

A0

A1

DQ

A

DQ

B

NC

NC

DQ

A

NC

DQ

A

DQ

A

NC

NC

DQ

A

NC

DQ

A

NC

DQ

A

NC

DQ

A

V

DD

NC

DQ

B

NC

V

DD

DQ

B

NC

DQ

B

NC

ADSC

NC

CE

1

OE

ADV

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

MODE

DQP

B

DQP

A

NC

BW

B

NC V

DD

NC

BW

A

NC

BWE

NC

ZZ

Figure 3. CY7C1380F (512K X 36)

Document #: 38-05543 Rev. *F Page 4 of 34

Figure 4. CY7C1382F (1M X 18)

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

165-Ball FBGA Pinout (3-Chip Enable)

234 5671
A

B
C
D

E
F
G

H

J
K
L

M
N

P

R

TDO

NC/288M

NC/144M

DQP

C

DQ

C

DQP

D

NC

DQ

D

CE

1

BW

B

CE

3

BW

C

BWE

A

CE2

DQ

C

DQ

D

DQ

D

MODE

NC

DQ

C

DQ

C

DQ

D

DQ

D

DQ

D

NC/36M

NC/72M

V

DDQ

BW

D

BW

A

CLK

GW

V

SS

V

SS

V

SS

V

SS

V

DDQ

V

SS

V

DD

V

SS

V

SS

V

SS

A

V

SS

V

SS

V

SS

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

V

DD

V

SS

V

DD

V

SS

V

SS

V

DDQ

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

SS

V

SS

V

DD

V

DD

V

SS

V

DD

V

SS

V

SS

NC

TCK

V

SS

TDI

A

A

DQ

C

V

SS

DQ

C

V

SS

DQ

C

DQ

C

NC

V

SS

V

SS

V

SS

V

SS

NC

V

SS

A1

DQ

D

DQ

D

NC

NC

V

DDQ

V

SS

TMS

891011

A

ADV

A

ADSC

NC

OE ADSP

A

NC/576M

V

SS

V

DDQ

NC/1G DQP

B

V

DDQ

V

DD

DQ

B

DQ

B

DQ

B

NC

DQ

B

NC

DQ

A

DQ

A

V

DD

V

DDQ

V

DD

V

DDQ

DQ

B

V

DD

NC

V

DD

DQ

A

V

DD

V

DDQ

DQ

A

V

DDQ

V

DD

V

DD

V

DDQ

V

DD

V

DDQ

DQ

A

V

DDQ

AA

V

SS

A

A

A

DQ

B

DQ

B

DQ

B

ZZ

DQ

A

DQ

A

DQP

A

DQ

A

A

V

DDQ

A

A0

A

V

SS

234 5671

A

B
C
D

E
F
G

H
J
K
L

M
N

P

R

TDO

NC/288M

NC/144M

NC

NC

DQP

B

NC

DQ

B

A

CE

1

NC

CE

3

BW

B

BWE

A

CE2

NC

DQ

B

DQ

B

MODE

NC

DQ

B

DQ

B

NC

NC

NC

NC/36M

NC/72M

V

DDQ

NC BW

A

CLK

GW

V

SS

V

SS

V

SS

V

SS

V

DDQ

V

SS

V

DD

V

SS

V

SS

V

SS

A

V

SS

V

SS

V

SS

V

SS

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

V

DD

V

SS

V

DD

V

SS

V

SS

V

DDQ

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

SS

V

SS

V

DD

V

DD

V

SS

V

DD

V

SS

V

SS

NC

TCKA0

V

SS

TDI

A

A

DQ

B

V

SS

NC V

SS

DQ

B

NC

NC

V

SS

V

SS

V

SS

V

SS

NC

V

SS

A1

DQ

B

NC

NC

NC

V

DDQ

V

SS

TMS

891011

A

ADV

A

ADSC

A

OE ADSP

A

NC/576M

V

SS

V

DDQ

NC/1G DQP

A

V

DDQ

V

DD

NC

DQ

A

DQ

A

NC

NC

NC

DQ

A

NC

V

DD

V

DDQ

V

DD

V

DDQ

DQ

A

V

DD

NC

V

DD

NCV

DD

V

DDQ

DQ

A

V

DDQ

V

DD

V

DD

V

DDQ

V

DD

V

DDQ

NC

V

DDQ

AA

V

SS

A

A

A

DQ

A

NC

NC

ZZ

DQ

A

NC

NC

DQ

A

A

V

DDQ

A

Figure 5. CY7C1380D/CY7C1380F (512K x 36)

Figure 6. CY7C1382D/CY7C1382F (1M x 18)

Document #: 38-05543 Rev. *F Page 5 of 34

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CY7C1380F, CY7C1382F

Table 1. Pin Definitions

Name I/O Description

, A1, A Input-

A

0

BWA, BW
BWC, BW

B
D

Synchronous

Input-

Synchronous

GW Input-

Synchronous

BWE

Input-

Synchronous

CLK Input-

Clock

CE

CE

CE

OE

1

[2]

2

[2]

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

Address inputs used to select one of the address locations. Sampled at the rising edge of
the CLK if ADSP
are fed to the two-bit counter.

or ADSC is active LOW, and CE1, CE2, and CE

.

Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.

Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BW

Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.

Clock input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
CE2 and CE
only when a new external address is loaded.

to select or deselect the device. ADSP is ignored

3

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
address is loaded.

and CE

1

3

is asserted LOW, during a burst operation.

to select or deselect the device. CE2 is sampled only when a new external

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE2 to select or deselect the device. CE3 is sampled only when a new external address

1

is loaded.

Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act
as input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.

ADV Input-

Synchronous

ADSP Input-

Synchronous

Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.

Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP
recognized. ASDP

is ignored when CE1 is deasserted HIGH.

[2]

are sampled active. A1: A0

3

and BWE).

X

conjunction with

if CE

is HIGH.

1

CE

is sampled

1

and ADSC are both asserted, only ADSP is

ADSC

Input-

Synchronous

Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP
recognized.

ZZ Input-

Asynchronous

ZZ sleep input. This active HIGH input places the device in a non-time critical sleep condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.

DQs, DQP

X

I/O-

Synchronous

Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle.
direction of the pins is controlled by OE
When HIGH, DQs and DQP

V

V

V

V

DD

SS

SSQ

DDQ

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

I/O Ground Ground for the I/O circuitry.

I/O Power

Power supply for the I/O circuitry.

Supply

Document #: 38-05543 Rev. *F Page 6 of 34

and ADSC are both asserted, only ADSP is

. When OE is asserted LOW, the pins behave as outputs.

are placed in a tri-state condition.

X

The

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Table 1. Pin Definitions (continued)

MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to V

TDO JTAG serial

output

Synchronous

TDI JTAG serial

input

Synchronous

TMS JTAG serial

input

Synchronous

TCK JTAG-

Clock

NC – No Connects. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not

floating selects interleaved burst sequence. This is a strap pin and must remain static during
device operation. Mode pin has an internal pull up.

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin must be disconnected. This pin is not available on TQFP
packages.

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being utilized, this pin can be disconnected or connected to V
TQFP packages.

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being utilized, this pin can be disconnected or connected to V
TQFP packages.

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be
connected to V

internally connected to the die.

. This pin is not available on TQFP packages.

SS

. This pin is not available on

DD

. This pin is not available on

DD

DD

or left

Document #: 38-05543 Rev. *F Page 7 of 34

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CY7C1380F, CY7C1382F

Functional Overview

All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (t
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
supports secondary cache in systems using a linear or inter­leaved burst sequence. The interleaved burst order supports
Pentium and i486™ processors. The linear burst sequence suits
processors that use a linear burst sequence. The burst order is
user selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the processor address
strobe (ADSP
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically incre­ments the address for the rest of the burst access.

Byte write operations are qualified with the byte write enable

) and byte write select (BWX) inputs. A global write enable

(BWE
(GW

) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.

Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE
selection and output tri-state control. ADSP
HIGH.

) or the controller address strobe (ADSC). Address

) is 2.6 ns (250 MHz device).

CO

) provide for easy bank

is ignored if CE1 is

Single Write Accesses Initiated by ADSP

This access is initiated when both the following conditions are
satisfied at clock rise: (1) ADSP
CE

, and CE3 are all asserted active. The address presented to

2

A is loaded into the address register and the address
advancement logic while being delivered to the memory array.
The write signals (GW
ignored during this first cycle.

ADSP

triggered write accesses require two clock cycles to
complete. If GW
data presented to the DQs inputs is written into the corre­sponding address location in the memory array. If GW is HIGH,
then the write operation is controlled by BWE

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
provides byte write capability that is described in the write cycle
descriptions table. Asserting the byte write enable input (BWE
with the selected byte write (BW
the desired bytes. Bytes not selected during a byte write
operation remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a
common I/O device, the output enable (OE
HIGH before presenting data to the DQs inputs. Doing so
tri-states the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a write cycle is detected,
regardless of the state of OE

, BWE, and BWX) and ADV inputs are

is asserted LOW on the second clock rise, the

is asserted LOW and (2) CE1,

and BWX signals.

) input, selectively writes to only

X

) must be deserted

.

)

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP
(2)

CE1, CE2, CE3 are all asserted active, and (3) the write
signals (GW
CE

is HIGH. The address presented to the address inputs (A)

1

is stored into the address advancement logic and the address
register while being presented to the memory array. The corre­sponding data is enabled to propagate to the input of the output
registers. At the rising edge of the next clock, the data is enabled
to propagate through the output register and onto the data bus
within 2.6 ns (250 MHz device) if OE
exception occurs when the SRAM is emerging from a deselected
state to a selected state; its outputs are always tri-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE
read cycles are supported. Once the SRAM is deselected at
clock rise by the chip select and either ADSP or ADSC signals,
its output tri-states immediately.

, BWE) are all deserted HIGH. ADSP is ignored if

or ADSC is asserted LOW,

is active LOW. The only

signal. Consecutive single

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC
HIGH, (3) CE
appropriate combination of the write inputs (GW
BW

) are asserted active to conduct a write to the desired

X

byte(s). ADSC
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV
this cycle. If a global write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a
common I/O device, the output enable (OE
HIGH before presenting data to the DQs inputs. Doing so
tri-states the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a write cycle is detected,
regardless of the state of OE

, CE2, and CE3 are all asserted active, and (4) the

1

-triggered Write accesses require a single clock

is asserted LOW, (2) ADSP is deserted

, BWE, and

input is ignored during

) must be deserted

.

Document #: 38-05543 Rev. *F Page 8 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Burst Sequences

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
provides a two-bit wraparound counter, fed by A1: A0, that imple­ments an interleaved or a linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.

Asserting ADV
burst counter to the next address in the burst sequence. Both

LOW at clock rise automatically increments the

Table 2. Interleaved Burst Address Table (MODE = Floating
or VDD)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

read and write burst operations are supported.

Table 3. Linear Burst Address Table (MODE = GND)

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE
ADSP

, and ADSC must remain inactive for the duration of t

after the ZZ input returns LOW.

, CE2, CE3,

1

ZZREC

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Table 4. ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Sleep mode standby current ZZ > VDD – 0.2V 80 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ Active to sleep current This parameter is sampled 2t

CYC

CYC

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

Fourth

Address

A1: A0

Fourth

Address

A1: A0

ns
ns
ns

Document #: 38-05543 Rev. *F Page 9 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Truth Table

Notes

4. X = Don't Care, H = Logic HIGH, L = Logic LOW.

5. WRITE

= L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.

6. The DQ pins are controlled by the current cycle and the

OE

signal. OE is asynchronous and is not sampled with the clock.

7. The SRAM always initiates a read cycle when ADSP

is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks

after the

ADSP

or with the assertion of

ADSC

. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a

don't care for the remainder of the write cycle.

8.

OE

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is

inactive or when the device is deselected, and all data bits behave as output when

OE

is active (LOW)

.

The Truth Table for this data sheet follows.

Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State

Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State

Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State

Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State

Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State

Sleep Mode, Power Down None X X X H X X X X X X Tri-State

READ Cycle, Begin Burst External L H L L L X X X L L-H Q

READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-State

WRITE Cycle, Begin Burst External L H L L H L X L X L-H D

READ Cycle, Begin Burst External L H L L H L X H L L-H Q

READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State

READ Cycle, Continue Burst Next X X X L H H L H L L-H Q

READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State

READ Cycle, Continue Burst Next H X X L X H L H L L-H Q

READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State

WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D

WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D

READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q

READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State

READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q

READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State

WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D

WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D

[4, 5, 6, 7, 8]

Document #: 38-05543 Rev. *F Page 10 of 34

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CY7C1380F, CY7C1382F

Truth Table for Read/Write

Note

9. Table only lists a partial listing of the byte write combinations. Any combination of BW

X

is valid. Appropriate write is done based on which byte write is active.

[4, 9]

Function (CY7C1380D/CY7C1380F) GW BWE BW

D

BW

C

BW

B

BW

A

Read HHXXXX

Read HLHHHH

Write Byte A – (DQ

Write Byte B – (DQ

and DQPA) H LHHHL

A

and DQPB)HLHHLH

B

Write Bytes B, A H L H H L L

Write Byte C – (DQ

and DQPC) HLHLHH

C

Write Bytes C, A H L H L H L

Write Bytes C, B H L H L L H

Write Bytes C, B, A H L H L L L

Write Byte D – (DQ

and DQPD) HL LHHH

D

Write Bytes D, A H L L H H L

Write Bytes D, B H L L H L H

Write Bytes D, B, A H L L H L L

Write Bytes D, C H L L L H H

Write Bytes D, C, A H L L L H L

Write Bytes D, C, B HLLLLH

Write All Bytes HLLLLL

Write All Bytes LXXXXX

Truth Table for Read/Write

Function (CY7C1382D/CY7C1382F) GW BWE BW

[4, 9]

B

BW

Read H H X X

Read H L H H

Write Byte A – (DQ

Write Byte B – (DQ

and DQPA)HLHL

A

and DQPB)HLLH

B

Write Bytes B, A H L L L

Write All Bytes H L L L

Write All Bytes L X X X

A

Document #: 38-05543 Rev. *F Page 11 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

IEEE 1149.1 Serial Boundary Scan (JTAG)

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

1

1

1

0

1 1

0 0

1 1

1

0

0

0

0 0

0

0

0 0

1

0

1

1

0

1

0

1

1

1

1 0

Bypass Register

0

Instruction Register

012

Identification Register

012293031 ...

Boundary Scan Register

012..x ...

S

election

Circuitr

y

Selection

Circuitry

TCK

TMS

TAP CONTROLLER

TDI TDO

The CY7C1380D/CY7C1382D incorporates a serial boundary
scan test access port (TAP).This part is fully compliant with

1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V
I/O logic levels.

The CY7C1380D/CY7C1382D contains a TAP controller,
instruction register, boundary scan register, bypass register, and
ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter­nally pulled up and may be unconnected. They may alternately
be connected to V
unconnected. Upon power up, the device comes up in a reset
state which does not interfere with the operation of the device.

through a pull up resistor. TDO must be left

DD

TAP Controller State Diagram

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an appli­cation. TDI is connected to the most significant bit (MSB) of any
register. (See TAP Controller Block Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See TAP Controller State Diagram.)

TAP Controller Block Diagram

The 0 or 1 next to each state represents the value of TMS at the
rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.

Document #: 38-05543 Rev. *F Page 12 of 34

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating.

At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and
enable data to be scanned in and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram.
Upon power up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.

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CY7C1380F, CY7C1382F

When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This enables data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (V
when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.

The boundary scan order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the “Identification Register Definitions”
on page 16.

SS

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit
instruction register. All combinations are listed in “Identification

Codes” on page 16. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions
are described in detail in this section.

Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller must be
moved into the Update-IR state.

EXTEST

The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the Shift-DR controller state.

IDCODE

The IDCODE instruction causes a vendor-specific 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and enables

the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP

)

controller is in a Shift-DR state. The SAMPLE Z command places
all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.

The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of
magnitude faster. As there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP may then try to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.

To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (t
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK# captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.

PRELOAD enables an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required; that is, while data captured is
shifted out, the preloaded data is shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.

EXTEST Output Bus Tri-State

IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at Bit #85
(for 119-BGA package) or Bit #89 (for 165-fBGA package). When
this scan cell, called the “extest output bus tri-state,” is latched
into the preload register during the Update-DR state in the TAP
controller, it directly controls the state of the output (Q-bus) pins,

and tCH). The SRAM clock input might not be captured

CS

Document #: 38-05543 Rev. *F Page 13 of 34

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CY7C1380F, CY7C1382F

when the EXTEST is entered as the current instruction. When

t

TL

Test Clock

(TCK)

Test Mode Select

(TMS)

t

TH

Test Data-Out

(TDO)

t

CYC

Test Data-In

(TDI)

t

TMSH

t

TMSS

t

TDIH

t

TDIS

t

TDOX

t

TDOV

DON’T CARE UNDEFINED

Notes

10. t

CS

and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

11. Test conditions are specified using the load in TAP AC test conditions. t

R/tF

= 1ns.

HIGH, it enables the output buffers to drive the output bus. When
LOW, this bit places the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the

TAP Timing

output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

TAP AC Switching Characteristics Over the Operating Range

Parameter Description Min Max Unit

Clock

t

TCYC

t

TF

t

TH

t

TL

Output Times

t

TDOV

t

TDOX

Setup Times

t

TMSS

t

TDIS

t

CS

Hold Times

t

TMSH

t

TDIH

t

CH

Document #: 38-05543 Rev. *F Page 14 of 34

TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH time 20 ns
TCK Clock LOW time 20 ns

TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns

TMS Setup to TCK Clock Rise 5 ns
TDI Setup to TCK Clock Rise 5 ns
Capture Setup to TCK Rise 5 ns

TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns

[10, 11]

[+] Feedback

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CY7C1380F, CY7C1382F

3.3V TAP AC Test Conditions

TDO

1.5V

20pF

Z = 50 Ω

O

50Ω

TDO

1.25V

20pF

Z = 50 Ω

O

50Ω

Note

12. All voltages referenced to V

SS (GND).

2.5V TAP AC Test Conditions

Input pulse levels.................................................VSS to 3.3V

Input rise and fall times....................................................1 ns

Input timing reference levels................... ........................1.5V

Output reference levels ................... ...............................1.5V

Test load termination supply voltage ................. .............1.5V

Figure 7. 3.3V TAP AC Output Load Equivalent

Input pulse levels.................................................VSS to 2.5V

Input rise and fall time .....................................................1 ns

Input timing reference levels................... ......................1.25V

Output reference levels .................. ..............................1.25V

Test load termination supply voltage .................... ........1.25V

Figure 8. 2.5V TAP AC Output Load Equivalent

TAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)

Parameter Description Test Conditions Min Max Unit

V

V

V

V

V

V

I

OH1

OH2

OL1

OL2

IH

IL

X

Output HIGH Voltage IOH = –4.0 mA, V

I

= –1.0 mA, V

OH

Output HIGH Voltage IOH = –100 µA V

Output LOW Voltage IOL = 8.0 mA V

Output LOW Voltage IOL = 100 µA V

Input HIGH Voltage V

Input LOW Voltage V

Input Load Current GND < VIN < V

[12]

= 3.3V 2.4 V

DDQ

= 2.5V 2.0 V

DDQ

= 3.3V 2.9 V

DDQ

V

= 2.5V 2.1 V

DDQ

= 3.3V 0.4 V

DDQ

V

= 2.5V 0.4 V

DDQ

= 3.3V 0.2 V

DDQ

V

= 2.5V 0.2 V

DDQ

= 3.3V 2.0 VDD + 0.3 V

DDQ

V

= 2.5V 1.7 VDD + 0.3 V

DDQ

= 3.3V –0.3 0.8 V

DDQ

V

= 2.5V –0.3 0.7 V

DDQ

DDQ

–5 5 µA

Document #: 38-05543 Rev. *F Page 15 of 34

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CY7C1380F, CY7C1382F

Identification Register Definitions

Note

13. Bit #24 is 1 in the register definitions for both 2.5v and 3.3v versions of this device.

Instruction Field

Revision Number (31:29) 000 000 Describes the version number.

Device Depth (28:24)

Device Width (23:18) 119-BGA 101000 101000 Defines the memory type and

Device Width (23:18) 165-FBGA 000000 000000 Defines the memory type and

Cypress Device ID (17:12) 100101 010101 Defines the width and density.

Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of

ID Register Presence Indicator (0) 1 1 Indicates the presence of an ID

[13]

CY7C1380D/CY7C1380F

(512K x 36)

01011 01011 Reserved for internal use.

CY7C1382D/CY7C1382F

(1 Mbit x 18)

Description

architecture.

architecture.

SRAM vendor.

register.

Scan Register Sizes

Register Name Bit Size (x36) Bit Size (x18)

Instruction 3 3

Bypass 1 1

ID 32 32

Boundary Scan Order (119-ball BGA package) 85 85

Boundary Scan Order (165-ball FBGA package) 89 89

Identification Codes

Instruction Code Description

EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 011 Do Not Use. This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 101 Do Not Use. This instruction is reserved for future use.

RESERVED 110 Do Not Use. This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

Forces all SRAM outputs to High-Z state.

This operation does not affect SRAM operations.

Forces all SRAM output drivers to a High-Z state.

Does not affect SRAM operation.

operations.

Document #: 38-05543 Rev. *F Page 16 of 34

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CY7C1380F, CY7C1382F

119-Ball BGA Boundary Scan Order

Notes

14. Balls which are NC (No Connect) are pre-set LOW.

15. Bit# 85 is pre-set HIGH.

Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID

1

2T424E746A468M2

3T5 25 D7 47 G3 69 N1

4T626H748C370P1

5R5 27 G6 49 B2 71 K1

6L528E650B372L2

7R629D651A373

8U630C752C274P2

9R731B753A275R3

10 T7 32 C6 54 B1 76 T1

11 P6 33 A6 55 C1 77 R1

12 N7 34 C5 56 D2 78 T2

13 M6 35 B5 57 E1 79 L3

14 L7 36 G5 58 F2 80 R2

15 K6 37 B6 59 G1 81 T3

16 P7 38 D4 60 H2 82 L4

17 N6 39 B4 61 D1 83 N4

18 L6 40 F4 62 E2 84 P4

19 K7 41 M4 63 G2 85 Internal

20 J5 42 A5 64 H1

21 H6 43 K4 65 J3

22 G7 44 E4 66 2K

H4

23 F6 45 G4 67 L1

[14, 15]

N2

Document #: 38-05543 Rev. *F Page 17 of 34

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CY7C1380F, CY7C1382F

165-Ball BGA Boundary Scan Order

Note

16. Bit# 89 is pre-set HIGH.

Bit # Ball ID Bit # Ball ID Bit # Ball ID

1 N6 31 D10 61 G1

2N7 32C11 62 D2

3 N10 33 A11 63 E2

4P11 34B11 64 F2

5 P8 35 A10 65 G2

6 R8 36 B10 66 H1

7R9 37A9 67 H3

8P9 38B9 68 J1

9 P10 39 C10 69 K1

10 R10 40 A8 70 L1

11 R11 41 B8 7 1 M 1

12 H11 42 A7 72 J2

13 N11 43 B7 73 K2

14 M11 44 B6 74 L2

15 L11 45 A6 75 M2

16 K11 46 B5 76 N1

17 J11 47 A5 77 N2

18 M10 48 A4 78 P1

19 L10 49 B4 79 R1

20 K10 50 B3 80 R2

21 J10 51 A3 81 P3

22 H9 52 A2 82 R3

23 H10 53 B2 83 P2

24 G11 54 C2 84 R4

25 F11 55 B1 85 P4

26 E11 56 A1 86 N5

27 D11 57 C1 87 P6

28 G10 58 D1 88 R6

29 F10 59 E1 89 Internal

30 E10 60 F1

[14, 16]

Document #: 38-05543 Rev. *F Page 18 of 34

[+] Feedback

CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Maximum Ratings

Notes

17. Overshoot: V

IH

(AC) < VDD +1.5V (pulse width less than t

CYC

/2), undershoot: VIL(AC) > –2V (pulse width less than t

CYC

/2).

18. TPower up: Assumes a linear ramp from 0v to V

DD

(min.) within 200 ms. During this time VIH < VDD and V

DDQ

< VDD.

Exceeding the maximum ratings may impair the useful life of the
device. For user guidelines, not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied ............................................ –55°C to +125°C

Supply Voltage on V

Supply Voltage on V

DC Voltage Applied to Outputs

in Tri-State ...........................................–0.5V to V

Relative to GND ........–0.3V to +4.6V

DD

Relative to GND...... –0.3V to +V

DDQ

DDQ

DD

+ 0.5V

DC Input Voltage ................................... –0.5V to V

+ 0.5V

DD

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current..................................................... >200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%
Industrial –40°C to +85°C

Ambient

Tem per ature

V

DD

V

to V

DDQ

DD

Electrical Characteristics Over the Operating Range

[17, 18]

Parameter Description Test Conditions Min Max Unit

V
V

DD

DDQ

Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage for 3.3V I/O 3.135 V

DD

for 2.5V I/O 2.375 2.625 V

V

OH

Output HIGH Voltage for 3.3V I/O, I

for 2.5V I/O, I

V

OL

Output LOW Voltage for 3.3V I/O, I

for 2.5V I/O, I

V

IH

Input HIGH Voltage

[17]

for 3.3V I/O 2.0 VDD + 0.3V V

= –4.0 mA 2.4 V

OH

= –1.0 mA 2.0 V

OH

= 8.0 mA 0.4 V

OL

= 1.0 mA 0.4 V

OL

for 2.5V I/O 1.7 VDD + 0.3V V

V

IL

Input LOW Voltage

[17]

for 3.3V I/O –0.3 0.8 V
for 2.5V I/O –0.3 0.7 V

I

X

Input Leakage Current
except ZZ and MODE

Input Current of MODE Input = V

Input Current of ZZ Input = V

I

OZ

I

DD

Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply

Current

GND ≤ VI ≤ V

SS

Input = V

Input = V

V

DD

f = f

DD

SS

DD

= Max., I

= 1/t

MAX

DDQ

–5 5 μA

–30 μA

–5 μA

Output Disabled –5 5 μA

DDQ,

OUT

CYC

= 0 mA,

4.0-ns cycle, 250 MHz 350 mA

5.0-ns cycle, 200 MHz 300 mA

5 μA

30 μA

6.0-ns cycle, 167 MHz 275 mA

I

SB1

I

SB2

I

SB3

I

SB4

Automatic CE
Power Down
Current—TTL Inputs

Automatic CE Power
Down Current-CMOS
Inputs

Automatic CE
Power Down
Current—CMOS Inputs

Automatic CE
Power Down
Current—TTL Inputs

V

= Max, Device Deselected,

DD

V

≥ VIH or VIN ≤ V

IN

f = f

V
V

V
V
f = f

V
V

= 1/t

MAX

= Max, Device Deselected,

DD

≤ 0.3V or VIN > V

IN

= Max, Device Deselected, or

DD

≤ 0.3V or VIN > V

IN

= 1/t

MAX

= Max, Device Deselected,

DD

≥ VIH or VIN ≤ VIL, f = 0

IN

IL

CYC

DDQ

DDQ

CYC

– 0.3V, f = 0

– 0.3V

4.0-ns cycle, 250 MHz 160 mA

5.0-ns cycle, 200 MHz 150 mA

6.0-ns cycle, 167 MHz 140 mA

All speeds 70 mA

4.0-ns cycle, 250 MHz 135 mA

5.0-ns cycle, 200 MHz 130 mA

6.0-ns cycle, 167 MHz 125 mA

All speeds 80 mA

V

Document #: 38-05543 Rev. *F Page 19 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Capacitance

Parameter Description Test Conditions

CIN Input Capacitance TA = 25°C, f = 1 MHz,

C

CLK

C

IO

[19]

V

= 3.3V.

Clock Input Capacitance 5 8 9 pF

Input/Output Capacitance 5 8 9 pF

V

DD
DDQ

= 2.5V

100 TQFP

Package

589pF

119 BGA
Package

165 FBGA

Package

Unit

Thermal Resistance

Parameter Description Test Conditions

Θ

Θ

JA

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

[19]

Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, in accordance with
EIA/JESD51.

100 TQFP

Package

28.66 23.8 20.7 °C/W

4.08 6.2 4.0 °C/W

119 BGA
Package

165 FBGA

Package

Unit

Document #: 38-05543 Rev. *F Page 20 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Figure 9. AC Test Loads and Waveforms

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

R

L

= 50Ω

Z

0

= 50Ω

VT= 1.5V

3.3V
ALL INPUT PULSES

V

DDQ

GND

90%

10%

90%

10%

≤ 1 ns

≤ 1 ns

(c)

OUTPUT

R = 1667Ω

R = 1538Ω

5pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

OUTPUT

R

L

= 50Ω

Z

0

= 50Ω

V

T

= 1.25V

2.5V
ALL INPUT PULSES

V

DDQ

GND

90%

10%

90%

10%

≤ 1 ns

≤ 1 ns

(c)

3.3V I/O Test Load

2.5V I/O Test Load

Note

19. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05543 Rev. *F Page 21 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Switching Characteristics Over the Operating Range

Notes

20. Timing reference level is 1.5V when V

DDQ

= 3.3V and is 1.25V when V

DDQ

= 2.5V.

21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

22. This part has a voltage regulator internally; t

POWER

is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation

can be initiated.

23. t

CHZ

, t

CLZ,tOELZ

, and t

OEHZ

are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 21. Transition is measured ± 200

mV from steady-state voltage.

24. At any given voltage and temperature, t

OEHZ

is less than t

OELZ

and t

CHZ

is less than t

CLZ

to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.

25. This parameter is sampled and not 100% tested.

Parameter

t

POWER

Clock

t

CYC

t

CH

t

CL

Output Times

t

CO

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Setup Times

t

AS

t

ADS

t

ADVS

t

WES

t

DS

t

CES

Hold Times

t

AH

t

ADH

t

ADVH

t

WEH

t

DH

t

CEH

VDD(Typical) to the first Access

Clock Cycle Time 4.0 56 ns

Clock HIGH 1.7 2.0 2.2 ns

Clock LOW 1.7 2.0 2.2 ns

Data Output Valid After CLK Rise 2.6 3.0 3.4 ns

Data Output Hold After CLK Rise 1.0 1.3 1.3 ns

Clock to Low-Z

Clock to High-Z

OE LOW to Output Valid 2.6 3.0 3.4 ns

OE LOW to Output Low-Z

OE HIGH to Output High-Z

Address Setup Before CLK Rise 1.2 1.4 1.5 ns

ADSC, ADSP Setup Before CLK Rise 1.2 1.4 1.5 ns

ADV Setup Before CLK Rise 1.2 1.4 1.5 ns

GW, BWE, BWX Setup Before CLK Rise 1.2 1.4 1.5 ns

Data Input Setup Before CLK Rise 1.2 1.4 1.5 ns

Chip Enable SetUp Before CLK Rise 1.2 1.4 1.5 ns

Address Hold After CLK Rise 0.3 0.4 0.5 ns

ADSP, ADSC Hold After CLK Rise 0.3 0.4 0.5 ns

ADV Hold After CLK Rise 0.3 0.4 0.5 ns

GW, BWE, BWX Hold After CLK Rise 0.3 0.4 0.5 ns

Data Input Hold After CLK Rise 0.3 0.4 0.5 ns

Chip Enable Hold After CLK Rise 0.3 0.4 0.5 ns

Description

[22]

[23, 24, 25]

[23, 24, 25]

[23, 24, 25]

[23, 24, 25]

[20, 21]

250 MHz 200 MHz 167 MHz

Min Max Min Max Min Max

1 11 ms

1.0 1.3 1.3 ns

2.6 3.0 3.4 ns

0 00 ns

2.6 3.0 3.4 ns

Unit

Document #: 38-05543 Rev. *F Page 22 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Switching Waveforms

t

CYC

t

CL

CLK

ADSP

t

ADH

t

ADS

ADDRESS

t

CH

OE

ADSC

CE

t

AH

t

AS

A1

t

CEH

t

CES

GW, BWE,

BWx

Data Out (Q)

High-Z

t

CLZ

t

DOH

t

CO

ADV

t

OEHZ

t

CO

Single READ BURST READ

t

OEV

t

OELZ

t

CHZ

ADV
suspends
burst.

Burst wraps around
to its initial state

t

ADVH

t

ADVS

t

WEH

t

WES

t

ADH

t

ADS

Q(A2) Q(A2 + 1) Q(A2 + 2)

Q(A1)

Q(A2) Q(A2 + 1)Q(A2 + 3)

A2 A3

Deselect
cycle

Burst continued with
new base address

DON’T CARE

UNDEFINED

Note

26. On this diagram, when CE

is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Figure 10. Read Cycle Timing

[26]

Document #: 38-05543 Rev. *F Page 23 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Switching Waveforms (continued)

t

CYC

t

CL

CLK

ADSP

t

ADH

t

ADS

ADDRESS

t

CH

OE

ADSC

CE

t

AH

t

AS

A1

t

CEH

t

CES

BWE,

BW

X

High-Z

ADV

BURST READ BURST WRITE

D(A2) D(A2 + 1) D(A2 + 1)

D(A1)

D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

A2 A3

Data In (D)

Extended BURST WRITE

D(A2 + 2)

Single WRITE

t

ADH

t

ADS

t

ADH

t

ADS

t

OEHZ

t

ADVH

t

ADVS

t

WEH

t

WES

t

DH

t

DS

GW

t

WEH

t

WES

Byte write signals are
ignored for first cycle when
ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE

UNDEFINED

Note

27.

Full width write can be initiated by either GW

LOW; or by GW HIGH, BWE LOW and BWX LOW

.

Figure 11. Write Cycle Timing

[26, 27]

Document #: 38-05543 Rev. *F Page 24 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Switching Waveforms (continued)

t

CYC

t

CL

CLK

ADSP

t

ADH

t

ADS

ADDRESS

t

CH

OE

ADSC

CE

t

AH

t

AS

A2

t

CEH

t

CES

BWE,

BW

X

Data Out (Q)

High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READBack-to-Back READs

High-Z

Q(A2)Q(A1)

Q(A4) Q(A4+1) Q(A4+2)

t

WEH

t

WES

Q(A4+3)

t

OEHZ

t

DH

t

DS

t

OELZ

t

CLZ

t

CO

Back-to-Back

WRITEs

A1

DON’T CARE UNDEFINED

A3

Notes

28. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP

or ADSC.

29. GW

is HIGH.

Figure 12. Read/Write Cycle Timing

[26, 28, 29]

Document #: 38-05543 Rev. *F Page 25 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Switching Waveforms (continued)

t

ZZ

I

SUPPLY

CLK

ZZ

t

ZZREC

ALL INPUTS

(except ZZ)

DON’T CARE

I

DDZZ

t

ZZI

t

RZZI

Outputs (Q)

High-Z

DESELECT or READ Only

Notes

30. Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.

31. DQs are in high-Z when exiting ZZ sleep mode.

Figure 13. ZZ Mode Timing

[30, 31]

Document #: 38-05543 Rev. *F Page 26 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Ordering Information

The following table lists all speed, package and temperature range options. Please note that some options listed below may not
be available for order entry. To verify the availability of a specific option, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products, or contact your local sales representative for the status of
availability of parts.

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the
office closest to you, visit us at http://app.cypress.com/portal/server.pt?space=CommunityPage&control=SetCom-

munity&CommunityID=201&PageID=230.

Speed

(MHz) Ordering Code

250 CY7C1380D-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1382D-250AXC

CY7C1380F-250AXC

CY7C1382F-250AXC

CY7C1380F-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1382F-250BGC

CY7C1380F-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1382F-250BGXC

CY7C1380D-250BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1382D-250BZC

CY7C1380F-250BZC

CY7C1382F-250BZC

CY7C1380D-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1382D-250BZXC

CY7C1380F-250BZXC

CY7C1382F-250BZXC

CY7C1380D-250AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Industrial

CY7C1382D-250AXI

CY7C1380F-250AXI

CY7C1382F-250AXI

CY7C1380F-250BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1382F-250BGI

CY7C1380F-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1382F-250BGXI

CY7C1380D-250BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1382D-250BZI

CY7C1380F-250BZI

CY7C1382F-250BZI

CY7C1380D-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1382D-250BZXI

CY7C1380F-250BZXI

CY7C1382F-250BZXI

Package
Diagram

Part and Package Type

Operating

Range

Document #: 38-05543 Rev. *F Page 27 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Speed

(MHz) Ordering Code

200 CY7C1380D-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1382D-200AXC

CY7C1380F-200AXC

CY7C1382F-200AXC

CY7C1380F-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1382F-200BGC

CY7C1380F-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1382F-200BGXC

CY7C1380D-200BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1382D-200BZC

CY7C1380F-200BZC

CY7C1382F-200BZC

CY7C1380D-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1382D-200BZXC

CY7C1380F-200BZXC

CY7C1382F-200BZXC

CY7C1380D-200AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Industrial

CY7C1382D-200AXI

CY7C1380F-200AXI

CY7C1382F-200AXI

CY7C1380F-200BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1382F-200BGI

CY7C1380F-200BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1382F-200BGXI

CY7C1380D-200BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1382D-200BZI

CY7C1380F-200BZI

CY7C1382F-200BZI

CY7C1380D-200BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1382D-200BZXI

CY7C1380F-200BZXI

CY7C1382F-200BZXI

Package
Diagram

Part and Package Type

Operating

Range

Document #: 38-05543 Rev. *F Page 28 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Speed

(MHz) Ordering Code

167 CY7C1380D-167AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1382D-167AXC

CY7C1380F-167AXC

CY7C1382F-167AXC

CY7C1380F-167BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1382F-167BGC

CY7C1380F-167BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1382F-167BGXC

CY7C1380D-167BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1382D-167BZC

CY7C1380F-167BZC

CY7C1382F-167BZC

CY7C1380D-167BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1382D-167BZXC

CY7C1380F-167BZXC

CY7C1382F-167BZXC

CY7C1380D-167AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Industrial

CY7C1382D-167AXI

CY7C1380F-167AXI

CY7C1382F-167AXI

CY7C1380F-167BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1382F-167BGI

CY7C1380F-167BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1382F-167BGXI

CY7C1380D-167BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1382D-167BZI

CY7C1380F-167BZI

CY7C1382F-167BZI

CY7C1380D-167BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1382D-167BZXI

CY7C1380F-167BZXI

CY7C1382F-167BZXI

Package
Diagram

Part and Package Type

Operating

Range

Document #: 38-05543 Rev. *F Page 29 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Package Diagrams

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

3. DIMENSIONS IN MILLIMETERS

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

0.30±0.08

0.65

20.00±0.10

22.00±0.20

1.40±0.05

12°±1°

1.60 MAX.

0.05 MIN.

0.60±0.15

0° MIN.

0.25

0°-7°

(8X)

STAND-OFF

R 0.08 MIN.

TYP.

0.20 MAX.

0.15 MAX.

0.20 MAX.

R 0.08 MIN.

0.20 MAX.

14.00±0.10

16.00±0.20

0.10

SEE DETAIL

A

DETAIL

A

1

100

30

31 50

51

80

81

GAUGE PLANE

1.00 REF.

0.20 MIN.

SEATING PLANE

51-85050-*B

Figure 14. 100-Pin Thin Plastic Quad Flat Pack (14 x 20 x 1.4 mm) (51-85050)

Document #: 38-05543 Rev. *F Page 30 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Package Diagrams (continued)

51-85115-*B

Figure 15. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

Document #: 38-05543 Rev. *F Page 31 of 34

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CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

Package Diagrams (continued)

A

1

PIN 1 CORNER

15.00±0.10

13.00±0.10

7.00

1.00

Ø0.50 (165X)

Ø0.25MCAB

Ø0.05 M C

B

A

0.15(4X)

0.35±0.06

SEATING PLANE

0.53±0.05

0.25 C

0.15 C

PIN 1 CORNER

TOP VIEW

BOTTOM VIEW

2345678910

10.00

14.00

B

C

D

E

F

G

H

J

K

L

M

N

11

1110986754321

P

R

P

R

K

M

N

L

J

H

G

F

E

D

C

B

A

A

15.00±0.10

13.00±0.10

B

C

1.00

5.00

0.36

-0.06
+0.14

1.40 MAX.

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

NOTES :

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

51-85180-*A

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

A

1

PIN 1 CORNER

15.00±0.10

13.00±0.10

7.00

1.00

Ø0.50 (165X)

Ø0.25 M C A B

Ø0.05 M C

B

A

0.15(4X)

0.35±0.06

SEATING PLANE

0.53±0.05

0.25 C

0.15 C

PIN 1 CORNER

TOP VIEW

BOTTOM VIEW

2345678910

10.00

14.00

B

C

D

E

F

G

H

J

K

L

M

N

11

1110986754321

P

R

P

R

K

M

N

L

J

H

G

F

E

D

C

B

A

A

15.00±0.10

13.00±0.10

B

C

1.00

5.00

0.36

-0.06

+0.14

1.40 MAX.

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

NOTES :

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

51-85180-*A

Figure 16. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)

Document #: 38-05543 Rev. *F Page 32 of 34

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Document History Page

Document Title: CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F, 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Document Number: 38-05543

REV. ECN NO.

Submission

Date

** 254515 See ECN RKF New data sheet

*A 288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

*B 326078 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as per

*C 416321 See ECN NXR Converted from Preliminary to Final

*D 475009 See ECN VKN Added the Maximum Rating for Supply Voltage on V

*E 776456 See ECN VKN Added Part numbers CY7C1380F and CY7C1382F and its related information

*F 2648065 01/27/09 VKN/PYRS Modified note on top of the Ordering information table

Orig. of

Change

Description of Change

non-compliance with 1149.1
Removed 225MHz and 133 MHz Speed Bins
Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA Packages
Added comment of ‘Pb-free BG packages availability’ below the Ordering Infor­mation

JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed Device Width (23:18) for 119-BGA from 000000 to 101000
Added separate row for 165 -FBGA Device Width (23:18)
Changed Θ
°C/W respectively
Changed Θ
respectively
Changed Θ
respectively
Modified V
Removed comment of ‘Pb-free BG packages availability’ below the Ordering Infor-

and Θ

JA

and Θ

JA

and Θ

JA

OL, VOH

for TQFP Package from 31 and 6 °C/W to 28.66 and 4.08

JC

for BGA Package from 45 and 7 °C/W to 23.8 and 6.2 °C/W

JC

for FBGA Package from 46 and 3 °C/W to 20.7 and 4.0 °C/W

JC

test conditions

mation
Updated Ordering Information Table

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Changed the description of I
page# 18

from Input Load Current to Input Leakage Current on

X

Changed the IX current values of MODE on page # 18 from –5 μA and 30 μA
to –30 μA and 5 μA
Changed the I
to –5 μA and 30 μA
Changed VIH < V
Replaced Package Name column with Package Diagram in the Ordering

current values of ZZ on page # 18 from –30 μA and 5 μA

X

to VIH < VDDon page # 18

DD

Information table
Updated Ordering Information Table

Relative to GND
Changed t
Switching Characteristics table.

, t

from 25 ns to 20 ns and t

TH

TL

TDOV

DDQ

from 5 ns to 10 ns in TAP AC

Updated the Ordering Information table.

Added footnote# 3 regarding Chip Enable
Updated Ordering Information table

Updated Ordering Information table to include CY7C1380F/CY7C1382F in 100-Pin
TSOP and 165 BGA package

Document #: 38-05543 Rev. *F Page 33 of 34

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Sales, Solutions, and Legal Information

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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.

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© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 38-05543 Rev. *F Revised January 12, 2009 Page 34 of 34

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