Cypress Semiconductor CY7C1370DV25, CY7C1372DV25 User Manual

a b c d

C

CY7C1370DV25 CY7C1372DV25

18-Mbit (512K x 36/1M x 18)

Pipelined SRAM with NoBL™ Architecture

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200 and 167 M Hz

• Internally self-timed output buffer control to eliminate the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined operation

• Byte Write capability

• Single 2.5V core power supply (V

• 2.5V I/O power supply (V

DDQ

)

• Fast clock-to-output times — 2.6 ns (for 250-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchronous self-timed writes

• Available in JEDEC-standard lead-free 100-Pin TQFP, lead-free and non-lead-free 119-Ball BGA and 165-Ball FBGA packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

DD

)

Functional Description

The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x 36 and 1 Mbit x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370DV25 and CY7C1372DV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370DV25 and CY7C1372DV25 are pin-compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN which when deasserted suspends operation and extends the previous clock cycle.

Write operations are controlled by the Byte Write Selects (BW

–BWd for CY7C1370DV25 and BWa–BWb for

a

CY7C1372DV25) and a Write Enable (WE

) input. All writes are

conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE

asynchronous Output Enable (OE

, CE2, CE3) and an

1

) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.

) signal,

Logic Block Diagram-CY7C1370DV25 (512K x 36)

A0, A1, A

MODE

CLK

C

EN

ADV/LD

BW

a

BW

b

BW

c

BW

d

WE

OE CE1 CE2 CE3

ZZ

ADDRESS

REGISTER 0

WRITE ADDRESS

REGISTER 1

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

SLEEP

CONTROL

ADV/LD

C

WRITE ADDRESS

REGISTER 2

A1

D1D0Q1

A0

BURST LOGIC

A1' A0'

Q0

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

REGISTER 1

O

S

U T

E

P

N

U T

S E

R E G

A

I

M

S T

P

E

S

R S

E

REGISTER 0

INPUT

O

D

U T

A

P

T

U

A

T B

S T E E R

I N G

E

DQs

U

DQP

F

DQP

F

DQP

E

DQP

R S

E

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05558 Rev. *D Revised June 29, 2006

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a b

C

Logic Block Diagram-CY7C1372DV25 (1M x 18)

CY7C1370DV25 CY7C1372DV25

CLK

EN

A0, A1, A

MODE

C

ADV/LD

BW

a

BW

b

WE

ADDRESS

REGISTER 0

WRITE ADDRESS

REGISTER 1

A1

D1D0Q1

A0

ADV/LD

C

WRITE ADDRESS

REGISTER 2

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST LOGIC

Q0

A1' A0'

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

REGISTER 1

O U T P

S

U

E

T

N

S

R

E

E G

A

I

M

S

P

T

S

E R

S

E

INPUT

REGISTER 0

O U T P

D

U

A

T

T A

B U

S

F

T

F

E

R

S

I N G

DQs DQP DQP

E

OE

CE1

READ LOGIC

CE2 CE3

ZZ

Sleep

Control

Selection Guide

250 MHz 200 MHz 167 MHz Unit

Maximum Access Time 2.6 3.0 3.4 ns Maximum Operating Current 350 300 275 mA Maximum CMOS Standby Current 70 70 70 mA

Document #: 38-05558 Rev. *D Page 2 of 27

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Pin Configurations

a

100-Pin TQFP Pinout

CY7C1370DV25 CY7C1372DV25

DQPc

DQc DQc

V

DDQ

V

SS

DQc DQc

V

SS

V

DDQ

DQc

NC

V

DD

NC V

SS

DQd DQd

V

DDQ

V

SS

DQd DQd DQd DQd V

SS

V

DDQ

DQd DQd

DQPd

1CE2

A

CE

BWd

BWc

3

CE

VDDV

SS

CLKWECEN

OE

BWa

BWb

100999897969594939291908988878685848382

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

CY7C1370DV25

(512K × 36)

17 18 19 20 21 22 23 24 25 26 27 28 29 30

31323334353637383940414243444546474849

AAA

MODE

0

A

A1A

SS

DD

V

NC(144)

NC(288)

NC(72)

AAA

A

NC(36)

ADV/LD

A

81

DDQ SS

SS

DDQ

SS

DD

DDQ

SS

SS DDQ

NC NC NC

V

DDQ

V

NC

NC DQb DQb

V

SS

V

DDQ

DQb DQb

NC

V

DD

NC

V DQb DQb

V

DDQ

V DQb

DQb

DQPb

NC

V

DDQ

NC NC NC

SS

DQPb

80

DQb

79

DQb

78

V

77

V

76

DQb

75

DQb

74

DQb

73

DQb

72

V

71

V

70

DQb

69

DQb

68

V

67

NC

66

V

65

ZZ

64

DQa

63

DQa

62

V

61

V

60

DQa

59

DQa

58

DQa

57

DQa

56

V

55

V

54

DQa

53

DQa

52

DQPa

51

50

1CE2

A

CE

100999897969594939291908988878685848382

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31323334353637383940414243444546474849

bBWa

3

SS

VDDV

CE

BW

NC

CLKWECEN

CY7C1372DV25

(1M × 18)

OE

ADV/LD

A

81

A

80

NC

79

NC

78

V

77

DDQ

V

SS

76

NC

75

DQP

74

DQa DQa V

SS

V

DDQ

DQa DQa V

SS

NC V

DD

ZZ DQa

DQa V

DDQ

V

SS

DQa DQa NC NC V

SS

V

DDQ

NC NC NC

73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

50

A

AAA

MODE

1A0

A

AAA

A

DD

SS

V

NC(144)

NC(288)

A

NC(36)

NC(72)

A

Document #: 38-05558 Rev. *D Page 3 of 27

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Pin Configurations (continued)

CY7C1370DV25 CY7C1372DV25

A B

C D

E F G H

J K L M N P

R T U

A B C

D E F G

H J

K L

M N

P

R

T

U

V

DDQ

NC/576M

NC/1G

DQ

c

DQ

c

V

DDQ

DQ

c

DQ

c

V

DDQ

DQ

d

DQ

d

V

DDQ

DQ

d

DQ

d

NC/144M

NC

V

DDQ

V

DDQ

NC/576M

NC/1G

b

NC

V

DDQ

NC

DQ

b

V

DDQ

NC

DQ

b

V

DDQ

DQ

b

NC

NC/144M

NC/72M

V

DDQ

119-Ball BGA

Pinout

CY7C1370DV25 (512K × 36)

2345671

AA AAAV

CE

2

A

DQP

c

DQ

c

DQ

c

DQ

c

DQ

c

V

DD

DQ

d

DQ

d

DQd

DQ

d

DQP

d

A

NC/72M

TMS

A A

V

SS

V

SS

V

SS

BW

V

SS

NC

V

SS

BW

V

SS

V

SS

V

SS

MODE

A

ADV/LD

V

DD

NC DQP

CE

1

OE

c

A

WE V

DD

CLK

d

NC

CEN

A1 A0 V

V

DD

A NC/36M

TCK

ACE3NC AANC

V

SS

V

SS

V

SS

BW

V

SS

NC V

V

SS

BW

V

SS

V

SS SS

DQ

b

DQ

b

DQ DQ

b b

DD

a a

b

a

DQP

NC

A

NCTDI TDO V

DDQ

DQ

b

a

DQ

V

DQ DQ

V

DQ DQ

V

DQ DQ

b b

DDQ

b b

DDQ

a a

DDQ

a a

NC/288MA

ZZ

DDQ

CY7C1372DV25 (1M x 18)

2345671

AA AAAV

CE

A

NCDQ

DQ

NC

DQ

NC

V

DD

DQ

NC

DQ

NC

DQP

A A

TMS

2

b

A A

V

SS

V

SS

V

SS

BW

V

SS

NC

V

SS

NC

V

SS

V

SS

V

SS

MODE

A

b

ADV/LD

V

DD

NC NCDQP

CE

1

OE

A AANC

V

SS

V

SS

V

SS

CE

NC

DQ

3

a

ANCNC

WE

V

DD

CLK

NC NC

CEN

A1 A0 V

V

DD

NC/36M

V

SS

NC V

SS

BW

V

SS

V

SS SS

NC

A

TCK

a

DQ

a

DD

NCV

DQ

a

NC V

DQ

a

NC

A A

NCTDI TDO V

a

DDQ

NC

DQ

a

V

DDQ

DQ

a

NC

V

DDQ

DQ

a

DDQ

NC

DQ

a

NC/288M

ZZ

DDQ

Document #: 38-05558 Rev. *D Page 4 of 27

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Pin Configurations (continued)

234 5671

A B C

D E F G

H J K L

M N

P

R

A B C

D E

F G H

J K

L

M

N P

R

NC/576M

NC/1G

DQP

c

DQ

c

DQ

c

DQ

c

DQ

c

NC

DQ

d

DQ

d

DQ

d

DQ

d

DQP

d

NC/144M

MODE

NC/576M

NC/1G

NC NC

NC V NC NC

NC

DQ

b

DQ

b

DQ

b

DQ

b

DQP

b

NC/144M

MODE

A A

NC

DQ

c

DQ

c

DQ

c

DQ

c

NC

DQ

d

DQ

d

DQ

d

DQ

d

NC

NC/72M NC/36M

2345671

A A

NC

DQ

b

DQ

b

DQ

b

DQ

b

NC NC NC NC

NC NC

NC/72M NC/36M

CE

CE2

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

CE

CE2 V V V V V

NC

V V V V V

A A

DDQ DDQ

DDQ DDQ DDQ

DDQ DDQ DDQ DDQ DDQ

A A

CY7C1370DV25 CY7C1372DV25

165-Ball FBGA Pinout

CY7C1370DV25 (512K × 36)

891011

V V

V V V

V V V V V

A AADV/LD

DDQ DDQ

DDQ DDQ DDQ

NC

DDQ DDQ DDQ DDQ DDQ

A

NC DQP

DQ

b

DQ

b

DQ

b

DQ

b

NC

DQ

a

DQ

a

DQ

a

DQ

a

NC

A

BW

1

BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

BW

c

BW

d

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

CE

b

CLK

a

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC A1

CEN

3

WE

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO TCKA0

OE A

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

CY7C1372DV25 (1M × 18)

891011

BW

1

b

NC

NC BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

CE CLK

a

V

SS

V

SS SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

A1

CEN

3

WE

V V

V V V

V V V V

V

NC

TDO

TCKA0

SS SS

SS SS SS

SS SS SS SS

SS

ADV/LD

OE

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD DD

V

DD

V

DD

V

DD

V

SS

A

A A

A

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A NC DQP NC NC NC NC

NC

DQ

a

DQ

a

DQ

a

DQ

a

NC

A

NC NC

b

DQ

b

DQ

b

DQ

b

DQ

b

ZZ

DQ

a

DQ

a

DQ

a

DQ

a

DQP

a

NC/288M

AA

A

NC

a

DQ

a

DQ

a

DQ

a

DQ

a

ZZ NCV NC NC

NC NC

NC/288M

AA

Document #: 38-05558 Rev. *D Page 5 of 27

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CY7C1370DV25 CY7C1372DV25

Pin Definitions

Pin Name I/O Type Pin Description

A0 A1 A

BW

a

BW

b

BW

c

BW

d

WE Input-

ADV/LD Input-

CLK Input-

CE

1

CE

2

CE

3

OE Input-

CEN Input-

DQ

S

DQP

X

MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

TDO JT AG ser ial

TDI JT AG ser ial

TMS Test Mode

TCK JTAG-Clock Clock input to the JTAG circuitry.

Input-

Synchronous

Input-

Synchronous

Clock Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Asynchronous

Synchronous

I/O-

Synchronous

I/O-

Synchronous

output

Synchronous

input

Synchronous

Select

Synchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK.

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BW

controls DQc and DQPc, BWd controls DQd and DQPd.

BW

c

controls DQa and DQPa, BWb controls DQb and DQPb,

a

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW . This signal must be asserted LOW to initiate a write sequence.

Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN new address can be loaded into the device for an access. After being deselected, ADV/LD

is asserted LOW) the internal burst counter is advanced. When LOW, a

should

be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to th e de vi ce . CL K is qu a l ified with CEN.

CLK is only recognized if CEN

is active LOW.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE3 to select/deselect the device.

2

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE3 to select/deselect the device.

1

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

and CE2 to select/deselect the device.

CE

1

Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE

is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected.

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN deselect the device, CEN

can be used to extend the previous cycle when required.

does not

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A controlled by OE as outputs. When HIGH, DQ automatically three-stated during the data portion of a write sequence, during the first clock when

during the previous clock rise of the read cycle. The direction of the pins is

[17:0]

and the internal control logic. When OE is asserted LOW, the pins can behave

–DQd are placed in a three-state condition. The outputs are

a

emerging from a deselected state, and when the device is deselected, regardless of the state of OE

.

Bidirectional Data Parity I/O lines. Functionally , these signals are identical to DQs. During write sequences, DQP and DQP

d

is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,

a

is controlled by BWd.

Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order.

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

Document #: 38-05558 Rev. *D Page 6 of 27

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Pin Definitions (continued)

Pin Name I/O Type Pin Description

V

DD

V

DDQ

V

SS

NC – No connects. This pin is not connected to the die. NC/(36M, 72M,

144M, 288M, 576M, 1G)

ZZ Input-

Power Supply Power supply inputs to the core of the device.

I/O Power

Power supply for the I/O circuitry.

Supply

Ground Ground for the device. Should be connected to ground of the system.

– These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M,

576M, and 1G densities.

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”

Asynchronous

condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.

CY7C1370DV25 CY7C1372DV25

Introduction

Functional Overview

The CY7C1370DV25 and CY7C1372DV25 are synchronous-pipelined Burst NoBL SRAMs desig ned specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t

) is 2.6 ns (250-MHz device).

CO

Accesses can be initiated by asserting all three Chip Enables (CE

, CE2, CE3) active at the rising edge of the clock. If Clock

1

Enable (CEN

) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE conduct byte write operations.

Write operations are qualified by the Write Enable (WE writes are simplified with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE asynchronous Output Enable (OE All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD

should be driven LOW once the device has been deselected in order to load a new address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN and CE signal WE

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) provided OE clock of the read access the output buffers are controlled by OE

and the internal control logic. OE must be driven LOW in

). If CEN is HIGH, the clock

). BWX can be used to

). All

, CE2, CE3) and an

1

) simplify depth expansion.

is asserted LOW, (2) CE1, CE2,

is active LOW. After the first

order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise.

Burst Read Accesses

The CY7C1370DV25 and CY7C1372DV25 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD

must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter i s determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD

will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN and CE is asserted LOW. The address presented is loaded into the

are ALL asserted active, and (3) the write signal WE

3

is asserted LOW, (2) CE1, CE2,

Address Register. The write signals are latched into the Control Logic block.

On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE allows the external logic to present the data on DQ (DQ for CY7C1372DV25). In addition, the address for the subse-

a,b,c,d

/DQP

for CY7C1370DV25 and DQ

a,b,c,d

input signal. This

and DQP

/DQP

a,b

quent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQ (DQ CY7C1372DV25) (or a subset for byte write operations, see

a,b,c,d

/DQP

for CY7C1370DV25 & DQ

a,b,c,d

a,b

/DQP

and DQP

a,b

for

Write Cycle Description table for details) inputs is latched into the device and the write is complete.

The data written during the write operation is controlled by BW (BW

for CY7C1370DV25 and BW

a,b,c,d

for CY7C1372DV25)

a,b

Document #: 38-05558 Rev. *D Page 7 of 27

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CY7C1370DV25 CY7C1372DV25

signals. The CY7C1370DV25/CY7C1372DV25 provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW

) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations.

Because the CY7C1370DV25 and CY7C1372DV25 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE deasserted HIGH before presenting data to the DQ (DQ for CY7C1372DV25) inputs. Doing so will three-state the

a,b,c,d

/DQP

for CY7C1370DV25 and DQ

a,b,c,d

output drivers. As a safety precaution, DQ (DQ for CY7C1372DV25) are automatically three-stated during the

a,b,c,d

/DQP

for CY7C1370DV25 and DQ

a,b,c,d

data portion of a write cycle, regardless of the state of OE

) can be

and DQP

/DQP

a,b

and DQP

/DQP

a,b

.

Burst Write Accesses

The CY7C1370DV25/CY7C1372DV25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD

must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE

) and WE inputs are ignored and the burst counter is incre-

CE

3

mented. The correct BW BW

for CY7C1372DV25) inputs must be driven in each

a,b

cycle of the burst write in order to write the correct bytes of

(BW

for CY7C1370DV25 and

a,b,c,d

, CE2, and

1

data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE for the duration of t

, CE2, and CE3, must remain inactive

1

after the ZZ input returns LOW.

ZZREC

Interleaved Burst Address Table (MODE = Floating or V

First

Address

A1,A0 A1,A0 A1,A0 A1,A0

00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00

Second

Address

DD

)

Address

Third

Fourth

Address

Linear Burst Address Table (MODE = GND)

First

Address

A1,A0 A1,A0 A1,A0 A1,A0

00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10

Second

Address

Third

Address

Fourth

Address

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Sleep mode standby current ZZ > VDD − 0.2V 80 mA Device operation to ZZ ZZ > VDD − 0.2V 2t ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ active to sleep current This parameter is sampled 2t

CYC

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

ns ns ns

Document #: 38-05558 Rev. *D Page 8 of 27

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CY7C1370DV25 CY7C1372DV25

Truth Table

[1, 2, 3, 4, 5, 6, 7]

Address

Operation

Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ

Deselect Cycle None H L L X X X L L-H Tri-state Continue Deselect Cycle None X L H X X X L L-H Tri-state Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q) Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q) NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-state Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-state Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D) Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D) NOP/Write Abort (Begin Burst) None L L L L H X L L-H Tri-state Write Abort (Continue Burst) Next X L H X H X L L-H Tri-state Ignore Clock Edge (Stall) Current X L X X X X H L-H – Sleep Mode None X H X X X X X X Tri-state

Partial Write Cycle Description

Function (CY7C1370DV25) WE BW

[1, 2, 3, 8]

d

BW

c

BW

b

BW

a

Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ Write Byte b – (DQ

and DQPa) LHHHL

a

and DQPb)LHHLH

b

Write Bytes b, a L H H L L Write Byte c – (DQ

and DQPc)LHLHH

c

Write Bytes c, a L H L H L Write Bytes c, b L H L L H Write Bytes c, b, a L H L L L Write Byte d – (DQ

and DQPd)LLHHH

d

Write Bytes d, a L L H H L Write Bytes d, b LLHLH Write Bytes d, b, a L L H L L Write Bytes d, c L L L H H Write Bytes d, c, a L L L H L Write Bytes d, c, b L L L L H Write All Bytes L L L L L

Notes:

1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE signifies that the desired byte write selects are asserted, see Write Cycle Descript i on table for details.

2. Write is defined by WE

3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

4. The DQ and DQP pins are controlled by the current cycle and the OE

= H inserts wait states.

5. CEN

6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Three-state when

7. OE OE

is inactive or when the device is deselected, and DQs = data when OE is active.

8. Table only lists a partial listing of the byte write combinations. Any Combina tion of BW

and BWX. See Write Cycle Description table for details.

Document #: 38-05558 Rev. *D Page 9 of 27

stands for ALL Chip Enables active. BWx = L signifies at least one Byt e Write Select is active, BWx = Valid

signal.

.

is valid. Appropriate write will be done based on which byte write is active.

X

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T

O

CY7C1370DV25 CY7C1372DV25

Function (CY7C1372DV25) WE

BW

b

Read H x x Write – No Bytes Written L H H Write Byte a – (DQ Write Byte b – (DQ

and DQPa)LHL

a

and DQPb)LLH

b

Write Both Bytes L L L

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1370DV25/CY7C1372DV25 incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.

The CY7C1370DV25/CY7C1372DV25 contains a TAP controller, instruction register , boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (V

) to prevent clocking of the device. TDI and TMS are inter-

SS

nally pulled up and may be unconnected. They may alternately be connected to V left unconnected. Upon power-up, the device will come up in

through a pull-up resistor. TDO should be

DD

a reset state which will not interfere with the operation of the device.

TAP Controller State Diagram

TEST-LOGIC

1

RESET

0

RUN-TEST/

IDLE

1

SELECT

DR-SCAN

1 1

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

0 0

EXIT2-DR

UPDATE-DR

1 0

1

0

0 0

1

1 1

0 0

0

1

IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

1

SELECT

1

0

1

0

1

0

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

0

Bypass Register

012

TDI TD

TCK

MS TAP CONTROLLER

Selection Circuitry

Instruction Register

012293031 ...

Identification Register

012..x ...

Boundary Scan Register

S

election

Circuitr

y

BW

a

The 0/1 next to each state represents the value of TMS at the rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Document #: 38-05558 Rev. *D Page 10 of 27

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (V rising edges of TCK. This RESET does not affect the operation

) for five

DD

of the SRAM and may be performed while the SRAM is operating.

At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

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CY7C1370DV25 CY7C1372DV25

TAP Registers

Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.

When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be pla ced betwee n the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (V

) when the BYPASS instruction is executed.

SS

Boundary Scan Register

The boundary scan register is connected to all the input and bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring.

The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table.

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.

EXTEST

The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction reg ister upon power-up or whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1 149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value th at will be captured. Repeatable results may not be possible.

To guarantee that the boundary scan registe r will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (t captured correctly if there is no way in a design to stop (o r slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK boundary scan register.

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in.

and tCH). The SRAM clock input might not be

CS

captured in the

Document #: 38-05558 Rev. *D Page 11 of 27

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123456

T

CY7C1370DV25 CY7C1372DV25

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruct ion is that it shortens the boundary scan path when multiple devices are connected together on a board.

EXTEST Output Bus Tri-State

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #85 (for 119-BGA package) or bit #89 (for 165-fBGA package). When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the

TAP Timin g

Test Clock

(TCK)

t

TMSS

t

TH

t

TMSH

current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR,” the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

t

TL

t

CYC

est Mode Select

(TMS)

t

TDIS

TDIH

Test Data-In

(TDI)

t

TDOX

t

TDOV

Test Data-Out

(TDO)

DON’T CARE UNDEFINED

Document #: 38-05558 Rev. *D Page 12 of 27

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TAP AC Switching Characteristics Over the Operating Range

[9, 10]

Parameter Description Min. Max. Unit

Clock

t

TCYC

t

TF

t

TH

t

TL

TCK Clock Cycle Time 50 ns TCK Clock Frequency 20 MHz TCK Clock HIGH time 20 ns TCK Clock LOW time 20 ns

Output Times

t

TDOV

t

TDOX

TCK Clock LOW to TDO Valid 10 ns TCK Clock LOW to TDO Invalid 0 ns

Set-up Times

t

TMSS

t

TDIS

t

CS

TMS Set-up to TCK Clock Rise 5 ns TDI Set-up to TCK Clock Rise 5 ns Capture Set-up to TCK Rise 5 ns

Hold Times

t

TMSH

t

TDIH

t

CH

Notes:

and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

9. t

CS

10.Test conditions are specified using the load in TAP AC test Conditions. t

TMS Hold after TCK Clock Rise 5 ns TDI Hold after Clock Rise 5 ns Capture Hold after Clock Rise 5 ns

= 1 ns.

R/tF

Document #: 38-05558 Rev. *D Page 13 of 27

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T

F

CY7C1370DV25 CY7C1372DV25

2.5V TAP AC Test Conditions

Input pulse levels................................................ VSS to 2.5V

2.5V TAP AC Output Load Equivalent

1.25V

Input rise and fall time.....................................................1 ns

Input timing reference levels.........................................1.25V

Output reference levels.................................................1.25V

Test load termination supply voltage.............................1.25V

DO

Z = 50Ω

O

50Ω

20p

TAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)

Parameter Description Test Conditions Min. Max. Unit

V V V V V V I

OH1 OH2 OL1 OL2 IH IL

X

Output HIGH Voltage IOH = –1.0 mA, V Output HIGH Voltage IOH = –100 µA, V Output LOW Voltage IOL = 8.0 mA, V Output LOW Voltage IOL = 100 µA V Input HIGH Voltage V Input LOW Voltage V Input Load Current GND < VIN < V

[11]

= 2.5V 2.0 V

DDQ

= 2.5V 2.1 V

DDQ

= 2.5V 0.4 V

DDQ

= 2.5V 0.2 V

DDQ

= 2.5V 1.7 VDD + 0.3 V

DDQ

= 2.5V –0.3 0.7 V

DDQ

–5 5 µA

Scan Register Sizes

Register Name

Bit Size (x18)

Bit Size (x36)

Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 85 85 Boundary Scan Order (165-ball fBGA package) 89 89

Identification Register Definitions

Instruction Field CY7C1372DV25 CY7C1370DV25 Description

Revision Number (31:29) 000 000 Reserved for version number. Cypress Device ID (28:12) 01011001000100101 01011001000010101 Reserved for future use. Cypress JEDEC ID (11:1) 00000110100 00000110100 All ows unique identification of

SRAM vendor.

ID Register Presence (0) 1 1 Indicate the presence of an ID

Note:

11.All voltages referenced to V

(GND).

SS

register.

Document #: 38-05558 Rev. *D Page 14 of 27

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CY7C1370DV25 CY7C1372DV25

Identification Codes

Instruction Code Description

EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI an d

SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

Forces all SRAM outputs to High-Z state.

TDO. This operation does not affect SRAM operations.

Forces all SRAM output drivers to a High-Z state.

Does not affect SRAM operation.

operations.

119-Ball BGA Boundary Scan Order

Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID

1 2T4 24E7 46A4 68M2 3T5 25D7 47G3 69N1 4T6 26H7 48C3 70P1 5R5 27G6 49B2 71K1 6L5 28E6 50B3 72L2 7R6 29D6 51A3 73 8U6 30C7 52C2 74P2

9R7 31B7 53A2 75R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36 G5 58 F2 80 R2 15 K6 37 B6 59 G1 81 T3 16 P7 38 D4 60 H2 82 L4 17 N6 39 B4 61 D1 83 N4 18 L6 40 F4 62 E2 84 P4 19 K7 41 M4 63 G2 85 Internal 20 J5 42 A5 64 H1 21 H6 43 K4 65 J3 22 G7 44 E4 66 2K

H4

23 F6 45 G4 67 L1

[12, 13]

N2

Notes:

12.Balls which are NC (No Connect) are pre-set LOW.

13.Bit# 85 is pre-set HIGH.

Document #: 38-05558 Rev. *D Page 15 of 27

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CY7C1370DV25 CY7C1372DV25

165-Ball FBGA Boundary Scan Order

Bit # Ball ID Bit # Ball ID Bit # Ball ID

1N6 31D10 61G1 2N7 32C11 62D2 3N10 33A11 63 E2 4P11 34B11 64 F2 5P8 35A10 65G2 6R8 36B10 66H1 7R9 37A9 67H3 8P9 38B9 68J1

9P10 39C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9 52 A2 82 R3 23 H10 53 B2 83 P2 24 G11 54 C2 84 R4 25 F11 55 B1 85 P4 26 E11 56 A1 86 N5 27 D11 57 C1 87 P6 28 G10 58 D1 88 R6 29 F10 59 E1 89 Internal 30 E10 60 F1

[12, 14]

Note:

14.Bit# 89 is pre-set HIGH.

Document #: 38-05558 Rev. *D Page 16 of 27

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CY7C1370DV25 CY7C1372DV25

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V Supply Voltage on V

DC to Outputs in Tri-State...................–0.5V to V

Relative to GND........–0.5V to +3.6V

DD

Relative to GND......–0.5V to +V

DDQ

DD

+ 0.5V

DC Input Voltage...................................–0.5V to VDD + 0.5V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current...................................... ... ........... > 200 mA

Operating Range

Range

Temperature

Commercial 0°C to +70°C 2.5V ±5%

Ambient

VDD/V

DDQ

Industrial –40°C to +85°C

Electrical Characteristics Over the Operating Range

[15, 16]

Parameter Description Test Conditions Min. Max. Unit

V V V V V V I

I I

DD DDQ OH OL IH IL

X

OZ DD

Power Supply Voltage 2.375 2.625 V I/O Supply Voltage for 2.5V I/O 2.375 V Output HIGH Voltage for 2.5V I/O, I

= −1.0 mA 2.0 V

OH

DD

Output LOW Voltage for 2.5V I/O, IOL= 1.0 mA 0.4 V Input HIGH Voltage Input LOW Voltage Input Leakage Current

except ZZ and MODE Input Current of MODE Input = V

Input Current of ZZ Input = V

Output Leakage Current GND ≤ VI ≤ V VDD Operating Supply V

[17]

for 2.5V I/O 1.7 VDD + 0.3V V

[17]

for 2.5V I/O –0.3 0.7 V GND ≤ VI ≤ V

SS

Input = V

f = f

= Max., I

DD

MAX

DD SS DD

= 1/t

DDQ

Output Disabled –5 5 µA

DD,

OUT

CYC

= 0 mA,

4.0-ns cycle, 250 MHz 350 mA

5.0-ns cycle, 200 MHz 300 mA

–5 5 µA

–30 µA

–5 µA

5 µA

30 µA

6.0-ns cycle, 167 MHz 275 mA

I

SB1

I

SB2

I

SB3

I

SB4

Automatic CE Power-down Current—TTL Inputs

Automatic CE Power-down Current—CMOS Inputs

Automatic CE Power-down Current—TTL Inputs

Max. VDD, Device Deselected, V

≥ VIH or VIN ≤ VIL, f = f

1/t

IN

CYC

MAX

Max. VDD, Device Deselected, V

≤ 0.3V or VIN > V

IN

f = 0

DDQ

− 0.3V,

Max. VDD, Device Deselected, V

≤ 0.3V or VIN > V

IN

MAX

= 1/t

f = f

CYC

DDQ

− 0.3V,

Max. VDD, Device Deselected, V

≥ VIH or VIN ≤ VIL, f = 0

IN

4.0-ns cycle, 250 MHz 160 mA

=

5.0-ns cycle, 200 MHz 150 mA

6.0-ns cycle, 167 MHz 140 mA All speed grades 70 mA

4.0-ns cycle, 250 MHz 135 mA

5.0-ns cycle, 200 MHz 130 mA

6.0-ns cycle, 167 MHz 125 mA All speed grades 80 mA

V

Notes:

15.Overshoot: V

16.T

Power-up

17.Tested initially and af ter any design or process change that may affect these parameters.

(AC) < V

IH

: Assumes a linear ramp from 0V to V

+1.5V (Pulse width less than t

DD

Document #: 38-05558 Rev. *D Page 17 of 27

/2), undershoot: VIL(AC)> –2V (Pulse width less than t

CYC

(min.) within 200 ms. During this time VIH < VDD and V

DD

DDQ

< VDD.

CYC

/2).

[+] Feedback

CY7C1370DV25 CY7C1372DV25

Capacitance

[17]

Parameter Description Test Conditions

CIN Input Capacitance TA = 25°C, f = 1 MHz,

V

= 2.5V.

C C

CLK I/O

Clock Input Capacitance 5 8 9 pF Input/Output Capacitance 5 8 9 pF

Thermal Resistance

[17]

V

DD DDQ

= 2.5V

Parameter Description T est Conditions

Θ

JA

Θ

JC

Thermal Resistance (Junction to Ambient)

Thermal Resistance (Junction to Case)

T est conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51.

AC Test Loads and Waveforms

2.5V I/O Test Load

OUTPUT

Z

= 50Ω

0

V

(a)

T

R

= 1.25V

= 50Ω

L

2.5V

OUTPUT

5pF

INCLUDING

JIG AND

SCOPE

R = 1667Ω

(b)

R = 1538Ω

100 TQFP

Package

119 BGA Package

165 FBGA

Package Unit

5 8 9 pF

100 TQFP

Package

119 BGA Package

165 FBGA

Package Unit

28.66 23.8 20.7 °C/W

4.08 6.2 4.0 °C/W

V

GND

DDQ

≤ 1 ns

ALL INPUT PULSES

10%

90%

10%

(c)

≤ 1 ns

Document #: 38-05558 Rev. *D Page 18 of 27

[+] Feedback

CY7C1370DV25 CY7C1372DV25

Switching Characteristics Over the Operating Range

Parameter Description

[18]

t

Power

Clock

t

CYC

F

MAX

t

CH

t

CL

Output Times

t

CO

t

EOV

t

DOH

t

CHZ

t

CLZ

t

EOHZ

t

EOLZ

Set-up Times

t

AS

t

DS

t

CENS

t

WES

t

ALS

t

CES

Hold Times

t

AH

t

DH

t

CENH

t

WEH

t

ALH

t

CEH

VCC (typical) to the first access read or write 1 1 1 ms

Clock Cycle Time 4.0 5 6 ns Maximum Operating Frequency 250 200 167 MHz Clock HIGH 1.7 2.0 2.2 ns Clock LOW 1.7 2.0 2.2 ns

Data Output Valid After CLK Rise 2.6 3.0 3.4 ns OE LOW to Output Valid 2.6 3.0 3.4 ns Data Output Hold After CLK Rise 1.0 1.3 1.3 ns Clock to High-Z Clock to Low-Z OE HIGH to Output High-Z OE LOW to Output Low-Z

[19, 20, 21]

Address Set-up Before CLK Rise 1.2 1.4 1.5 ns Data Input Set-up Before CLK Rise 1.2 1.4 1.5 ns CEN Set-up Before CLK Rise 1.2 1.4 1.5 ns WE, BWx Set-up Before CLK Rise 1.2 1.4 1.5 ns ADV/LD Set-up Before CLK Rise 1.2 1.4 1.5 ns Chip Select Set-up 1.2 1.4 1.5 ns

Address Hold After CLK Rise 0.3 0.4 0.5 ns Data Input Hold After CLK Ri se 0.3 0.4 0.5 ns CEN Hold After CLK Rise 0.3 0.4 0.5 ns WE, BWx Hold After CLK Rise 0.3 0.4 0.5 ns ADV/LD Hold after CLK Rise 0.3 0.4 0.5 ns Chip Select Hold After CLK Rise 0.3 0.4 0.5 ns

[22, 23]

–250 –200 –167

UnitMin. Max. Min. Max. Min. Max.

2.6 3.0 3.4 ns

1.0 1.3 1.3 ns

2.6 3.0 3.4 ns

0 0 0 ns

Notes:

18.This part has a voltage regulator internally; t be initiated.

, t

19.t

CHZ

CLZ

20.At any given voltage and temperature, t data bus. These specifications do not imp ly a bus contentio n condition, but reflect parame ters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

21.This parameter is sampled and not 100% tested.

22.Timing reference 1.25V when V

23.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

EOLZ

, and t

are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

EOHZ

DDQ

EOHZ

= 2.5V.

Document #: 38-05558 Rev. *D Page 19 of 27

is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can

Power

is less than t

EOLZ

and t

is less than t

CHZ

to eliminate bus contention between SRAMs when sharing the same

CLZ

[+] Feedback

Switching Waveforms

123456789

10

I

CE

x

[24, 25, 26]

t

CENS

t

CES

t

CENH

t

CEH

Read/Write/Timing

CLK

CEN

ADV/LD

WE

BW

CY7C1370DV25 CY7C1372DV25

t

CYC

t

CL

CH

ADDRESS

Data

n-Out (DQ)

OE

A1 A2

t

AH

AS

WRITE

D(A1)

WRITE

D(A2)

A3

t

DH

DS

D(A1) D(A2) D(A5)Q(A4)Q(A3)

BURST WRITE

D(A2+1)

READ Q(A3)

A4

t

CO

t

CLZ

D(A2+1)

READ

Q(A4)

t

BURST

READ

Q(A4+1)

DOH

A5 A6 A7

t

OEHZ

t

WRITE

D(A5)

OEV

t

OELZ

t

CHZ

Q(A4+1)

t

DOH

READ

Q(A6)

DON’T CARE UNDEFINED

Notes:

24.For this waveform ZZ is tied LOW.

25.When CE

26.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Inte rleaved). Burst operations are optional.

is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

WRITE

D(A7)

Q(A6)

DESELECT

Document #: 38-05558 Rev. *D Page 20 of 27

[+] Feedback

Switching Waveforms (continued)

45678910

123

A

NOP,STALL and DESELECT Cycles

CLK

CEN

CE

ADV/LD

WE

BWx

[24, 25, 27]

CY7C1370DV25 CY7C1372DV25

ADDRESS

Data

In-Out (DQ)

ZZ Mode Timing

A1

D(A1)

[28, 29]

READ Q(A2)

CLK

ZZ

I

SUPPLY

LL INPUTS

(except ZZ)

A2

STALL NOP READ

t

ZZ

t

ZZI

I

DDZZ

A3 A4

D(A1) Q(A2) Q(A3)

READ Q(A3)

WRITE

D(A4)

DON’T CARE UNDEFINED

STALLWRITE

A5

D(A4)

Q(A5)

t

ZZREC

t

RZZI

DESELECT or READ Only

t

CHZ

Q(A5)

DESELECT CONTINUE

DESELECT

Outputs (Q)

Notes:

27.The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN

28.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

29.I/Os are in High-Z when exiting ZZ sleep mode.

Document #: 38-05558 Rev. *D Page 21 of 27

High-Z

DON’T CARE

being used to create a pause. A write is not performed during this cycle

[+] Feedback

CY7C1370DV25 CY7C1372DV25

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

Speed

(MHz) Ordering Code

167 CY7C1370DV25-167AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1372DV25-167AXC CY7C1370DV25-167BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-167BGC CY7C1370DV25-167BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1372DV25-167BGXC CY7C1370DV25-167BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) CY7C1372DV25-167BZC CY7C1370DV25-167BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) CY7C1372DV25-167BZXC CY7C1370DV25-167AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial CY7C1372DV25-167AXI CY7C1370DV25-167BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-167BGI CY7C1370DV25-167BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1372DV25-167BGXI CY7C1370DV25-167BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) CY7C1372DV25-167BZI CY7C1370DV25-167BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) CY7C1372DV25-167BZXI

200 CY7C1370DV25-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1372DV25-200AXC CY7C1370DV25-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-200BGC CY7C1370DV25-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1372DV25-200BGXC CY7C1370DV25-200BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) CY7C1372DV25-200BZC CY7C1370DV25-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) CY7C1372DV25-200BZXC CY7C1370DV25-200AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial CY7C1372DV25-200AXI CY7C1370DV25-200BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-200BGI CY7C1370DV25-200BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1372DV25-200BGXI CY7C1370DV25-200BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) CY7C1372DV25-200BZI CY7C1370DV25-200BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) CY7C1372DV25-200BZXI

visit www.cypress.com for actual products offered.

Package

Diagram Part and Package Type

Lead-Free

Operating

Range

Document #: 38-05558 Rev. *D Page 22 of 27

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CY7C1370DV25 CY7C1372DV25

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

250 CY7C1370DV25-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1372DV25-250AXC CY7C1370DV25-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-250BGC CY7C1370DV25-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1372DV25-250BGXC CY7C1370DV25-250BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) CY7C1372DV25-250BZC CY7C1370DV25-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) CY7C1372DV25-250BZXC CY7C1370DV25-250AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial CY7C1372DV25-250AXI CY7C1370DV25-250BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1372DV25-250BGI CY7C1370DV25-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1372DV25-250BGXI CY7C1370DV25-250BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) CY7C1372DV25-250BZI CY7C1370DV25-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) CY7C1372DV25-250BZXI

visit www.cypress.com for actual products offered.

Lead-Free

Document #: 38-05558 Rev. *D Page 23 of 27

[+] Feedback

Package Diagrams

R 0.08 MIN.

0.20 MAX.

0.25

GAUGE PLANE

0°-7°

0.60±0.15

1.00 REF.

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)

16.00±0.20

14.00±0.10

20.00±0.10

22.00±0.20

100

1

30

31 50

0° MIN.

R 0.08 MIN.

0.20 MAX.

0.20 MIN.

A

DETAIL

81

80

0.30±0.08

0.65 TYP.

51

STAND-OFF

0.05 MIN.

0.15 MAX.

SEATING PLANE

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

CY7C1370DV25 CY7C1372DV25

1.40±0.05

12°±1°

(8X)

0.20 MAX.

1.60 MAX.

0.10

51-85050-*B

SEE DETAIL

A

Document #: 38-05558 Rev. *D Page 24 of 27

[+] Feedback

Package Diagrams (continued)

119- B al l BG A (1 4 x 22 x 2.4 mm) (51-85115)

CY7C1370DV25 CY7C1372DV25

51-85115-*B

Document #: 38-05558 Rev. *D Page 25 of 27

[+] Feedback

Package Diagrams (continued)

TOP VIEW

PIN 1 CORNER

A

B

C

D

E

F

G

H

J

B

K

L

M

N

P

R

B

0.53±0.05

C

0.36

J

K

L

M

N

P

R

SEATING PLANE

C

13.00±0.10

SEATING PLANE

13.00±0.10

15.00±0.10

A

0.25 C

15.00±0.10

A

0.25 C

0.53±0.05

0.36

165-Ball FBGA (13 x 15 x 1.4 mm) (51-85 180)

1110986754321

14.00

15.00±0.10

A

0.15(4X)

1.40 MAX.

0.15 C

1.40 MAX.

11

1.00

14.00

7.00

5.00

B

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

BOTTOM VIEW

Ø0.05 M C

Ø0.25MCAB

Ø0.50 (165X)

5.00

10.00

13.00±0.10

CY7C1370DV25 CY7C1372DV25

PIN1CORNER

PIN 1 CORNER

Ø0.05 M C

Ø0.25 M C A B

-0.06

-

0.06

Ø0.50 (165X)

+0.14

1

2345678910

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

1.00

10.00

51-85180-*A

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05558 Rev. *D Page 26 of 27

© Cypress Semiconductor Corporation, 2006. The information contained herein is su bj ect to ch an ge wi t hou t notice. Cypress Semiconductor Corporation assumes no responsibility for th e u se of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypre ss does not aut horize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

0.35±0.06

[+] Feedback

CY7C1370DV25 CY7C1372DV25

Document History Page

Document Title: CY7C1370DV25/CY7C1372DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05558

REV. ECN No. Issue Date

** 254509 See ECN RKF New data sheet

*A 288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

*B 326078 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as

*C 418125 See ECN NXR Converted from Preliminary to Final

*D 475677 See ECN VKN Added th e Maximum Rating for Supply Voltage on V

Orig. of

Change Description of Change

non-compliance with 1149.1 Removed 225 Mhz Speed Bin Added lead-free information for 100-Pin TQFP , 119 BGA and 165 FBGA package Added comment of ‘Lead-free BG packages availability’ below the Ordering Information

per JEDEC standard Added description on EXTEST Output Bus Tri-State Changed description on the Tap Instruction Set Overview and Extest Changed Θ

4.08 °C/W respectively Changed Θ °C/W respectively Changed Θ

4.0 °C/W respectively Modified V Removed comment of ‘Lead-free BG packages availability’ below the

and Θ

JA

and Θ

JA

and Θ

JA

OL, VOH

for TQFP Package from 31 and 6 °C/W to 28.66 and

JC

for BGA Package from 45 and 7 °C/W to 23.8 and 6.2

JC

for FBGA Package from 46 and 3 °C/W to 20.7 and

JC

test conditions

Ordering Information Updated Ordering Information Table

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed the description of I Current on page# 18

from Input Load Current to Input Leakage

X

Changed the IX current values of MODE on page # 18 from –5 µA and 30 µA to –30 µA and 5 µA Changed the IX current values of ZZ on page # 18 from –30 µA and 5 µA to –5 µA and 30 µA Changed V Updated Ordering Information Table

Changed t AC Switching Characteristics table.

< V

to VIH < VDDon page # 18

DD

from 25 ns to 20 ns and t

TL

TH

IH

, t

from 5 ns to 10 ns in TAP

TDOV

Updated the Ordering Information table.

Relative to GND.

DDQ

Document #: 38-05558 Rev. *D Page 27 of 27

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Cypress Semiconductor CY7C1370DV25, CY7C1372DV25 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual