a
b
c
d
C
CY7C1370D
CY7C1372D
18-Mbit (512K x 36/1M x 18) Pipelined
SRAM with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 M Hz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• 3.3V core power supply (VDD)
• 3.3V/2.5V I/O power supply(V
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN
) pin to suspend operation
• Synchronous self-timed writes
• Available in JEDEC-standard lead-free 100-pin TQFP,
lead-free and non-lead-free 119-Ball BGA and 165-Ball
FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
DDQ
)
Functional Description
The CY7C1370D and CY7C1372D are 3.3V, 512K x 36 and
1M x 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL™) logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations
with no wait states. The CY7C1370D and CY7C1372D are
equipped with the advanced (NoBL) logic requi red to enable
consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1370D and CY7C1372D are
pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
–BWd for CY7C1370D and BWa–BWb for CY7C1372D)
(BW
a
and a Write Enable (WE
) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
) signal,
Logic Block Diagram-CY7C1370D (512K x 36)
A0, A1, A
MODE
CLK
C
EN
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
I
M
S
T
P
E
S
R
S
E
E
REGISTER 0
INPUT
O
D
U
T
A
P
T
U
A
T
B
S
T
E
E
R
I
N
G
E
DQs
U
DQP
F
DQP
F
DQP
E
DQP
R
S
E
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05555 Rev. *F Revised June 28, 2006
[+] Feedback
a
b
C
Logic Block Diagram-CY7C1372D (1M x 18)
CY7C1370D
CY7C1372D
CLK
EN
A0, A1, A
MODE
C
ADV/LD
BW
a
BW
b
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1
D1D0Q1
A0
BURST
ADV/LD
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
LOGIC
C
Q0
A1'
A0'
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
U
T
P
S
U
E
T
N
S
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
E
INPUT
REGISTER 0
O
U
T
P
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
G
DQs
DQP
DQP
E
E
OE
CE1
CE2
READ LOGIC
CE3
ZZ
Sleep
Control
Selection Guide
250 MHz 200 MHz 167 MHz Unit
Maximum Access Time 2.6 3.0 3.4 ns
Maximum Operating Current 350 300 275 mA
Maximum CMOS Standby Current 70 70 70 mA
Document #: 38-05555 Rev. *F Page 2 of 28
[+] Feedback
Pin Configurations
a
100-pin TQFP Pinout
CY7C1370D
CY7C1372D
DQPc
DQc
DQc
V
DDQ
V
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
V
DDQ
DQd
DQd
DQPd
1CE2
A
A
CE
BWd
BWc
3
CE
VDDV
SS
CLKWECEN
BWa
BWb
100999897969594939291908988878685848382
1
2
3
4
5
SS
6
7
8
9
10
11
12
13
14
15
16
CY7C1370D
(512K × 36)
17
18
19
20
21
22
23
24
25
SS
26
27
28
29
30
31323334353637383940414243444546474849
OE
A
ADV/LD
A
A
A
81
DDQ
SS
SS
DDQ
SS
DD
DDQ
SS
SS
DDQ
NC
NC
NC
V
DDQ
V
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
NC
V
DD
NC
V
DQb
DQb
V
DDQ
V
DQb
DQb
DQPb
NC
V
V
DDQ
NC
NC
NC
SS
SS
SS
SS
DQPb
80
DQb
79
DQb
78
V
77
V
76
DQb
75
DQb
74
DQb
73
DQb
72
V
71
V
70
DQb
69
DQb
68
V
67
NC
66
V
65
ZZ
64
DQa
63
DQa
62
V
61
V
60
DQa
59
DQa
58
DQa
57
DQa
56
V
55
V
54
DQa
53
DQa
52
DQPa
51
50
1CE2
A
A
CE
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
bBWa
3
CE
BW
NC
NC
CY7C1372D
(1M × 18)
VDDV
SS
CLKWECEN
OE
A
A
ADV/LD
A
A
81
A
80
NC
79
NC
78
V
77
DDQ
V
SS
76
NC
75
DQP
74
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
AAA
MODE
0
A
A1A
SS
DD
V
V
NC(144)
NC(288)
AAA
A
NC(72)
NC(36)
A
A
A
A
AAA
MODE
1A0
A
AAA
A
DD
SS
V
V
NC(144)
NC(288)
A
NC(36)
NC(72)
A
A
Document #: 38-05555 Rev. *F Page 3 of 28
[+] Feedback
Pin Configurations (continued)
CY7C1370D
CY7C1372D
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/576M
NC/1G
DQ
c
DQ
c
V
DDQ
DQ
c
DQ
c
V
DDQ
DQ
d
DQ
d
V
DDQ
DQ
d
DQ
d
NC/144M
NC
V
DDQ
V
DDQ
NC/576M
NC/1G
b
NC
V
DDQ
NC
DQ
b
V
DDQ
NC
DQ
b
V
DDQ
DQ
b
NC
NC/144M
NC/72M
V
DDQ
119-Ball BGA
CY7C1370D (512K x 36)
Pinout
2345671
AA AAAV
CE
2
A
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQd
DQ
d
DQP
d
A
NC/72M
TMS
A
A
V
SS
V
SS
V
SS
BW
V
SS
NC
V
SS
BW
V
SS
V
SS
V
SS
MODE
A
ADV/LD
V
DD
NC DQP
CE
1
OE
c
A
WE
V
DD
CLK
NC
d
CEN
A1
A0 V
V
DD
A NC/36M
TCK
ACE3NC
AANC
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
BW
V
SS
V
SS
SS
DQ
b
DQ
b
DQ
DQ
DQ
DQ
DQ
DQ
b
b
DD
a
a
a
a
b
a
DQP
NC
A
NCTDI TDO V
DDQ
DQ
b
a
DQ
V
DQ
DQ
V
DQ
DQ
V
DQ
DQ
b
b
DDQ
b
b
DDQ
a
a
DDQ
a
a
NC/288MA
ZZ
DDQ
CY7C1372D (1M x 18)
2345671
AA AAAV
CE
A
NCDQ
DQ
NC
DQ
NC
V
DD
DQ
NC
DQ
NC
DQP
A
A
TMS
2
b
b
b
b
b
A
A
V
SS
V
SS
V
SS
BW
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
MODE
A
ADV/LD
V
DD
NC NCDQP
CE
1
OE
b
ANCNC
WE
V
DD
CLK
NC NC
CEN
A1
A0 V
V
DD
NC/36M
A
AANC
V
SS
V
SS
V
SS
V
SS
NC V
SS
BW
a
V
SS
V
SS
SS
NC
A
TCK
CE
3
NC
DQ
a
DQ
a
DD
NCV
DQ
a
NC V
DQ
a
NC
A
A
NCTDI TDO V
a
DDQ
NC
DQ
a
V
DDQ
DQ
a
NC
V
DDQ
DQ
a
DDQ
NC
DQ
a
NC/288M
ZZ
DDQ
Document #: 38-05555 Rev. *F Page 4 of 28
[+] Feedback
Pin Configurations (continued)
165-Ball FBGA Pinout
CY7C1370D (512K x 36)
CY7C1370D
CY7C1372D
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2345671
NC/576M
NC/1G
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
NC
DQ
d
DQ
d
DQ
d
DQ
d
DQP
d
NC/144M
MODE
A
A
NC
DQ
c
DQ
c
DQ
c
DQ
c
NC
DQ
d
DQ
d
DQ
d
DQ
d
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
A
BW
BW
V
V
V
V
V
V
V
V
V
V
b
a
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
c
d
NC
TDI
TMS
CY7C1372D (1M x 18)
2345671
NC/576M
NC/1G
NC
NC
NC V
NC
NC
NC
DQ
b
DQ
b
DQ
b
DQ
b
DQP
b
NC/144M
MODE
A
A
NC
DQ
b
DQ
b
DQ
b
DQ
b
NC
NC
NC
NC
NC
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
BW
1
b
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
A
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
a
891011
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
CE
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCKA0
V
V
V
V
V
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
A
NC DQP
DQ
DQ
DQ
DQ
DQ
b
DQ
b
DQ
b
DQ
b
NC
a
a
a
a
DQ
DQ
DQ
DQ
DQP
NC/288M
DQ
DQ
DQ
DQ
NC
A
NC
NC
b
b
b
b
b
ZZ
a
a
a
a
a
AA
891011
CE
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCKA0
A A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
NC
NC DQP
NC
NC
NC
NC
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
a
a
a
a
A
NCV
NC
NC
NC
NC
NC/288M
A
a
a
a
a
a
ZZ
AA
Document #: 38-05555 Rev. *F Page 5 of 28
[+] Feedback
CY7C1370D
CY7C1372D
Pin Definitions
Pin Name I/O Type Pin Description
A0
A1
A
BW
a
BW
b
BW
c
BW
d
WE Input-
ADV/LD Input-
CLK Input-
CE
1
CE
2
CE
3
OE Input-
CEN Input-
DQ
S
DQP
X
MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order .
TDO JT AG ser ial
TDI JT AG ser ial
TMS Test Mode
TCK JTAG-Clock Clock input to the JTAG circuitry.
V
DD
Input-
Synchronous
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
controls DQc and DQPc, BWd controls DQd and DQPd.
BW
c
controls DQa and DQPa, BWb controls DQb and DQPb,
a
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
Synchronous
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
Synchronous
When HIGH (and CEN
is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD
be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
CLK is only recognized if CEN
Chip Enable 1 Input, active LOW . Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW . Sampled on the rising edge of CLK. Used in conjunction with
and CE2 to select/deselect the device.
CE
1
is active LOW.
Output Enable, active LOW. Comb ined with the synchronous logic block inside the device to
Asynchronous
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE
the data portion of a write sequence, during the first clock when emerging from a deselected
state and when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
Synchronous
I/O-
Synchronous
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
deselect the device, CEN
can be used to extend the previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
controlled by OE
as outputs. When HIGH, DQ
ically tri-stated during the data portion of a write seq uence, during the fi rst clock when emerging
during the previous clock rise of the read cycle. The direction of the pins is
[17:0]
and the internal control logic. When OE is asserted LOW, the pins can behave
–DQd are placed in a tri-state condition. The outputs are automat-
a
from a deselected state, and when the device is deselected, regardless of the state of OE
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally , these signals are identical to DQs. During write
sequences, DQP
and DQP
d
is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,
a
is controlled by BWd.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
output
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
input
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Select
Synchronous
Power Supply Power supply inputs to the core of the device.
should
is masked during
does not
.
Document #: 38-05555 Rev. *F Page 6 of 28
[+] Feedback
Pin Definitions (continued)
Pin Name I/O Type Pin Description
V
DDQ
V
SS
NC – No connects. This pin is not connected to the die.
NC/(36M,72M,
144M, 288M,
576M, 1G)
ZZ Input-
I/O Power
Power supply for the I/O circuitry.
Supply
Ground Ground for the device. Should be connected to ground of the system.
– These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M,
576M and 1G densities.
ZZ “sleep” Input. This active HIGH input pla ces the device in a non-time critical “s leep” condition
Asynchronous
with data integrity preserved. During normal operation, this pin can be connected to V
floating. ZZ pin has an internal pull-down.
CY7C1370D
CY7C1372D
or left
SS
Introduction
Functional Overview
The CY7C1370D and CY7C1372D are synchronous-pipelined
Burst NoBL SRAMs designed specifically to eliminate wait
states during Write/Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of
the clock. The clock signal is qualified with the Clock Enable
input signal (CEN
recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
) is 2.6 ns (250-MHz device).
CO
Accesses can be initiated by asserting all three Chip Enables
(CE
, CE2, CE3) active at the rising edge of the clock. If Clock
1
Enable (CEN
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE
conduct byte write operations.
Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD
should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.6 ns
(250-MHz device) provided OE
clock of the read access the output buffers are controlled by
OE
and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
). If CEN is HIGH, the clock signal is not
) is active LOW and ADV/LD is asserted LOW,
). BWX can be used to
). All
, CE2, CE3) and an
1
) simplify depth expansion.
is asserted LOW, (2) CE1, CE2,
is active LOW. After the first
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will tri-state following the
next clock rise.
Burst Read Accesses
The CY7C1370D and CY7C1372D have an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD
must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter i s
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal
burst counter regardless of the state of chip enables inputs or
WE
. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented is loaded into the
are ALL asserted active, and (3) the write signal WE
3
is asserted LOW, (2) CE1, CE2,
Address Register. The write signals are latched into the
Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
allows the external logic to present the data on DQ
(DQ
CY7C1372D). In addition, the address for the subsequent
a,b,c,d
/DQP
for CY7C1370D and DQ
a,b,c,d
input signal. This
and DQP
a,b
/DQP
a,b
for
access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ
(DQ
CY7C1372D) (or a subset for byte write operations, see Write
a,b,c,d
/DQP
for CY7C1370D & DQ
a,b,c,d
a,b
and DQP
/DQP
a,b
for
Cycle Description table for details) inputs is latched into the
device and the write is complete.
The data written during the write operation is controlled by BW
(BW
signals. The CY7C1370D/CY7C1372D provides byte write
for CY7C1370D and BW
a,b,c,d
for CY7C1372D)
a,b
capability that is described in the Write Cycle Description table.
Document #: 38-05555 Rev. *F Page 7 of 28
[+] Feedback
CY7C1370D
CY7C1372D
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW
) input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple byte write operations.
Because the CY7C1370D and CY7C1372D are common I/O
devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE
HIGH before presenting data to the DQ
(DQ
CY7C1372D) inputs. Doing so will tri-state the output drivers.
a,b,c,d
/DQP
for CY7C1370D and DQ
a,b,c,d
As a safety precaution, DQ and DQP (DQ
CY7C1370D and DQ
automatically tri-stated during the data portion of a write cycle,
a,b
/DQP
a,b
) can be deasserted
and DQP
/DQP
a,b
/DQP
a,b,c,d
for CY7C1372D) are
a,b
a,b,c,d
for
for
regardless of the state of OE.
Burst Write Accesses
The CY7C1370D/CY7C1372D has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four write operations without reasserting the
address inputs. ADV/LD
must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD
quent clock rise, the chip enables (CE
WE
inputs are ignored and the burst counter is incremented.
The correct BW
CY7C1372D) inputs must be driven in each cycle of the burst
(BW
a,b,c,d
is driven HIGH on the subse-
, CE2, and CE3) and
1
for CY7C1370D and BW
a,b
for
write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
, CE2, and CE3, must remain inactive
1
after the ZZ input returns LOW.
ZZREC
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
DD
)
Address
Third
Fourth
Address
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
Third
Address
Fourth
Address
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Sleep mode standby current ZZ > VDD − 0.2V 80 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
CYC
CYC
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
ns
ns
ns
Document #: 38-05555 Rev. *F Page 8 of 28
[+] Feedback
CY7C1370D
CY7C1372D
Truth Table
[1, 2, 3, 4, 5, 6, 7]
Address
Operation
Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ
Deselect Cycle None H L L X X X L L-H Tri-State
Continue Deselect Cycle None X L H X X X L L-H Tri-State
Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q)
Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q)
NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State
Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State
Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D)
Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D)
NOP/Write Abort (Begin Burst) None L L L L H X L L-H Tri-State
Write Abort (Continue Burst) Next X L H X H X L L-H Tri-State
Ignore Clock Edge (Stall) Current X L X X X X H L-H –
Sleep Mode None X H X X X X X X Tri-State
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE
= H inserts wait states.
5. CEN
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Three-state when OE
7. OE
is inactive or when the device is deselected, and DQ
and BWX. See Write Cycle Description table for details.
stands for ALL Chip Enables active. BWx = L signifies at least one B yte W rite Select is active, BWx = Valid
signal.
.
= data when OE is active.
s
Document #: 38-05555 Rev. *F Page 9 of 28
[+] Feedback
CY7C1370D
CY7C1372D
Partial Write Cycle Description
Function (CY7C1370D) WE BW
[1, 2, 3, 8]
d
BW
c
BW
b
BW
a
Read H X X X X
Write – No bytes written L H H H H
Write Byte a – (DQ
Write Byte b – (DQ
and DQPa) LHHHL
a
and DQPb)LHHLH
b
Write Bytes b, a L H H L L
Write Byte c – (DQ
and DQPc)LHLHH
c
Write Bytes c, a L H L H L
Write Bytes c, b L H L L H
Write Bytes c, b, a L H L L L
Write Byte d – (DQ
and DQPd)LLHHH
d
Write Bytes d, a L L H H L
Write Bytes d, b LLHLH
Write Bytes d, b, a L L H L L
Write Bytes d, c L L L H H
Write Bytes d, c, a L L L H L
Write Bytes d, c, b L L L L H
Write All Bytes L L L L L
Function (CY7C1372D) WE
BW
b
BW
a
Read Hxx
Write – No Bytes Written L H H
Write Byte a – (DQ
Write Byte b – (DQ
and DQPa)LHL
a
and DQPb)LLH
b
Write Both Bytes L L L
Note:
8. Table only lists a par tial list ing of th e byte write combinatio ns. Any Combination of BW
is valid Appropriate write will be done based on which byte write is active.
X
Document #: 38-05555 Rev. *F Page 10 of 28
[+] Feedback
T
O
CY7C1370D
CY7C1372D
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1370D/CY7C1372D incorporates a serial boundary
scan test access port (TAP). This part is fully compliant with
1149.1. The TAP operates using JEDEC-standard 3.3V or
2.5V I/O logic levels.
The CY7C1370D/CY7C1372D contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V
) to prevent clocking of the device. TDI and TMS are inter-
SS
nally pulled up and may be unconnected. They may alternately
be connected to V
left unconnected. Upon power-up, the device will come up in
through a pull-up resistor. TDO should be
DD
a reset state which will not interfere with the operation of the
device.
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1 1
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
0 0
EXIT2-DR
UPDATE-DR
1 0
1
0
0
0 0
1
1 1
0 0
0
1
1
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
SELECT
1
0
0
1
0
1
1
0
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
012
TDI TD
TCK
MS TAP CONTROLLER
Selection
Circuitry
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
Instruction Register
012293031 ...
Identification Register
012..x ...
Boundary Scan Register
S
election
Circuitr
y
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the T AP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Document #: 38-05555 Rev. *F Page 11 of 28
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO bal l on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
[+] Feedback
CY7C1370D
CY7C1372D
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be pla ced betwee n the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V
) when the BYPASS instruction is executed.
SS
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction reg ister
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value th at will be
captured. Repeatable results may not be possible.
To guaran tee that the boundary scan registe r will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (t
captured correctly if there is no way in a design to stop (o r
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-FBGA package).
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the “Update-DR” state
and tCH). The SRAM clock input might not be
CS
Document #: 38-05555 Rev. *F Page 12 of 28
[+] Feedback
123456
T
CY7C1370D
CY7C1372D
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell will latch into the preload
TAP Timing
Test Clock
(TCK)
t
est Mode Select
(TMS)
t
Test Data-In
(TDI)
Test Data-Out
(TDO)
TMSS
TDIS
t
t
TMSH
t
TDIH
TH
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
t
TL
t
CYC
t
TDOX
t
TDOV
DON’T CARE UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range
[9, 10]
Parameter Description Min. Max. Unit
Clock
t
TCYC
t
TF
t
TH
t
TL
TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH time 20 ns
TCK Clock LOW time 20 ns
Output Times
t
TDOV
t
TDOX
TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns
Set-up Times
t
TMSS
t
TDIS
t
CS
TMS Set-up to TCK Clock Rise 5 ns
TDI Set-up to TCK Clock Rise 5 ns
Capture Set-up to TCK Rise 5 ns
Hold Times
t
TMSH
t
TDIH
t
CH
Notes:
and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
9. t
CS
10.Test conditions are specified using the load in TAP AC test Conditions. t
TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns
= 1 ns.
R/tF
Document #: 38-05555 Rev. *F Page 13 of 28
[+] Feedback
T
F
T
F
CY7C1370D
CY7C1372D
3.3V TAP AC Test Conditions
Input pulse levels................................................ VSS to 3.3V
Input rise and fall times................................................ ...1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supp ly voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
1.5V
50Ω
DO
Z = 50Ω
O
20p
2.5V TAP AC Test Conditions
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Test load te rmination supply voltage ............................1.25V
2.5V TAP AC Output Load Equivalent
1.25V
50Ω
DO
Z = 50Ω
O
20p
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)
Parameter Description T est Conditions Min. Max. Unit
V
V
V
V
V
V
I
OH1
OH2
OL1
OL2
IH
IL
X
Output HIGH Voltage IOH = –4.0 mA, V
I
= –1.0 mA, V
OH
Output HIGH Voltage IOH = –100 µA V
Output LOW Voltage IOL = 8.0 mA, V
I
= 8.0 mA, V
OL
Output LOW Voltage IOL = 100 µA V
Input HIGH Voltage V
Input LOW Voltage V
Input Load Current
= 3.3V 2.0 VDD + 0.3 V
DDQ
V
= 2.5V 1.7 VDD + 0.3 V
DDQ
= 3.3V –0.5 0.7 V
DDQ
V
= 2.5V –0.3 0.7 V
DDQ
VIN < V
GND <
[11]
= 3.3V 2.4 V
DDQ
= 2.5V 2.0 V
DDQ
= 3.3V 2.9 V
DDQ
V
= 2.5V 2.1 V
DDQ
= 3.3V 0.4 V
DDQ
= 2.5V 0.4 V
DDQ
= 3.3V 0.2 V
DDQ
V
= 2.5V 0.2 V
DDQ
DDQ
–5 5 µA
Note:
11.All voltages referenced to V
Document #: 38-05555 Rev. *F Page 14 of 28
(GND).
SS
[+] Feedback
CY7C1370D
CY7C1372D
Identification Register Definitions
Instruction Field CY7C1372D CY7C1370D Description
Revision Number (31:29) 000 000 Reserved for version number.
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor.
ID Register Presence (0) 1 1 Indicate the presence of an ID register.
Scan Register Sizes
Register Name Bit Size (x18) Bit Size (x36)
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary Scan Order (119-ball BGA package) 85 85
Boundary Scan Order (165-ball FBGA package) 89 89
Identification Codes
Instruction Code Description
EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM opera-
[12]
01011001000100101 01011001000010101 Reserved for future use.
Forces all SRAM outputs to High-Z state.
operation does not affect SRAM operations.
Forces all SRAM output drivers to a High-Z state.
Does not affect SRAM operation.
tions.
Note:
12.Bit #24 is “1” in the Register Definitions for both 2.5Vand 3.3V versions of this device.
Document #: 38-05555 Rev. *F Page 15 of 28
[+] Feedback
CY7C1370D
CY7C1372D
119-Ball BGA Boundary Scan Order
Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID
1
2T4 24E7 46A4 68M2
3T5 25D7 47G3 69N1
4T6 26H7 48C3 70P1
5R5 27G6 49B2 71K1
6L5 28E6 50B3 72L2
7R6 29D6 51A3 73
8U6 30C7 52C2 74P2
9R7 31B7 53A2 75R3
10 T7 32 C6 54 B1 76 T1
11 P6 33 A6 55 C1 77 R1
12 N7 34 C5 56 D2 78 T2
13 M6 35 B5 57 E1 79 L3
14 L7 36 G5 58 F2 80 R2
15 K6 37 B6 59 G1 81 T3
16 P7 38 D4 60 H2 82 L4
17 N6 39 B4 61 D1 83 N4
18 L6 40 F4 62 E2 84 P4
19 K7 41 M4 63 G2 85 Internal
20 J5 42 A5 64 H1
21 H6 43 K4 65 J3
22 G7 44 E4 66 2K
H4
23 F6 45 G4 67 L1
[13, 14]
N2
Notes:
13.Balls which are NC (No Connect) are pre-set LOW.
14.Bit# 85 is pre-set HIGH.
Document #: 38-05555 Rev. *F Page 16 of 28
[+] Feedback
CY7C1370D
CY7C1372D
165-Ball BGA Boundary Scan Order
Bit # Ball ID Bit # Ball ID Bit # Ball ID
1N6 31D10 61G1
2N7 32C11 62D2
3N10 33A11 63 E2
4P11 34B11 64 F2
5P8 35A10 65G2
6R8 36B10 66H1
7R9 37A9 67H3
8P9 38B9 68J1
9P10 39C10 69 K1
10 R10 40 A8 70 L1
11 R11 41 B8 71 M1
12 H11 42 A7 72 J2
13 N11 43 B7 73 K2
14 M11 44 B6 74 L2
15 L11 45 A6 75 M2
16 K11 46 B5 76 N1
17 J11 47 A5 77 N2
18 M10 48 A4 78 P1
19 L10 49 B4 79 R1
20 K10 50 B3 80 R2
21 J10 51 A3 81 P3
22 H9 52 A2 82 R3
23 H10 53 B2 83 P2
24 G11 54 C2 84 R4
25 F11 55 B1 85 P4
26 E11 56 A1 86 N5
27 D11 57 C1 87 P6
28 G10 58 D1 88 R6
29 F10 59 E1 89 Internal
30 E10 60 F1
[13, 15]
Note:
15.Bit# 89 is pre-set HIGH.
Document #: 38-05555 Rev. *F Page 17 of 28
[+] Feedback
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
Supply Voltage on V
DC to Outputs in Tri-State...................–0.5V to V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Relative to GND........–0.5V to +4.6V
DD
Relative to GND......–0.5V to +V
DDQ
+ 0.5V
DDQ
DD
CY7C1370D
CY7C1372D
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current...................................... ... ........... > 200 mA
Operating Range
Range
Commercial 0°C to +70°C 3.3V–5%/+10% 2.5V –5% to
Industrial –40°C to +85°C
Ambient
Temperature V
DD
V
DDQ
V
DD
Electrical Characteristics Over the Operating Range
[16, 17]
Parameter Description Test Conditions Min. Max. Unit
V
V
DD
DDQ
Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage for 3.3V I/O 3.135 V
DD
for 2.5V I/O 2.375 2.625 V
V
OH
V
OL
V
IH
V
IL
Output HIGH Voltage for 3.3V I/O, I
for 2.5V I/O, I
Output LOW Voltage for 3.3V I/O, I
for 2.5V I/O, I
Input HIGH Voltage
[16]
for 3.3V I/O 2.0 VDD + 0.3V V
for 2.5V I/O 1.7 V
Input LOW Voltage
[16]
for 3.3V I/O –0.3 0.8 V
= –4.0 mA 2.4 V
OH
= –1.0 mA 2.0 V
OH
= 8.0 mA 0.4 V
OL
= 1.0 mA 0.4 V
OL
+ 0.3V V
DD
for 2.5V I/O –0.3 0.7
I
X
I
OZ
I
DD
Input Leakage Current
GND ≤ VI ≤ V
except ZZ and MODE
Input Current of MODE Input = V
Input = V
Input Current of ZZ Input = V
Input = V
SS
DD
SS
DD
Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply V
DD
f = f
= Max., I
= 1/t
MAX
DDQ
–5 5 µA
–30 µA
–5 µA
Output Disabled –5 5 µA
DDQ,
OUT
CYC
= 0 mA,
4-ns cycle, 250 MHz 350 mA
5-ns cycle, 200 MHz 300 mA
5 µA
30 µA
6-ns cycle, 167 MHz 275 mA
I
SB1
I
SB2
I
SB3
I
SB4
Notes:
16.Overshoot: V
17.T
Power-up
Automatic CE
Power-down
Current—TTL Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—TTL Inputs
(AC) < V
IH
: Assumes a linear ramp from 0V to V
+1.5V (Pulse width less than t
DD
Max. VDD, Device Deselected,
V
≥ VIH or VIN ≤ VIL, f = f
1/t
IN
CYC
MAX
Max. VDD, Device Deselected,
V
≤ 0.3V or VIN > V
IN
f = 0
DDQ
− 0.3V,
Max. VDD, Device Deselected,
V
≤ 0.3V or VIN > V
IN
MAX
= 1/t
f = f
CYC
DDQ
− 0.3V,
Max. VDD, Device Deselected,
V
≥ VIH or VIN ≤ VIL, f = 0
IN
/2), undershoot: VIL(AC)> –2V (Pulse width less than t
CYC
(min.) within 200 ms. During this time V
DD
4-ns cycle, 250 MHz 160 mA
=
5-ns cycle, 200 MHz 150 mA
6-ns cycle, 167 MHz 140 mA
All speed grades 70 mA
4-ns cycle, 250 MHz 135 mA
5-ns cycle, 200 MHz 130 mA
6-ns cycle, 167 MHz 125 mA
All speed grades 80 mA
/2).
< VDD and V
IH
DDQ
< VDD.
CYC
V
V
Document #: 38-05555 Rev. *F Page 18 of 28
[+] Feedback
CY7C1370D
CY7C1372D
Capacitance
[18]
Parameter Description Test Conditions
C
Input Capacitance TA = 25°C, f = 1 MHz,
IN
C
C
CLK
I/O
Clock Input Capacitance 5 8 9 pF
Input/Output Capacitance 5 8 9 pF
Thermal Resistance
[18]
V
V
= 3.3V.
DD
DDQ
= 2.5V
Parameter Description T est Conditions
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
T est conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA/JESD51.
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
Z
2.5V I/O Test Load
= 50Ω
0
VT= 1.5V
(a)
R
= 50Ω
L
3.3V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
R = 317Ω
(b)
R = 351Ω
100 TQFP
Max.
119 BGA
Max.
165 FBGA
Max. Unit
589pF
100 TQFP
Package
119 BGA
Package
165 FBGA
Package Unit
28.66 23.8 20.7 °C/W
4.08 6.2 4.0 °C/W
V
DDQ
GND
≤ 1 ns
ALL INPUT PULSES
10%
90%
90%
10%
≤ 1 ns
(c)
OUTPUT
= 50Ω
Z
0
= 1.25V
V
T
R
L
(a)
Note:
18.Tested initially and after any design or process change that may affect these parameters.
2.5V
OUTPUT
= 50Ω
5pF
INCLUDING
JIG AND
SCOPE
R = 1667Ω
R = 1538Ω
(b)
V
DDQ
GND
≤ 1 ns
ALL INPUT PULSES
10%
90%
90%
10%
≤ 1 ns
(c)
Document #: 38-05555 Rev. *F Page 19 of 28
[+] Feedback
CY7C1370D
CY7C1372D
Switching Characteristics Over the Operating Range
Parameter Description
[19]
t
Power
Clock
t
CYC
F
MAX
t
CH
t
CL
Output Times
t
CO
t
EOV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Set-up Times
t
AS
t
DS
t
CENS
t
WES
t
ALS
t
CES
Hold Times
t
AH
t
DH
t
CENH
t
WEH
t
ALH
t
CEH
VCC (typical) to the first access read or write 1 1 1 ms
Clock Cycle Time 4.0 5 6 ns
Maximum Operating Frequency 250 200 167 MHz
Clock HIGH 1.7 2.0 2.2 ns
Clock LOW 1.7 2.0 2.2 ns
Data Output Valid After CLK Rise 2.6 3.0 3.4 ns
OE LOW to Output Valid 2.6 3.0 3.4 ns
Data Output Hold After CLK Rise 1.0 1.3 1.3 ns
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
[20, 21, 22]
[20, 21, 22]
[20, 21, 22]
[20, 21, 22]
Address Set-up Before CLK Rise 1.2 1.4 1.5 ns
Data Input Set-up Before CLK Rise 1.2 1.4 1.5 ns
CEN Set-up Before CLK Rise 1.2 1.4 1.5 ns
WE, BWx Set-up Before CLK Rise 1.2 1.4 1.5 ns
ADV/LD Set-up Before CLK Rise 1.2 1.4 1.5 ns
Chip Select Set-up 1.2 1.4 1.5 ns
Address Hold After CLK Rise 0.3 0.4 0.5 ns
Data Input Hold After CLK Rise 0.3 0.4 0.5 ns
CEN Hold After CLK Rise 0.3 0.4 0.5 ns
WE, BWx Hold After CLK Rise 0.3 0.4 0.5 ns
ADV/LD Hold after CLK Rise 0.3 0.4 0.5 ns
Chip Select Hold After CLK Rise 0.3 0.4 0.5 ns
[23, 24]
–250 –200 –167
UnitMin. Max. Min. Max. Min. Max.
2.6 3.0 3.4 ns
1.0 1.3 1.3 ns
2.6 3.0 3.4 ns
000ns
Notes:
19.This part has a voltage regulator internally; t
initiated.
, t
, t
20.t
CHZ
CLZ
21.At any given voltage and temperature, t
data bus. These specifications do not imply a bus co nte nti on condit ion, bu t reflect parameters guaranteed over worst case user co ndition s. Device i s designe d
to achieve High-Z prior to Low-Z under the same system conditions.
22.This parameter is sampled and not 100% tested.
23.Timing reference is 1.5V when V
24.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
EOLZ
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
EOHZ
DDQ
Power
EOHZ
= 3.3V and is 1.25V when V
Document #: 38-05555 Rev. *F Page 20 of 28
is the time power needs to be supplied above VDD minimum initially , before a Read or W rite opera tion can be
is less than t
EOLZ
and t
DDQ
is less than t
CHZ
= 2.5V.
to eliminate bus contention between SRAMs when sharing the same
CLZ
[+] Feedback
Switching Waveforms
123456789
10
I
CE
x
[25, 26, 27]
t
CENS
t
CES
t
CENH
t
CEH
Read/Write/Timing
CLK
CEN
ADV/LD
WE
BW
CY7C1370D
CY7C1372D
t
CYC
t
t
CL
CH
ADDRESS
Data
n-Out (DQ)
OE
A1 A2
t
t
AH
AS
WRITE
D(A1)
WRITE
D(A2)
A3
t
t
DH
DS
D(A1) D(A2) D(A5)Q(A4)Q(A3)
BURST
WRITE
D(A2+1)
READ
Q(A3)
A4
t
CO
t
CLZ
D(A2+1)
READ
Q(A4)
t
DOH
BURST
READ
Q(A4+1)
A5 A6 A7
t
OEHZ
t
WRITE
D(A5)
OEV
t
OELZ
t
CHZ
Q(A4+1)
t
DOH
READ
Q(A6)
DON’T CARE UNDEFINED
Notes:
25.For this waveform ZZ is tied LOW.
26.When CE
27.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved).Burst operations are optional.
is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
WRITE
D(A7)
Q(A6)
DESELECT
Document #: 38-05555 Rev. *F Page 21 of 28
[+] Feedback
Switching Waveforms (continued)
45678910
123
A
NOP,STALL and DESELECT Cycles
CLK
CEN
CE
ADV/LD
WE
BWx
[25, 26, 28]
CY7C1370D
CY7C1372D
ADDRESS
Data
In-Out (DQ)
ZZ Mode Timing
A1
D(A1)
[29, 30]
A2
READ
Q(A2)
CLK
ZZ
I
SUPPLY
LL INPUTS
(except ZZ)
A3 A4
D(A1) Q(A2) Q(A3)
STALL NOP READ
t
ZZ
t
ZZI
I
DDZZ
READ
Q(A3)
WRITE
D(A4)
DON’T CARE UNDEFINED
STALLWRITE
t
RZZI
DESELECT or READ Only
t
ZZREC
A5
D(A4)
DESELECT CONTINUE
Q(A5)
t
CHZ
Q(A5)
DESELECT
Outputs (Q)
Notes:
28.The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN
29.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
30.I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05555 Rev. *F Page 22 of 28
High-Z
DON’T CARE
being used to create a pause. A write is not performed during this cycle.
[+] Feedback
CY7C1370D
CY7C1372D
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz) Ordering Code
167 CY7C1370D-167AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1372D-167AXC
CY7C1370D-167BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1372D-167BGC
CY7C1370D-167BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372D-167BGXC
CY7C1370D-167BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1372D-167BZC
CY7C1370D-167BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1372D-167BZXC
CY7C1370D-167AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
CY7C1372D-167AXI
CY7C1370D-167BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1372D-167BGI
CY7C1370D-167BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372D-167BGXI
CY7C1370D-167BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1372D-167BZI
CY7C1370D-167BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1372D-167BZXI
200 CY7C1370D-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1372D-200AXC
CY7C1370D-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1372D-200BGC
CY7C1370D-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372D-200BGXC
CY7C1370D-200BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1372D-200BZC
CY7C1370D-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1372D-200BZXC
CY7C1370D-200AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
CY7C1372D-200AXI
CY7C1370D-200BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1372D-200BGI
CY7C1370D-200BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372D-200BGXI
CY7C1370D-200BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1372D-200BZI
CY7C1370D-200BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1372D-200BZXI
visit www.cypress.com for actual products offered.
Package
Diagram Part and Package Type
Operating
Range
Document #: 38-05555 Rev. *F Page 23 of 28
[+] Feedback
CY7C1370D
CY7C1372D
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
250 CY7C1370D-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1372D-250AXC
CY7C1370D-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1372D-250BGC
CY7C1370D-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372D-250BGXC
CY7C1370D-250BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1372D-250BZC
CY7C1370D-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1372D-250BZXC
CY7C1370D-250AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
CY7C1372D-250AXI
CY7C1370D-250BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1372D-250BGI
CY7C1370D-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372D-250BGXI
CY7C1370D-250BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1372D-250BZI
CY7C1370D-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1372D-250BZXI
visit www.cypress.com for actual products offered.
Document #: 38-05555 Rev. *F Page 24 of 28
[+] Feedback
Package Diagrams
R 0.08 MIN.
0.20 MAX.
0.25
GAUGE PLANE
0°-7°
0.60±0.15
1.00 REF.
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
14.00±0.10
81
80
0.30±0.08
0.65
TYP.
51
STAND-OFF
0.05 MIN.
0.15 MAX.
SEATING PLANE
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
20.00±0.10
22.00±0.20
100
1
30
31 50
0° MIN.
R 0.08 MIN.
0.20 MAX.
0.20 MIN.
A
DETAIL
12°±1°
(8X)
CY7C1370D
CY7C1372D
1.40±0.05
0.20 MAX.
1.60 MAX.
0.10
51-85050-*B
SEE DETAIL
A
Document #: 38-05555 Rev. *F Page 25 of 28
[+] Feedback
Package Diagrams (continued)
A1 CORNER
2165437
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
Ø1.00(3X) REF.
1.27
19.50
20.32
22.00±0.20
10.16
CY7C1370D
CY7C1372D
Ø0.05 M C
Ø0.25MCAB
Ø0.75±0.15(119X)
2143657
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
0.70 REF.
12.00
30° TYP.
0.90±0.05
0.25 C
SEATING PLANE
C
0.56
2.40 MAX.
0.15 C
0.60±0.10
A
B
0.15(4X)
3.81
7.62
14.00±0.20
51-85115-*B
1.27
Document #: 38-05555 Rev. *F Page 26 of 28
[+] Feedback
Package Diagrams (continued)
TOP VIEW
TOP VIEW
PIN 1 CORNER
PIN 1 CORNER
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
15.00±0.10
A
0.53±0.05
0.25 C
0.36
B
J
K
L
M
N
P
R
B
0.53±0.05
C
0.36
J
K
L
M
N
P
R
SEATING PLANE
C
13.00±0.10
13.00±0.10
SEATING PLANE
15.00±0.10
A
0.25 C
165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D
165-Ball FBGA (13 x 15 x 1.4 mm) (51-85 180)
1110986754321
1110986754321
14.00
15.00±0.10
15.00±0.10
A
A
0.15(4X)
1.40 MAX.
0.15 C
0.15 C
1.40 MAX.
0.35±0.06
0.35±0.06
11
11
1.00
1.00
14.00
7.00
7.00
5.00
B
B
0.15(4X)
NOTES :
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE WEIGHT : 0.475g
PACKAGE CODE : BB0AC
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
BOTTOM VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.25MCAB
Ø0.50 (165X)
5.00
10.00
13.00±0.10
13.00±0.10
PIN1CORNER
Ø0.05 M C
-0.06
Ø0.25 M C A B
+0.14
Ø0.50 (165X)
1.00
10.00
51-85180-*A
CY7C1370D
CY7C1372D
PIN 1 CORNER
-0.06
1
2345678910
+0.14
2345678910
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1.00
51-85180-*A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
ZBT is a trademark of Integrated Device T echnology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor
Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05555 Rev. *F Page 27 of 28
© Cypress Semiconductor Corporation, 2006. The information contained herein is su bj ect to ch an ge wi t hou t notice. Cypress Semiconductor Corporation assumes no responsibility for th e u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypre ss does not aut horize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY7C1370D
CY7C1372D
Document History Page
Document Title: CY7C1372D/CY7C1370D 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05555
REV. ECN No. Issue Date
** 254509 See ECN RKF New data sheet
*A 276690 See ECN VBL Changed TQFP pkg to Lead-free TQFP in Ordering Information section
*B 288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
*C 326078 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as
*D 370734 See ECN PCI Modified test condition in note# 17 from V
*E 416321 See ECN NXR Converted from preliminary to final
*F 475677 See ECN VKN Added the Maximum Rating for Supply Voltage on V
Orig. of
Change Description of Change
Added comment of Lead-free BG and BZ packages availability
non-compliance with 1149.1
Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA
Packages
per JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed Θ
4.08 °C/W respectively
Changed Θ
°C/W respectively
Changed Θ
4.0 °C/W respectively
Modified V
Removed shading from AC/DC Ta ble and Selection Guide
and Θ
JA
and Θ
JA
and Θ
JA
OL, VOH
for TQFP Package from 31 and 6 °C/W to 28.66 and
JC
for BGA Package from 45 and 7 °C/W to 23.8 and 6.2
JC
for FBGA Package from 46 and 3 °C/W to 20.7 and
JC
test conditions
Removed comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Updated Ordering Information Table
Changed from Preliminary to final
< V
DDQ
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Changed three-state to tri-state
Changed the I
to –30 µA and 5 µA
Changed the I
to –5 µA and 30 µA
Changed VIH < V
Replaced Package Name column with Package Diagram in the Ordering
current values of MODE on page # 18 from – 5 µA and 30 µA
X
current values of ZZ on page # 18 from –30 µA and 5 µA
X
to VIH < VDDon page # 18
DD
Information table
Updated Ordering Information Table
Changed t
AC Switching Characteristics table.
, t
from 25 ns to 20 ns and t
TH
TL
from 5 ns to 10 ns in TAP
TDOV
Updated the Ordering Information table.
DD to VDDQ
Relative to GND
DDQ
≤ V
DD
Document #: 38-05555 Rev. *F Page 28 of 28
[+] Feedback
Loading...