Cypress Semiconductor CY7C1371D, CY7C1373D Specification Sheet

Features

CY7C1371D CY7C1373D

18-Mbit (512K x 36/1M x 18)

Flow-Through SRAM with NoBL™ Architecture

Functional Description

[1]

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles

• Supports up to 133-MHz bus operations with zero wait states

— Data is transferred on every clock

• Pin-compatible and functionally equivalent to ZBT™ devices

• Internally self-timed output buffer control to eliminate the need to use OE

• Registered inputs for flow through operation

• Byte Write capability

• 3.3V/2.5V IO power supply (V

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

• Clock Enable (CEN operation

• Synchronous self-timed writes

• Asynchronous Output Enable

• Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 119-Ball BGA and 165-Ball FBGA package.

• Three chip enables for simple depth expansion

• Automatic Power down feature available using ZZ mode or CE deselect

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst Capability — linear or interleaved burst order

• Low standby power

) pin to enable clock and suspend

DDQ

)

The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1M x 18 Synchronous flow through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations with no wait state insertion. The CY7C1371D/CY7C1373D is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device).

Write operations are controlled by the two or four Byte Write Select (BW conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE asynchronous Output Enable (OE selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

) and a Write Enable (WE) input. All writes are

X

) signal, which when deasserted

, CE2, CE3) and an

1

) provide for easy bank

Selection Guide

Maximum Access Time 6.5 8.5 ns

Maximum Operating Current 210 175 mA

Maximum CMOS Standby Current 70 70 mA

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05556 Rev. *F Revised July 09, 2007

133 MHz 100 MHz Unit

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Logic Block Diagram – CY7C1371D (512K x 36)

CY7C1371D CY7C1373D

ADDRESS REGISTER

A1 A0

ADV/LD

C

WRITE ADDRESS

REGISTER

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

SLEEP

CONTROL

D1 D0

CLK

CEN

A0, A1, A

MODE

C

ADV/LD

BW

WE

CE1 CE2 CE3

ZZ

CE

A

B

C

D

OE

Logic Block Diagram – CY7C1373D (1M x 18)

BURST LOGIC

A1'

Q1

A0'

Q0

O U

T P

D

U

A

T

T A

B

U

S

F

T

F

E

R

S

I N G

E

DQs DQP DQP DQP DQP

A

B

C

D

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

REGISTER

S E

N

S

E

A

M

P

S

E

CLK CEN

A0, A1, A

MODE

C

ADV/LD

BW

WE

OE CE1 CE2 CE3

ZZ

ADDRESS REGISTER

CE

ADV/LD

A1 A0

D1 D0

BURST LOGIC

Q1 Q0

A1' A0'

C

WRITE ADDRESS

REGISTER

S E

N

INPUT

S E

A M

P S

E

A

B

WRITE REGISTRY

AND DATA COHERENCY

WRITE

DRIVERS

MEMORY

ARRAY

CONTROL LOGIC

REGISTER

O U

T P

D

U

A

T

A

B U

S

F

T

F

E

R

S

I N G

E

DQs DQP DQP

A

B

READ LOGIC

SLEEP

CONTROL

Document #: 38-05556 Rev. *F Page 2 of 29

[+] Feedback

Pin Configurations

100-Pin TQFP Pinout

CY7C1371D

CY7C1373D

BYTE C

BYTE D

DQP

DQ DQ

V

DDQ

V DQ DQ DQ DQ

V

DDQ

DQ DQ

V

V DQ DQ

V

DDQ

V DQ DQ DQ DQ

V

DDQ

DQ DQ

DQP

SS

NC

DD

NC

SS

1CE2

A

CE

A

100

999897

1

C

2

C

3

C

4 5 6

C

7

C

8

C

9

C

10 11 12

C

13

C

14 15 16 17 18

D

19

D

20 21 22

D

23

D

24

D

25

D

26 27 28

D

29

D

30

D

C

BWDBW

BWBBWACE3VDDV

969594939291908988878685848382

SS

CLKWECEN

OE

ADV/LD

A

CY7C1371D

A

81

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

DQP DQ DQ V

DDQ

V

SS

DQ DQ DQ DQ V

SS

V

DDQ

DQ DQ V

SS

NC V

DD

ZZ

DQ DQ V

DDQ

V

SS

DQ DQ DQ DQ V

SS

V

DDQ

DQ DQ DQP

B

BYTE B

B

A

BYTE A

A

31323334353637383940414243

A

MODE

Document #: 38-05556 Rev. *F Page 3 of 29

444546

A

A1

A0

NC/288M

NC/144M

SS

DD

V

NC/72M

A

NC/36M

474849

A

50

A

[+] Feedback

Pin Configurations (continued)

100-Pin TQFP Pinout

CY7C1371D CY7C1373D

BYTE B

V

DDQ

V

DQ DQ

V

DDQ

DQ DQ

V

V DQ DQ

V

DDQ

V DQ DQ

DQP

V

DDQ

NC NC NC

SS

NC NC

SS

NC

DD

NC

SS

NC

SS

NC NC NC

1CE2

A

100

A

999897

CE

NC

1 2 3 4 5 6 7 8

B

9

B

10 11 12

B

13

B

14 15 16 17 18

B

19

B

20 21 22

B

23

B

24

B

25 26 27 28 29 30

BBWA

NC

BW

969594939291908988878685848382

CE3VDDV

SS

CLKWECEN

OE

ADV/LD

A

CY7C1373D

A

81

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

A NC NC V

DDQ

V

SS

NC DQP DQ DQ V

SS

V

DDQ

DQ DQ V

SS

NC V

DD

ZZ

DQ DQ V

DDQ

V

SS

DQ DQ NC NC V

SS

V

DDQ

NC NC NC

A

BYTE A

A

31323334353637383940414243

A

MODE

Document #: 38-05556 Rev. *F Page 4 of 29

444546

A

A1

A0

NC/288M

NC/144M

SS

DD

V

NC/72M

A

NC/36M

474849

A

50

A

[+] Feedback

Pin Configurations (continued)

CY7C1371D CY7C1373D

A

B

C

D

E

F

G H

J

K

L

M

N

P

R

T U

V

DDQ

NC/576M

NC/1G

DQ

C

DQ

C

V

DDQ

DQ

C

DQ

C

V

DDQ

DQ

D

DQ

D

V

DDQ

DQ

D

DQ

D

NC/144M

NC

V

DDQ

119-Ball BGA

Pinout

CY7C1371D (512K x 36)

2345671

AA AAV

CE

2

A

AA

DQP

DQ

DQ DQ

V

DD

DQ

DQP

A

V

C

V

BW

V

SS

C

SS

NC V

V

BW

V

SS

D

SS

D

MODE

AAA

A

ADV/LD

V

DD

NC

CE

1

OE

A

WE

DD

CLK

NC

CEN

A1

A0

V

DD

A

V

BW

V

NC

V

BW

V

NC

TDOTCKTDITMS

SS

DDQ

B

A

NC/288M

DQ

V

DQ DQ

V

DQ

V

DQ

V

NC

DDQ

ZZ

DDQ

CE

3

AA

DQP

DQ

B

DQ

B

DQ DQ

V

DQ

B

DD

A

B

A

DQP

A

NC/36MNC/72M

NC

B

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

DDQ

NC/576M

NC/1G

B

NC

V

DDQ

NC

DQ

B

V

DDQ

NC

DQ

B

V

DDQ

DQ

B

NC

NC/144M

NC/72M

V

DDQ

CY7C1373D (1Mx 18)

2

AA AAV

CE

2

NCDQ

DQ

B

NC

DQ

B

NC

V

DD

DQ

B

NC

DQ

B

NC

DQP

B

A

345671

A

ADV/LD

AA

V

SS

V

SS

V

SS

BW

V

SS

NC V

V

SS

NC

V

SS

V

SS

V

SS

MODE

V

DD

NC

CE

OE

B

A

WE

DD

CLK

NC

CEN

A1

A0

V

DD

V

1

V

NC

V

NC

V

BW

V

NC

ANC/36MA

TDOTCKTDITMS

A

SS

DDQ

A

NC/288M

DQ

V

DQ

V

DQ

V

DQ

V

NC

A

DDQ

A

NC

DDQ

A

NC

DDQ

NC

A

ZZ

DDQ

CE

3

AA

DQP

NC

DQ

A

NC

DQ

A

V

DD

NC

DQ

A

NC

DQ

A

NC

A

AA

NC

Document #: 38-05556 Rev. *F Page 5 of 29

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Pin Configurations (continued)

165-Ball FBGA Pinout

CY7C1371D (512K x 36)

CY7C1371D CY7C1373D

A

B C D

E F G

H

J K L M N P

R

A

B C D

E F

G H

J

K

L

M N P

R

234 5671

NC/576M

NC/1G

DQP

C

DQ

C

DQ

C

DQ

C

DQ

C

NC

DQ

D

DQ

D

DQ

D

DQ

D

DQP

D

NC/144M

MODE

A

NC

DQ

C

DQ

C

DQ

C

DQ

C

NC

DQ

D

DQ

D

DQ

D

DQ

D

NC

NC/72M

NC/36M

CE

CE2

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

BW

1

BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

BW

V

V V V

V

B

A

SS

C

D

NC

TDI

TMS

CY7C1373D (1M x 18)

234 5671

NC/576M

NC/1G

NC

NC V

NC

NC NC

DQ

B

DQ

B

DQ

B

DQ

B

DQP

B

NC/144M

MODE

A

NC

DQ

B

DQ

B

DQ

B

DQ

B

NC

NC/72M

NC/36M

CE

CE2

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

BW

1

B

NC BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

NC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

A

CE

CLK

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

A1

A0

CE

CLK

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

A1

A0

SS

891011

A

NC

NC DQP

DQ

B

DQ

B

DQ

B

DQ

B

NC

A

DQ

DQP

NC/288M

DQ

NC

A

B

ZZ

A

AA

SS

ADV/LD

OE

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

CEN

3

WE

V

V V

V

NC

TDO

TCK

V

A

DDQ

NC

DDQ

A

891011

A

NC

NC DQP

A

DQ

ZZ

NCV

NC

NC/288M

NC

NC NC

DQ

NC

A

AA

SS

ADV/LD

OE

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

CEN

3

WE

V

V V

V

NC

TDO

TCK

V

A

DDQ

NC

DDQ

A

Document #: 38-05556 Rev. *F Page 6 of 29

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Pin Definitions

Name IO Description

, A1, A Input-

A

0

BWA, BW BWC, BW

Synchronous

B

Synchronous

D

Input-

WE Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. A

are fed to the two-bit burst counter.

[1:0]

Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK.

Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence.

CY7C1371D CY7C1373D

ADV/LD

Input-

Synchronous

CLK Input-

Clock

CE

OE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

CEN

Input-

Synchronous

ZZ Input-

Asynchronous

DQ

s

IO-

Synchronous

Advance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH (and CEN address can be loaded into the device for an access. After being deselected, ADV/LD

is asserted LOW) the internal burst counter is advanced. When LOW, a new

must be

driven LOW to load a new address.

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN

is active LOW.

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE3 to select/deselect the device.

2

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE3 to select/deselect the device.

1

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE2 to select/deselect the device.

1

Output Enable, asynchronous input, Active LOW. Combined with the synchronous logic block inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected.

Clock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. While deasserting CEN deselect the device, use CEN

to extend the previous cycle when required.

does not

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull down.

Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE DQ

and DQP

s

the data portion of a write sequence, during the first clock when emerging from a deselected state,

[A:D]

. When OE is asserted LOW, the pins behave as outputs. When HIGH,

are placed in a tri-state condition.The outputs are automatically tri-stated during

and when the device is deselected, regardless of the state of OE.

DQP

X

IO-

Synchronous

Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs.

MODE Input Strap Pin Mode Input. Selects the burst order of the device.

When tied to Gnd selects linear burst sequence. When tied to V burst sequence.

V

DD

DDQ

SS

Power Supply Power supply inputs to the core of the device.

IO Power

Power supply for the IO circuitry.

Supply

Ground Ground for the device.

Document #: 38-05556 Rev. *F Page 7 of 29

or left floating selects interleaved

DD

[+] Feedback

Pin Definitions (continued)

Name IO Description

TDO JTAG serial

output

Synchronous

TDI JTAG serial

input

Synchronous

TMS JTAG serial

input

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being used, this pin must be left unconnected. This pin is not available on TQFP packages.

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being used, this pin can be left floating or connected to V not available on TQFP packages.

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being used, this pin can be disconnected or connected to V packages.

CY7C1371D CY7C1373D

through a pull up resistor. This pin is

DD

. This pin is not available on TQFP

DD

TCK JTAG-

NC – No Connects. Not internally connected to the die. NC/(36 M, 72 M, 144 M, 288M, 576M, 1G)are

Clock

Functional Overview

The CY7C1371D/CY7C1373D is a synchronous flow through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN nized and all internal states are maintained. All synchronous operations are qualified with CEN from the clock rise (t

Accesses can be initiated by asserting all three Chip Enables (CE

1

Enable (CEN the address presented to the device is latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE byte write operations.

Write operations are qualified by the Write Enable (WE writes are simplified with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD deselected to load a new address for the next operation.

). If CEN is HIGH, the clock signal is not recog-

CDV

, CE2, CE3) active at the rising edge of the clock. If Clock

) is active LOW and ADV/LD is asserted LOW,

must be driven LOW after the device has been

Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected to V

address expansion pins and are not internally connected to the die.

. Maximum access delay

) is 6.5 ns (133-MHz device).

). BWX can be used to conduct

) simplify depth expansion.

. This pin is not available on TQFP packages.

SS

is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output is tri-stated immediately.

Burst Read Accesses

The CY7C1371D/CY7C1373D has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address

). All

inputs. ADV/LD into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A sequence, and wraps around when incremented sufficiently. A HIGH input on ADV/LD regardless of the state of chip enable inputs or WE latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence.

must be driven LOW to load a new address

is active LOW. After the first

increments the internal burst counter

and A1 in the burst

0

. WE is

Single Read Accesses

A read access is initiated when these conditions are satisfied at clock rise:

is asserted LOW

•CEN

•CE

, CE2, and CE3 are ALL asserted active

1

• The Write Enable input signal WE

•ADV/LD

The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic. The control logic determines that a read access

Document #: 38-05556 Rev. *F Page 8 of 29

is asserted LOW.

is deasserted HIGH

Single Write Accesses

Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE is asserted LOW. The address presented to the address bus is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically tri-stated regardless of the state of the OE signal. This allows the external logic to present the data on DQs and DQPX.

On the next clock rise the data presented to DQs and DQP (or a subset for byte write operations, see truth table for

are ALL asserted active, and (3) the write signal WE

3

input

X

[+] Feedback

CY7C1371D CY7C1373D

details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle.

The data written during the Write operation is controlled by BW

signals. The CY7C1371D/CY7C1373D provides byte

X

write capability that is described in the truth table. Asserting the Write Enable input (WE

) with the selected Byte Write Select input selectively writes to only the desired bytes. Bytes not selected during a byte write operation remains unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations.

Because the CY7C1371D/CY7C1373D is a common IO device, data must not be driven into the device while the outputs are active. The Output Enable (OE HIGH before presenting data to the DQs and DQP Doing so tri-states the output drivers. As a safety precaution,

) can be deasserted

inputs.

X

DQs and DQPX are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE

.

Burst Write Accesses

The CY7C1371D/CY7C1373D has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD

must be driven LOW to load the initial address, as described in the Single Write Access section above. When ADV/LD rise, the Chip Enables (CE ignored and the burst counter is incremented. The correct BW

inputs must be driven in each cycle of the burst write, to

X

write the correct bytes of data.

is driven HIGH on the subsequent clock

, CE2, and CE3) and WE inputs are

1

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE for the duration of t

, CE2, and CE3, must remain inactive

1

after the ZZ input returns LOW.

ZZREC

Interleaved Burst Address Table (MODE = Floating or V

First

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Second

Address

A1: A0

DD

)

Third

Address

A1: A0

Fourth

Address

A1: A0

Linear Burst Address Table (MODE = GND)

First

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Document #: 38-05556 Rev. *F Page 9 of 29

Sleep mode standby current ZZ > VDD – 0.2V 80 mA

Device operation to ZZ ZZ > VDD – 0.2V 2t

ZZ recovery time ZZ < 0.2V 2t

ZZ active to sleep current This parameter is sampled 2t

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

CYC

ns

[+] Feedback

CY7C1371D CY7C1373D

Truth Table

[2, 3, 4, 5, 6, 7, 8]

Address

Operation

Used CE1CE

ZZ ADV/LD WE BWXOE CEN CLK DQ

CE

2

3

Deselect Cycle None H X X L L X X X L L->H Tri-State

Deselect Cycle None X X H L L X X X L L->H Tri-State

Deselect Cycle None X L X L L X X X L L->H Tri-State

Continue Deselect Cycle None X X X L H X X X L L->H Tri-State

Read Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q)

Read Cycle (Continue Burst) Next X X X L H X X L L L->H Data Out (Q)

NOP/Dummy Read (Begin Burst) External L H L L L H X H L L->H Tri-State

Dummy Read (Continue Burst) Next X X X L H X X H L L->H Tri-State

Write Cycle (Begin Burst) External L H L L L L L X L L->H Data In (D)

Write Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D)

NOP/Write Abort (Begin Burst) None L H L L L L H X L L->H Tri-State

Write Abort (Continue Burst) Next X X X L H X H X L L->H Tri-State

Ignore Clock Edge (Stall) Current X X X L X X X X H L->H –

Sleep Mode None X X X H X X X X X X Tri-State

Partial Truth Table for Read/Write

Function (CY7C1371D) WE BW

[2, 3, 9]

A

BW

B

BW

C

BW

D

Read HXXXX

Write No bytes written L H H H H

Write Byte A – (DQ

Write Byte B – (DQ

Write Byte C – (DQ

Write Byte D – (DQ

and DQPA)LLHHH

A

and DQPB)LHLHH

B

and DQPC)LHHLH

C

and DQPD)LHHHL

D

Write All Bytes LLLLL

Partial Truth Table for Read/Write

[2, 3, 9]

Function (CY7C1373D) WE BW

Read HXX

Write - No bytes written L H H

Write Byte A – (DQ

Write Byte B – (DQ

and DQPA)LLH

A

and DQPB)LHL

B

Write All Bytes L L L

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW selects are asserted, see truth table for details.

3. Write is defined by BW

4. When a write cycle is detected, all IOs are tri-stated, even during byte writes.

5. The DQs and DQP

6. CEN

= H, inserts wait states.

7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE

8. OE is inactive or when the device is deselected, and DQs and DQP

9. Table only lists a partial listing of the byte write combinations. Any Combination of BW

, and WE. See truth table for Read/Write.

X

pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

X

Document #: 38-05556 Rev. *F Page 10 of 29

A

= 0 signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired byte write

X

.

= data when OE is active.

X

is valid Appropriate write is based on which byte write is active.

X

BW

B

[+] Feedback

CY7C1371D

Bypass Register

0

Instruction Register

012

Identication Register

012293031 ...

Boundary Scan Register

012..x ...

Selection

Circuitry

TCK

TMS

TAP CONTROLLER

TDI TDO

Selection

Circuitry

CY7C1373D

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1371D/CY7C1373D incorporates a serial boundary scan test access port (TAP).This part is fully compliant with

1149.1. The TAP operates using JEDEC-standard 3.3V or

2.5V IO logic levels. The CY7C1371D/CY7C1373D contains a TAP controller,

instruction register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW

) to prevent clocking of the device. TDI and TMS are inter-

(V

SS

nally pulled up and may be unconnected. They may alternately be connected to V left unconnected. Upon power up, the device is up in a reset

through a pull up resistor. TDO must be

DD

state which does not interfere with the operation of the device.

TAP Controller State Diagram

TEST-LOGIC

1

RESET

0

IDLE

1

SELECT

DR-SCAN

1 1

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

0 0

EXIT2-DR

UPDATE-DR

1 0

0

RUN-TEST/

The 0/1 next to each state represents the value of TMS at the rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.

1

0

0 0

1

1 1

0 0

0

1

SELECT

IR-SCAN

0

CAPTURE-IR

0

SHIFT-IR

1

EXIT1-IR

PAUSE-IR

1

EXIT2-IR

1

UPDATE-IR

1

0

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

1

0

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (V rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating.

At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE

) for five

DD

Document #: 38-05556 Rev. *F Page 11 of 29

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CY7C1371D CY7C1373D

instruction if the controller is placed in a reset state as described in the previous section.

When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW

) when the BYPASS instruction is executed.

(V

SS

Boundary Scan Register

The boundary scan register is connected to all the input and bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring.

The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table.

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail below.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller needs to be moved into the Update-IR state.

EXTEST

access between the TDI and TDO in the shift-DR controller state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is supplied a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible.

To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (t captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK boundary scan register.

After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in.

and tCH). The SRAM clock input might not be

CS

captured in the

The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial

Document #: 38-05556 Rev. *F Page 12 of 29

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the

[+] Feedback

CY7C1371D

T

CY7C1373D

boundary scan path when multiple devices are connected together on a board.

EXTEST Output Bus Tri-State

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #85 (for 119-BGA package) or bit #89 (for 165-fBGA package). When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the “Update-DR” state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition.

TAP Timing

123456

Test Clock

(TCK)

est Mode Select

(TMS)

t

TMSS

t

TDIS

t

TMSH

t

TDIH

TH

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR,” the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

t

TL

t

CYC

Test Data-In

(TDI)

Test Data-Out

(TDO)

DON’T CARE UNDEFINED

t

TDOX

t

TDOV

Document #: 38-05556 Rev. *F Page 13 of 29

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CY7C1371D CY7C1373D

TAP AC Switching Characteristics Over the Operating Range

[10, 11]

Parameter Description Min Max Unit

Clock

t

TCYC

t

TF

t

TH

t

TL

TCK Clock Cycle Time 50 ns

TCK Clock Frequency 20 MHz

TCK Clock HIGH time 20 ns

TCK Clock LOW time 20 ns

Output Times

t

TDOV

t

TDOX

TCK Clock LOW to TDO Valid 10 ns

TCK Clock LOW to TDO Invalid 0 ns

Setup Times

t

TMSS

t

TDIS

t

CS

TMS Setup to TCK Clock Rise 5 ns

TDI Setup to TCK Clock Rise 5 ns

Capture Setup to TCK Rise 5 ns

Hold Times

t

TMSH

t

TDIH

t

CH

TMS Hold after TCK Clock Rise 5 ns

TDI Hold after Clock Rise 5 ns

Capture Hold after Clock Rise 5 ns

Notes:

and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

10. t

CS

11.Test conditions are specified using the load in TAP AC test Conditions. t

Document #: 38-05556 Rev. *F Page 14 of 29

R/tF

= 1 ns.

[+] Feedback

CY7C1371D

TDO

1.25V

20pF

Z = 50Ω

O

50Ω

CY7C1373D

3.3V TAP AC Test Conditions

Input pulse levels ............................................... .VSS to 3.3V

Input rise and fall times................................................... 1 ns

Input timing reference levels ...........................................1.5V

Output reference levels...................................................1.5V

Test load termination supply voltage...............................1.5V

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Test Conditions

Input pulse level................................................... VSS to 2.5V

Input rise and fall time .....................................................1 ns

Input timing reference levels........................................ .1.25V

Output reference levels ................................................1.25V

Test load termination supply voltage ............................1.25V

2.5V TAP AC Output Load Equivalent

1.5V

50Ω

TDO

Z = 50Ω

O

20pF

TAP DC Electrical Characteristics And Operating Conditions

DDQ

[12]

= 3.3V 2.4 V

DDQ

= 2.5V 2.0 V

DDQ

= 3.3V 2.9 V

DDQ

= 2.5V 2.1 V

V

DDQ

= 3.3V 0.4 V

DDQ

= 2.5V 0.4 V

DDQ

= 3.3V 0.2 V

DDQ

V

= 2.5V 0.2 V

DDQ

= 3.3V 2.0 VDD + 0.3 V

DDQ

= 2.5V 1.7 VDD + 0.3 V

V

DDQ

= 3.3V –0.5 0.7 V

DDQ

= 2.5V –0.3 0.7 V

V

DDQ

–5 5 µA

(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)

Parameter Description Description Conditions Min Max Unit

V

I

OH1

OH2

OL1

OL2

IH

IL

X

Output HIGH Voltage IOH = –4.0 mA V

I

= –1.0 mA V

OH

Output HIGH Voltage IOH = –100 µA V

Output LOW Voltage IOL = 8.0 mA V

= 1.0 mA V

I

OL

Output LOW Voltage IOL = 100 µA V

Input HIGH Voltage V

Input LOW Voltage V

Input Load Current GND < VIN < V

Note:

12. All voltages referenced to V

Document #: 38-05556 Rev. *F Page 15 of 29

(GND).

SS

[+] Feedback

Identification Register Definitions

CY7C1371D CY7C1373D

Instruction Field

Revision Number (31:29) 000 000 Describes the version number

Device Depth (28:24) 01011 01011 Reserved for internal use

Device Width (23:18) 001001 001001 Defines memory type and architecture

Cypress Device ID (17:12) 100101 010101 Defines width and density

Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor

ID Register Presence Indicator (0) 1 1 Indicates the presence of an ID register

CY7C1371D

(512K X 36)

CY7C1373D

(1M X 18) Description

Scan Register Sizes

Register Name Bit Size (x36) Bit Size (x18)

Instruction 3 3

Bypass 1 1

ID 32 32

Boundary Scan Order (119-Ball BGA package) 85 85

Boundary Scan Order (165-Ball FBGA package) 89 89

Identification Codes

Instruction Code Description

EXTEST 000 Captures IO ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

SAMPLE Z 010 Captures IO ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures IO ring contents. Places the boundary scan register between TDI and TDO.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

Document #: 38-05556 Rev. *F Page 16 of 29

Does not affect SRAM operation.

operations.

[+] Feedback

CY7C1371D CY7C1373D

119-Ball BGA Boundary Scan Order

Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID

1

2 T4 24E7 46A4 68M2

3T5 25D7 47G3 69N1

4 T6 26H7 48C3 70P1

5R5 27G6 49B2 71K1

6 L5 28E6 50B3 72L2

7R629D651A373

8U630C752C274P2

9 R7 31B7 53A2 75R3

10 T7 32 C6 54 B1 76 T1

11 P6 33 A6 55 C1 77 R1

12 N7 34 C5 56 D2 78 T2

13 M6 35 B5 57 E1 79 L3

14 L7 36 G5 58 F2 80 R2

15 K6 37 B6 59 G1 81 T3

16 P7 38 D4 60 H2 82 L4

17 N6 39 B4 61 D1 83 N4

18 L6 40 F4 62 E2 84 P4

19 K7 41 M4 63 G2 85 Internal

20 J5 42 A5 64 H1

21 H6 43 K4 65 J3

22 G7 44 E4 66 2K

H4

23 F6 45 G4 67 L1

[13, 14]

N2

Notes:

13. Balls which are NC (No Connect) are pre-set LOW.

14. Bit# 85 is pre-set HIGH.

Document #: 38-05556 Rev. *F Page 17 of 29

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CY7C1371D CY7C1373D

165-Ball BGA Boundary Scan Order

Bit # Ball ID Bit # Ball ID Bit # Ball ID

1 N6 31 D10 61 G1

2N7 32C11 62D2

3 N10 33 A11 63 E2

4P11 34B11 64F2

5P8 35A10 65G2

6R8 36B10 66H1

7R9 37A9 67H3

8P938B968J1

9 P10 39 C10 69 K1

10 R10 40 A8 70 L1

11 R11 41 B8 71 M1

12 H11 42 A7 72 J2

13 N11 43 B7 73 K2

14 M11 44 B6 74 L2

15 L11 45 A6 75 M2

16 K11 46 B5 76 N1

17 J11 47 A5 77 N2

18 M10 48 A4 78 P1

19 L10 49 B4 79 R1

20 K10 50 B3 80 R2

21 J10 51 A3 81 P3

22 H9 52 A2 82 R3

23 H10 53 B2 83 P2

24 G11 54 C2 84 R4

25 F11 55 B1 85 P4

26 E11 56 A1 86 N5

27 D11 57 C1 87 P6

28 G10 58 D1 88 R6

29 F10 59 E1 89 Internal

30 E10 60 F1

[13, 15]

Note:

15. Bit# 89 is pre-set HIGH.

Document #: 38-05556 Rev. *F Page 18 of 29

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CY7C1371D CY7C1373D

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V

DC Voltage Applied to Outputs

in Tri-State........................................... –0.5V to V

Relative to GND........ –0.5V to +4.6V

DD

Relative to GND ...... –0.5V to +V

DDQ

DD

+ 0.5V

DC Input Voltage ................................... –0.5V to V

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage.......................................... > 2001V

(MIL-STD-883, Method 3015)

Latch up Current.................................................... > 200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5% Industrial –40°C to +85°C

Ambient

Temperature V

DD

+ 0.5V

DD

V

to V

DDQ

DD

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Max Unit

V V

V

I

X

DD

DDQ

OH

OL

IH

IL

Power Supply Voltage 3.135 3.6 V IO Supply Voltage for 3.3V IO 3.135 V

Output HIGH Voltage for 3.3V IO, I

Output LOW Voltage for 3.3V IO, I

Input HIGH Voltage

Input LOW Voltage

Input Leakage Current except ZZ and MODE

Input Current of MODE Input = V

Input Current of ZZ Input = V

I

DD

I

SB1

VDD Operating Supply Current

Automatic CE Power down Current—TTL Inputs

I

SB2

Automatic CE Power down Current—CMOS Inputs

I

SB3

Automatic CE Power down Current—CMOS Inputs

I

SB4

Automatic CE Power down Current—TTL Inputs

[16, 17]

for 2.5V IO 2.375 2.625 V

= –4.0 mA 2.4 V

OH

for 2.5V IO, I

[16]

for 3.3V IO 2.0 VDD + 0.3V V

= –1.0 mA 2.0 V

OH

= 8.0 mA 0.4 V

OL

= 1.0 mA 0.4 V

OL

for 2.5V IO 1.7 VDD + 0.3V V

[16]

for 3.3V IO –0.3 0.8 V for 2.5V IO –0.3 0.7 GND ≤ VI ≤ V

Input = V

V

= Max., I

DD

f = f

MAX

V

= Max, Device Deselected,

DD

V

≥ VIH or VIN ≤ V

IN

f = f

MAX

V

= Max, Device Deselected,

DD

V

≤ 0.3V or VIN > VDD – 0.3V,

IN

f = 0, inputs static

V

= Max, Device Deselected, or

DD

≤ 0.3V or VIN > V

V

IN

f = f

MAX

V

= Max, Device Deselected,

DD

V

≥ VDD – 0.3V or VIN ≤

IN

0, inputs static

DDQ

SS

DD

SS

DD

= 0 mA,

OUT

= 1/t

CYC

, inputs switching

IL

DDQ

– 0.3V

, f =

0.3V

7.5 ns cycle, 133 MHz 210 mA

10 ns cycle, 100 MHz 175 mA

7.5 ns cycle, 133 MHz 140 mA

10 ns cycle, 100 MHz 120 mA

All speeds 70 mA

7.5 ns cycle, 133 MHz 130 mA

10 ns cycle, 100 MHz 11 0 mA

All Speeds 80 mA

–5 5 µA

–30 µA

–5 µA

DD

5 µA

30 µA

V

Notes:

16. Overshoot: V

17. T

Power-up

(AC) < VDD +1.5V (Pulse width less than t

IH

: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and V

Document #: 38-05556 Rev. *F Page 19 of 29

/2), undershoot: VIL(AC) > –2V (Pulse width less than t

CYC

DDQ

< VDD.

CYC

/2).

[+] Feedback

CY7C1371D CY7C1373D

Capacitance

[18]

Parameter Description Test Conditions

Input Capacitance TA = 25°C, f = 1 MHz,

C

IN

C

CLK

IO

Clock Input Capacitance 5 8 9 pF

Input/Output Capacitance 5 8 9 pF

Thermal Resistance

[18]

V V

= 3.3V

DD DDQ

= 2.5V

Parameter Description Test Conditions

Θ

JA

Θ

JC

Thermal Resistance (Junction to Ambient)

Thermal Resistance (Junction to Case)

Test conditions follow standard test methods and procedures for measuring thermal impedance, according to EIA/JESD51.

AC Test Loads and Waveforms

3.3V IO Test Load

= 50Ω

3.3V

OUTPUT

INCLUDING

5pF

JIG AND

SCOPE

(b)

OUTPUT

2.5V IO Test Load

Z

= 50Ω

0

VT= 1.5V

(a)

R

L

R = 317Ω

R = 351Ω

100 TQFP

Package

119 BGA Package

165 FBGA

Package Unit

589pF

100 TQFP

Package

119 BGA Package

165 FBGA

Package Unit

28.66 23.8 20.7 °C/W

4.08 6.2 4.0 °C/W

V

DDQ

GND

≤ 1ns

ALL INPUT PULSES

10%

90%

10%

≤ 1ns

(c)

OUTPUT

= 50Ω

Z

0

= 1.25V

V

T

R

L

(a)

Note:

18. Tested initially and after any design or process change that may affect these parameters.

2.5V

OUTPUT

= 50Ω

5pF

INCLUDING

JIG AND

SCOPE

R = 1667Ω

R = 1538Ω

(b)

V

DDQ

GND

≤ 1ns

ALL INPUT PULSES

10%

90%

10%

≤ 1ns

(c)

Document #: 38-05556 Rev. *F Page 20 of 29

[+] Feedback

CY7C1371D CY7C1373D

Switching Characteristics Over the Operating Range

Parameter Description

[19]

t

POWER

Clock

t

CYC

t

CH

t

CL

Output Times

t

CDV

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Setup Times

t

AS

t

ALS

t

WES

t

CENS

t

DS

t

CES

Hold Times

t

AH

t

ALH

t

WEH

t

CENH

t

DH

t

CEH

Clock Cycle Time 7.5 10 ns

Clock HIGH 2.1 2.5 ns

Clock LOW 2.1 2.5 ns

Data Output Valid After CLK Rise 6.5 8.5 ns

Data Output Hold After CLK Rise 2.0 2.0 ns

Clock to Low-Z

Clock to High-Z

[20, 21, 22]

OE LOW to Output Valid 3.2 3.8 ns

OE LOW to Output Low-Z

OE HIGH to Output High-Z

[20, 21, 22]

Address Setup Before CLK Rise 1.5 1.5 ns

ADV/LD Setup Before CLK Rise 1.5 1.5 ns

WE, BWX Setup Before CLK Rise 1.5 1.5 ns

CEN Setup Before CLK Rise 1.5 1.5 ns

Data Input Setup Before CLK Rise 1.5 1.5 ns

Chip Enable Setup Before CLK Rise 1.5 1.5 ns

Address Hold After CLK Rise 0.5 0.5 ns

ADV/LD Hold After CLK Rise 0.5 0.5 ns

WE, BWX Hold After CLK Rise 0.5 0.5 ns

CEN Hold After CLK Rise 0.5 0.5 ns

Data Input Hold After CLK Rise 0.5 0.5 ns

Chip Enable Hold After CLK Rise 0.5 0.5 ns

[23, 24]

133 MHz 100 MHz

UnitMin Max Min Max

11ms

2.0 2.0 ns

4.0 5.0 ns

00ns

4.0 5.0 ns

Notes:

19. This part has a voltage regulator internally; t can be initiated.

, t

20. t

CHZ

21. At any voltage and temperature, t

22. This parameter is sampled and not 100% tested.

23. Timing reference level is 1.5V when V

24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

CLZ

These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

OELZ

, and t

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

OEHZ

POWER

is less than t

= 3.3V and is 1.25V when V

DDQ

Document #: 38-05556 Rev. *F Page 21 of 29

is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation

and t

OELZ

is less than t

CHZ

DDQ

to eliminate bus contention between SRAMs when sharing the same data bus.

CLZ

= 2.5V.

[+] Feedback

Switching Waveforms

Read/Write Waveforms

[25, 26, 27]

CY7C1371D CY7C1373D

CLK

CEN

CE

ADV/LD

WE

BWX

ADDRESS

DQ

123456789

t

CENS

CENH

t

CES

CEH

A1 A2

t

AS

AH

t

CYC

t

CL

CH

A3

t

CDV

t

CLZ

D(A1) D(A2) Q(A4)Q(A3)

D(A2+1)

A4

t

DOH

A5 A6 A7

t

OEV

t

Q(A4+1)

CHZ

D(A5)

10

D(A7)Q(A6)

t

READ

Q(A4)

OEHZ

Q(A4+1)

BURST

READ

t

OELZ

WRITE

D(A5)

t

DOH

READ Q(A6)

OE

COMMAND

WRITE

D(A1)

t

DS

WRITE

D(A2)

t

DH

BURST WRITE

D(A2+1)

READ

Q(A3)

DON’T CARE UNDEFINED

Notes:

For this waveform ZZ is tied LOW.

25.

26. When CE

27. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

WRITE

D(A7)

DESELECT

Document #: 38-05556 Rev. *F Page 22 of 29

[+] Feedback

Switching Waveforms (continued)

NOP, STALL AND DESELECT Cycles

[25, 26, 28]

CY7C1371D CY7C1373D

CLK

CEN

CE

ADV/LD

WE

[A:D]

BW

ADDRESS

DQ

COMMAND

123

A1 A2

456 78910

A3 A4

Q(A2)D(A1) Q(A3)

READ Q(A3)

D(A1)

READ

Q(A2)

STALL NOP READ

WRITE D(A4)

A5

t

CHZ

D(A4)

STALLWRITE

Q(A5)

t

DOH

DESELECT CONTINUE

DESELECT

DON’T CARE UNDEFINED

Note:

28. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN

Document #: 38-05556 Rev. *F Page 23 of 29

being used to create a pause. A write is not performed during this cycle.

[+] Feedback

Switching Waveforms (continued)

ZZ Mode Timing

[29, 30]

CLK

t

ZZ

CY7C1371D

t

ZZRE C

CY7C1373D

I

SUPPLY

ALL INPUTS

(except ZZ)

Outputs (Q)

ZZ

t

ZZI

I

DDZZ

High-Z

t

RZZI

DESELECT or READ Only

DON’T CARE

Notes:

29. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.

30. DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05556 Rev. *F Page 24 of 29

[+] Feedback

CY7C1371D

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code

133 CY7C1371D-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1373D-133AXC

CY7C1371D-133BGC 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1373D-133BGC

CY7C1371D-133BGXC 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1373D-133BGXC

CY7C1371D-133BZC 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1373D-133BZC

CY7C1371D-133BZXC 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1373D-133BZXC

CY7C1371D-133AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial

CY7C1373D-133AXI

CY7C1371D-133BGI 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1373D-133BGI

CY7C1371D-133BGXI 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1373D-133BGXI

CY7C1371D-133BZI 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1373D-133BZI

CY7C1371D-133BZXI 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1373D-133BZXI

100 CY7C1371D-100AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial

CY7C1373D-100AXC

CY7C1371D-100BGC 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1373D-100BGC

CY7C1371D-100BGXC 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1373D-100BGXC

CY7C1371D-100BZC 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1373D-100BZC

CY7C1371D-100BZXC 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1373D-100BZXC

CY7C1371D-100AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial

CY7C1373D-100AXI

CY7C1371D-100BGI 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1373D-100BGI

CY7C1371D-100BGXI 51-85115 119-Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

CY7C1373D-100BGXI

CY7C1371D-100BZI 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1373D-100BZI

CY7C1371D-100BZXI 51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1373D-100BZXI

Package Diagram Part and Package Type

CY7C1373D

Operating

Range

Document #: 38-05556 Rev. *F Page 25 of 29

[+] Feedback

Package Diagrams

Figure 1. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050

16.00±0.20

14.00±0.10

20.00±0.10

22.00±0.20

100

1

30

81

80

0.30±0.08

0.65 TYP.

51

0513

12°±1°

(8X)

CY7C1371D CY7C1373D

1.40±0.05

SEE DETAIL

0.20 MAX.

A

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

0° MIN.

R 0.08 MIN.

0.20 MIN.

0.20 MAX.

DETAIL

1.60 MAX.

STAND-OFF

0.05 MIN.

0.15 MAX.

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

3. DIMENSIONS IN MILLIMETERS

SEATING PLANE

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

A

0.10

51-85050-*B

Document #: 38-05556 Rev. *F Page 26 of 29

[+] Feedback

Package Diagrams (continued)

A1 CORNER

2165437

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

Ø1.00(3X) REF.

1.27

19.50

20.32

22.00±0.20

10.16

CY7C1371D CY7C1373D

Ø0.05 M C

Ø0.25MCAB

Ø0.75±0.15(119X)

2143657

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

0.70 REF.

12.00

30° TYP.

0.90±0.05

0.25 C

SEATING PLANE

C

0.56

2.40 MAX.

0.15 C

0.60±0.10

A

B

0.15(4X)

3.81

7.62

14.00±0.20

1.27

51-85115-*B

Document #: 38-05556 Rev. *F Page 27 of 29

[+] Feedback

Package Diagrams (continued)

Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)

CY7C1371D CY7C1373D

15.00±0.10

A

0.25 C

B

0.53±0.05

0.36

PIN 1 CORNER

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

C

SEATING PLANE

TOP VIEW

13.00±0.10

BOTTOM VIEW

1110986754321

14.00

15.00±0.10

A

0.15(4X)

11

1.00

7.00

5.00

10.00

B

13.00±0.10

Ø0.05 M C

Ø0.25MCAB

-0.06

Ø0.50 (165X)

+0.14

1.00

PIN 1 CORNER

2345678910

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

NOTES :

1.40 MAX.

0.15 C

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

0.35±0.06

51-85180-*A

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05556 Rev. *F Page 28 of 29

© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

[+] Feedback

CY7C1371D

Document History Page

Document Title: CY7C1371D/CY7C1373D 18-Mbit (512K x 36/1 Mbit x 18) flow through SRAM with NoBL™ Architecture Document Number: 38-05556

REV. ECN NO.

Date

** 254513 See ECN RKF New data sheet

*A 288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

*B 326078 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified

*C 345117 See ECN PCI Updated Ordering Information Table

*D 416321 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901

*E 475677 See ECN VKN Added the Maximum Rating for Supply Voltage on V

*F 1274734 See ECN VKN/AESA Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform

Issue

Orig. of

Change Description of Change

non-compliance with 1149.1 Removed 117 Mhz Speed Bin Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA Packages Added comment of ‘Pb-free BG packages availability’ below the Ordering Information

according to JEDEC standard Added description on EXTEST Output Bus Tri-State Changed description on the Tap Instruction Set Overview and Extest Changed Θ °C/W respectively Changed Θ respectively Changed Θ °C/W respectively Modified V Removed comment of ‘Pb-free BG packages availability’ below the Ordering Infor-

and Θ

JA

and Θ

JA

and Θ

JA

OL, VOH

for TQFP Package from 31 and 6 °C/W to 28.66 and 4.08

JC

for BGA Package from 45 and 7 °C/W to 23.8 and 6.2 °C/W

JC

for FBGA Package from 46 and 3 °C/W to 20.7 and 4.0

JC

test conditions

mation Updated Ordering Information Table

Changed from Preliminary to Final

North First Street” to “198 Champion Court” In the Partial Truth Table for Read/Write on page # 10, the BW (DQ

and DQPA) and BWB of Write Byte B – (DQB and DQPB) has been changed

A

from H to L Changed the description of IX from Input Load Current to Input Leakage Current on page# 20 Changed the Ix current values of MODE on page # 20 from -5 µA and 30 µA to -30 µA and 5 µA Changed the Ix current values of ZZ on page # 20 from -30 µA and 5 µA to -5 µA and 30 µA Changed V Replaced Package Name column with Package Diagram in the Ordering

IH

< V

to VIH < VDDon page # 20

DD

Information table Updated Ordering Information Table

, t

Changed t Switching Characteristics table.

from 25 ns to 20 ns and t

TH

TL

from 5 ns to 10 ns in TAP AC

TDOV

Updated the Ordering Information table.

CY7C1373D

of Write Byte A –

A

Relative to GND

DDQ

Document #: 38-05556 Rev. *F Page 29 of 29

[+] Feedback

Cypress Semiconductor CY7C1371D, CY7C1373D Specification Sheet

Specifications and Main Features

Frequently Asked Questions

User Manual