CY7C1365C
9-Mbit (256K x 32) Flow-Through Sync SRAM
Features
• 256K x 32 common I/O
• 3.3V core power supply (V
• 2.5V/3.3V I/O power supply (V
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Supports 3.3V I/O level
• Available in JEDEC-standard lead-free 100-Pin TQFP
package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• “ZZ” Sleep Mode option
DD
)
DDQ
)
®
Functional Description
[1]
The CY7C1365C is a 256K x 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-trigg ered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE2 and CE
1
Control inputs (ADSC
(BW
[A:D], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE
, ADSP, and ADV), Write Enables
) and the ZZ pin
[2]
3
), Burst
.
The CY7C1365C allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP
Address Strobe (ADSC
) inputs. Address advancement is
controlled by the Address Advancement (ADV
) or the cache Controller
) input.
Addresses and Chip Enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC
) are active. Subsequent
) or
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1365C operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.5 ns
Maximum Operating Current 250 180 mA
Maximum Standby Current 40 40 mA
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
is not available on 2 Chip Enable TQFP package.
2.
CE
3
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05690 Rev . *E Revised September 14, 2006
[+] Feedback
s
A
Logic Block Diagram-CY7C1365C (256K x 32)
CY7C1365C
0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
BW
BW
BW
A
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
BURST
COUNTER
AND LOGIC
CLR
DQ
D
C
B
D
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
DQ
C
BYTE
WRITE REGISTER
DQ
B
BYTE
WRITE REGISTER
DQ
A
BYTE
WRITE REGISTER
ENABLE
REGISTER
Q1
Q0
A
[1:0]
DQ
D
BYTE
WRITE REGISTER
DQ
C
BYTE
WRITE REGISTER
DQ
B
BYTE
WRITE REGISTER
DQ
A
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
DQ
ZZ
SLEEP
CONTROL
Document #: 38-05690 Rev. *E Page 2 of 18
[+] Feedback
Pin Configurations
100-Pin TQFP Pinout (2 Chip Enable) (AJ version)
C
BWSBBWS
A
DDVSS
A
V
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100
CE
CE
BWSDBWS
99989796959493929190898887868584838281
2
1
A
CY7C1365C
A
BYTE C
BYTE D
V
V
V
V
V
V
V
V
DQ
DQ
DDQ
SSQ
DQ
DQ
DQ
DQ
SSQ
DDQ
DQ
DQ
V
NC
V
DQ
DQ
DDQ
SSQ
DQ
DQ
DQ
DQ
SSQ
DDQ
DQ
DQ
NC
NC
DD
SS
NC
1
2
C
3
C
4
5
6
C
7
C
8
C
9
C
10
11
12
C
13
C
14
15
CY7C1365C
16
17
18
D
19
D
20
21
22
D
23
D
24
D
25
D
26
27
28
D
29
D
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
NC
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
BYTE B
BYTE A
31323334353637383940414243444546474849
MODE
Document #: 38-05690 Rev. *E Page 3 of 18
AAAAA1A
50
0
NC
NC
SS
DD
NC
NC
V
V
AAAAA
A
A
[+] Feedback
Pin Configurations (continued)
100-Pin TQFP Pinout (3 Chip Enable) (A version)
A
100
C
BWSBBWS
A
3
CE
VDDV
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
2
1
A
CE
CE
BWSDBWS
99989796959493929190898887868584838281
CY7C1365C
A
BYTE C
BYTE D
V
V
V
V
V
V
V
V
DQ
DQ
DDQ
SSQ
DQ
DQ
DQ
DQ
SSQ
DDQ
DQ
DQ
V
NC
V
DQ
DQ
DDQ
SSQ
DQ
DQ
DQ
DQ
SSQ
DDQ
DQ
DQ
NC
NC
DD
SS
NC
1
2
C
3
C
4
5
6
C
7
C
8
C
9
C
10
11
12
C
13
C
14
15
CY7C1365C
16
17
18
D
19
D
20
21
22
D
23
D
24
D
25
D
26
27
28
D
29
D
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
NC
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
BYTE B
BYTE A
31323334353637383940414243444546474849
MODE
Document #: 38-05690 Rev. *E Page 4 of 18
AAAAA1A
50
0
NC
NC
SS
DD
A
NC
V
V
AAAAA
A
A
[+] Feedback
CY7C1365C
Pin Descriptions
Name TQFP I/O Description
A0, A1, A 37,36,32,33,34,35,44,45,46,
47,48,49,50,81,82,99,100
92 (for 2 Chip Enable Version)
43 (for 3 Chip Enable Version)
BW
BW
A, BWB,
C, BWD
93,94,
95,96
GW 88 Input-
BWE 87 Input-
CLK 89 Input-Clock Clock Input. Used to capture all synchronous inputs to the device.
CE
CE
CE
OE
ADV
1
2
3
98 Input-
97 Input-
92 (for 3 Chip Enable Version) Input-
86 Input-
83 Input-
ADSP 84 Input-
ADSC
85 Input-
ZZ 64 Input-
DQs 52,53,56, 57,58,59, 62,63,68,
69,72,73,74,75,78,79,2,3,6,7,
8,9,12,13,18,19,22,23,24,25,
28,29
Input-
Synchronous
Input-
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Asynchronous
I/O-
Synchronous
Address Inputs used to select one of the 256K address
locations. Sampled at the rising edge of the CLK if ADSP
is active LOW, and CE
the 2-bit counter.
, and CE3 are sampled active. A
1, CE2
or ADSC
feed
[1:0]
Byte Write Select Inputs, active LOW. Qualified with BWE to
conduct Byte Writes to the SRAM. Sampled on the rising edge of
CLK.
Global Write Enable Input, active LOW. When asserted LOW on
the rising edge of CLK, a global write is conducted (ALL bytes are
written, regardless of the values on BW
and BWE).
[A:D]
Byte Write Enable Input, active LOW. Sampled on the rising edge
of CLK. This signal must be asserted LOW to conduct a Byte Write.
Also used to increment the burst counter when ADV
is asserted LOW,
during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of
CLK. Used in conjunction with CE
device. ADSP
is ignored
if CE
a new external address is loaded.
and CE3 to select/deselect the
2
is HIGH.
1
is sampled only when
CE
1
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of
CLK. Used in conjunction with CE
device. CE
is sampled only when a new external address is loaded.
2
and CE3 to select/deselect the
1
Chip Enable 3 Input, active LOW. Sampled on the rising edge of
CLK. Used in conjunction with CE
device. CE
CE
is sampled only when a new external address is loaded.
3
is assumed active throughout this document for BGA.
3
and CE2 to select/deselect the
1
Output Enable, asynchronous input, active LOW. Controls the
direction of the I/O pins. When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE
is masked during the first clock of a Read cycle when
emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When
asserted, it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of
CLK, active LOW. When asserted LOW , addresses presented to the
device are captured in the address registers. A
into the burst counter. When ADSP
only ADSP
is recognized. ASDP is ignored when
and ADSC are both asserted,
HIGH.
are also loaded
[1:0]
is deasserted
CE
1
Address Strobe from Controller, sampled on the rising edge of
CLK, active LOW. When asserted LOW , addresses presented to the
device are captured in the address registers. A
into the burst counter. When ADSP
only ADSP
is recognized.
and ADSC are both asserted,
are also loaded
[1:0]
ZZ “sleep” Input, active HIGH. When asserted HIGH places the
device in a non-time-critical “sleep” condition with data integrity
preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip
data register that is triggered by the rising edge of CLK. As outputs,
they deliver the data contained in the memory location specified by
the addresses presented during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE
. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQs are
placed in a tri-state condition.
Document #: 38-05690 Rev. *E Page 5 of 18
[+] Feedback
Pin Descriptions (continued)
Name TQFP I/O Description
V
DD
V
SS
V
DDQ
V
SSQ
MODE 31 Input-
NC 1,30,51,80,14,16,38,39,42,66
15,41,65, 91 Power Supply Power supply inputs to the core of the device.
17,40,67,90 Ground Ground for the core of the device.
4,1 1,20,27,54,61,70,77
,
I/O Power
Supply
Power supply for the I/O circuitry.
5,10,21,26,55,60,71,76 I/O Ground Ground for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear burst
Static
sequence. When tied to V
sequence. This is a strap pin and should remain static during device
or left floating selects interleaved burst
DD
operation. Mode Pin has an internal pull-up.
No Connects. Not Internally connected to the die.
43 (for 2 Chip Enable Version)
CY7C1365C
Document #: 38-05690 Rev. *E Page 6 of 18
[+] Feedback
CY7C1365C
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access d elay from
the clock rise (t
The CY7C1365C supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486 processors.
The linear burst sequence is suited for processors that utilize
a linear burst sequence. The burst order is user-selectable,
and is determined by sampling the MODE input. Accesses can
be initiated with either the Processor Address Strobe (ADSP
or the Controller Address Strobe (ADSC
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter
captures the first address in a burst sequence and au tomatically increments the address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
) and Byte Write Select (BW[A:D]) inputs. A Global Write
(BWE
Enable (GW
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP
the access is initiated by ADSC
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE
input is asserted LOW, the requested data will be
available at the data outputs a maximum to t
rise. ADSP
is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, and (2) ADSP
presented are loaded into the address register and the burst
inputs (GW
, BWE, and BW[A:D]) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device.Byte writes are allowed.
During byte writes, BWA
DQB, BWC
controls DQC, and BWD controls DQD. All I/Os
are tri-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri -stated
once a write cycle is detected, regardless of the state of OE
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
) is 6.5 ns (133-MHz device).
CDV
). Address
) overrides all byte write inputs and writes data to
) provide for easy bank
is ignored if CE
, CE2, and CE3 are all
1
or ADSC is asserted LOW (if
, the write inputs must be
after clock
CDV
, CE2, CE3 are all asserted
1
is asserted LOW. The addresses
controls DQA and BWB controls
, CE2, and CE3 are all asserted
1
active, (2) ADSC
HIGH, and (4) the write input signals (GW
indicate a write access. ADSC
is asserted LOW, (3) ADSP is deasserted
, BWE, and BW[A:D])
is ignored if ADSP is active
LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[D:A] will be
written into the specified address location. Byte writes are
allowed. During byte writes, BWA
DQB, BWC
controls DQC, and BWD controls DQD. All I/Os
controls DQA, BWB controls
are tri-stated when a write is detected, even a byte write. Since
)
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless
of the state of OE
.
Burst Sequences
The CY7C1365C provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter-
1
leaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of t
LOW.
after the ZZ input returns
ZZREC
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
A1, A0
DD
)
Third
Address
A1, A0
Linear Burst Address Table (MODE = GND)
First
Address
A1, A
.
0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
A1, A
0
Third
Address
A1, A
0
Fourth
Address
A1, A0
Fourth
Address
A1, A
0
Document #: 38-05690 Rev. *E Page 7 of 18
[+] Feedback
CY7C1365C
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
Cycle Description
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Sleep Mode, Power-down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L L H L L X X X L L-H Q
Read Cycle, Begin Burst External L L H L L X X X H L-H Tri-State
Write Cycle, Begin Burst External L L H L H L X L X L-H D
Read Cycle, Begin Burst External L L H L H L X H L L-H Q
Read Cycle, Begin Burst External L L H L H L X H H L-H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
Write Cycle, Suspend Burst Current X X X L H H H L X L-H D
Write Cycle, Suspend Burst Current H X X L X H H L X L-H D
Sleep mode standby current ZZ > VDD – 0.2V 50 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ Active to Sleep current This parameter is sampled 2t
CYC
CYC
ZZ Inactive to exit Sleep current This parameter is sampled 0 ns
[3, 4, 5, 6, 7]
Address
Used CE1CE3CE2ZZ ADSP ADSC ADV WRITE OE CLK DQ
None H X X L X L X X X L-H Tri-State
None L X L L L X X X X L-H Tri-State
None L H X L L X X X X L-H Tri-State
None L X L L H L X X X L-H Tri-State
None X X X L H L X X X L-H Tri-State
ns
ns
ns
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE
5. The DQ pins are controlled by the current cycle and the OE
6. The SRAM always initiates a Read cycle when ADSP
7. OE
= L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
(BW
, BWB, BWC, BWD), BWE, GW = H.
A
after the ADSP
don't care for the remainder of the Write cycle.
is asynchronous and is not sampled with the clock rise. It is masked inte rnally during W ri te cycles. Durin g a read cycle all dat a bi ts are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE
or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
Document #: 38-05690 Rev. *E Page 8 of 18
signal. OE is asynchronous and is not sampled with the clock.
is asserted, regardless of the state of GW, BWE, or BW
is active (LOW).
. Writes may occur only on subsequent clocks
[A: D]
[+] Feedback
CY7C1365C
Truth Table for Read/Write
Function GW BWE BW
[3, 4]
D
BW
C
BW
B
BW
A
Read HHXXXX
Read HLHHHH
Write Byte (A, DQP
Write Byte (B, DQP
Write Bytes (B, A, DQP
Write Byte (C, DQP
Write Bytes (C, A, DQP
Write Bytes (C, B, DQP
Write Bytes (C, B, A, DQP
Write Byte (D, DQP
Write Bytes (D, A, DQP
Write Bytes (D, B, DQP
Write Bytes (D, B, A, DQP
Write Bytes (D, B, DQP
Write Bytes (D, B, A, DQP
Write Bytes (D, C, A, DQP
) HLHHHL
A
)HLHHLH
B
, DQPB)HLHHLL
A
) HLHLHH
C
, DQPA) HLHLHL
C
, DQPB)HLHLLH
C
, DQPB, DQPA)HLHLLL
C
) HLLHHH
D
, DQPA)HLLHHL
D
, DQPA)HLLHLH
D
, DQPB, DQPA)H L L H L L
D
, DQPB) HLLLHH
D
, DQPC, DQPA)HLLLHL
D
, DQPB, DQPA)HLLLLH
D
Write All Bytes HLLLLL
Write All Bytes L XXXXX
Document #: 38-05690 Rev. *E Page 9 of 18
[+] Feedback
CY7C1365C
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ......................... .. ... ...–65°C to +150°C
Ambient Temperature with
Power Applied..................................... ........–55°C to +125°C
Supply Voltage on V
Supply Voltage on V
DC Voltage Applied to Outputs
in Tri-State...........................................–0.5V to V
Electrical Characteristics
Relative to GND........–0.5V to +4.6V
DD
Relative to GND......–0.5V to +V
DDQ
+ 0.5V
DDQ
Over the Operating Range
DD
DC Input Voltage............................... ... .–0.5V to V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Commercial 0°C to +70°C 3.3V –
Industrial –40°C to +85°C
[8, 9]
Parameter Description Test Conditions
V
V
DD
DDQ
Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage for 3.3V I/O 3.135 3.6 V
for 2.5V I/O 2.375 2.625 V
V
OH
V
OL
V
IH
Output HIGH Voltage for 3.3V I/O, I
for 2.5V I/O, I
Output LOW Voltage for 3.3V I/O, I
for 2.5V I/O, I
= –4.0 mA 2.4 V
OH
= –1.0 mA 2.0 V
OH
= 8.0 mA 0.4 V
OL
= 1.0 mA 0.4 V
OL
Input HIGH Voltage for 3.3V I/O 2.0 VDD + 0.3V V
for 2.5V I/O 1.7 V
V
IL
Input LOW Voltage
[8]
for 3.3V I/O –0.3 0.8 V
for 2.5V I/O –0.3 0.7 V
I
X
I
OZ
I
DD
I
SB1
I
SB2
I
SB3
I
SB4
Input Leakage Current
GND ≤ VI ≤ V
except ZZ and MODE
Input Current of MODE Input = V
Input = V
Input Current of ZZ Input = V
Input = V
SS
DD
SS
DD
Output Leakage Current GND ≤ VI ≤ V
V
Operating Supply Current V
DD
Automatic CE Power-Down
Current—TTL Inputs
Automatic CE Power-Down
Current—CMOS Inputs
Automatic CE Power-Down
Current—CMOS Inputs
Automatic CE Power-Down
Current—TTL Inputs
= Max., I
DD
= 1/t
f = f
MAX
CYC
Max. VDD, Device Deselected,
V
≥ VIH or VIN ≤ VIL, f = f
IN
inputs switching
Max. VDD, Device Deselected,
V
≥ VDD – 0.3V or VIN ≤ 0.3V,
IN
f = 0, inputs static
Max. VDD, Device Deselected,
V
IN
f = f
≥ V
– 0.3V or VIN ≤ 0. 3V ,
DDQ
, inputs switching
MAX
Max. VDD, Device Deselected,
≥ VIH or VIN ≤ VIL, f = 0,
V
IN
inputs static.
DDQ
, Output Disabled –5 5 µA
DDQ
OUT
= 0 mA,
7.5-ns cycle, 133 MHz 250 mA
10-ns cycle, 100 MHz 180 mA
All speeds 110 mA
MAX,
All speeds 40 mA
All speeds 100 mA
All speeds 40 mA
Ambient
Temperature V
5%/+10%
–30 µA
+ 0.5V
DD
DD
V
DDQ
2.5V – 5% to
V
DD
CY7C1365C
UnitMin. Max.
+ 0.3V V
DD
−55µA
5 µA
–5 µA
30 µA
Notes:
8. Overshoot: V
9. T
Power-up
(AC) < VDD +1.5V (Pulse width less than t
IH
: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and V
Document #: 38-05690 Rev. *E Page 10 of 18
/2), undershoot: VIL(AC) > –2V (Pulse width less than t
CYC
DDQ
< VDD.
CYC
/2).
[+] Feedback
CY7C1365C
Capacitance
[10]
Parameter Description T e st Con dit ion s
C
IN
C
CLK
C
I/O
Thermal Resistance
Input Capacitance TA = 25°C, f = 1 MHz,
Clock Input Capacitance 5 pF
Input/Output Capacitance 5 pF
[10]
V
V
DDQ
Parameter Description Test Conditions
Θ
JA
Thermal Resistance
Θ
JC
Thermal Resistance
(Junction to Ambient)
(Junction to Case)
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
Z
0
2.5V I/O Test Load
OUTPUT
Z
0
3.3V
= 50Ω
R
VT= 1.5V
(a) (b)
= 50Ω
V
T
R
= 1.25V
= 50Ω
L
= 50Ω
L
OUTPUT
INCLUDING
JIG AND
SCOPE
2.5V
OUTPUT
INCLUDING
JIG AND
SCOPE
(a) (b)
5pF
5pF
R = 317Ω
R = 351Ω
R = 1667Ω
R =1538Ω
DD
= 3.3V
= 2.5V
V
V
DDQ
GND
DDQ
GND
≤ 1 ns
≤ 1 ns
100 TQFP
100 TQFP
Package Unit
29.41 °C/W
ALL INPUT PULSES
10%
10%
90%
ALL INPUT PULSES
90%
Max. Unit
5pF
6.13 °C/W
90%
10%
≤ 1 ns
(c)
90%
10%
≤ 1 ns
(c)
Notes:
10.Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05690 Rev. *E Page 11 of 18
[+] Feedback
CY7C1365C
Switching Characteristics Over the Operating Range
Parameter Description
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CDV
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
t
AH
t
ADH
t
WEH
t
ADVH
t
DH
t
CEH
VDD(Typical) to the First Access
Clock Cycle Time 7.5 10 ns
Clock HIGH 3.0 4.0 ns
Clock LOW 3.0 4.0 ns
Data Output Valid after CLK Rise 6.5 8.5 ns
Data Output Hold after CLK Rise 2.0 2.0 ns
Clock to Low-Z
Clock to High-Z
[14, 15, 16]
[14, 15, 16]
OE LOW to Output Valid 3.5 3.5 ns
OE LOW to Output Low-Z
OE HIGH to Output High-Z
Address Set-up before CLK Rise 1.5 1.5 ns
ADSP, ADSC Set-up before CLK Rise 1.5 1.5 ns
ADV Set-up before CLK Rise 1.5 1.5 ns
GW, BWE, BW
Set-up before CLK Rise 1.5 1.5 ns
[A:D]
Data Input Set-up before CLK Rise 1.5 1.5 ns
Chip Enable Set-up 1.5 1.5 ns
Address Hold after CLK Rise 0.5 0.5 ns
ADSP, ADSC Hold after CLK Rise 0.5 0.5 ns
GW
,
BWE, BW
Hold after CLK Rise
[A:D]
ADV Hold after CLK Rise 0.5 0.5 ns
Data Input Hold after CLK Rise 0.5 0.5 ns
Chip Enable Hold after CLK Rise 0.5 0.5 ns
[13]
[14, 15, 16]
[14, 15, 16]
[11, 12]
–133 –100
UnitMin. Max. Min. Max.
11ms
00ns
3.5 3.5 ns
00ns
3.5 3.5 ns
0.5 0.5 ns
Notes:
11.Timing reference level is 1.5V when V
12.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
13.This part has a voltage regulator internally; t
can be initiated.
, t
14.t
CHZ
15.At any given voltage and temperature, t
data bus. These specifications do not imply a bus conten tion c ondi tion, b ut reflect p a rameters gu aran tee d over worst case u se r condi tio ns. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
16.This parameter is sampled and not 100% tested.
CLZ,tOELZ
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
= 3.3V and is 1.25V when V
DDQ
POWER
OEHZ
Document #: 38-05690 Rev. *E Page 12 of 18
= 2.5V.
DDQ
is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operat ion
is less than t
OELZ
and t
is less than t
CHZ
to eliminate bus contention between SRAMs when sharing the same
CLZ
[+] Feedback
Timing Diagrams
G
Read Cycle Timing
[17]
t
CYC
CY7C1365C
CLK
ADSP
ADSC
ADDRESS
W, BWE,BW
[A:D]
CE
ADV
OE
Data Out (Q)
Note:
17.On this diagram, when CE
High-Z
t
t
CL
CH
t
t
ADH
ADS
t
t
ADH
ADS
t
t
AH
AS
A1
t
WES
t
t
CES
CEH
t
WEH
A2
t
ADVS
t
ADVH
Deselect Cycle
ADV suspends burst.
t
CDV
t
DOH
Q(A2) Q(A2 + 1) Q(A2 + 2)
Q(A2) Q(A2 + 1) Q(A2 + 2)Q(A2 + 3)
Burst wraps around
to its initial state
t
t
CLZ
OEV
t
CDV
t
OEHZ
Q(A1)
t
OELZ
Single READ BURST
READ
DON’T CARE
is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
UNDEFINED
t
CHZ
Document #: 38-05690 Rev. *E Page 13 of 18
[+] Feedback
Timing Diagrams (continued)
D
Write Cycle Timing
[18, 19]
t
CYC
CY7C1365C
ADSP
ADSC
ADDRESS
BWE,
BW
[A:D]
GW
CE
CLK
t
t
CL
CH
t
t
ADH
ADS
t
t
ADH
ADS
t
t
AH
AS
A1
A2 A3
Byte write signals are ignored for first cycle when
ADSP initiates burst.
t
t
CEH
CES
t
WES
t
WEH
ADSC extends burst.
t
ADS
t
ADH
t
t
ADVS
WES
t
WEH
t
ADVH
ADV
ADV suspends burst.
OE
t
t
DH
DS
Data in (D)
High-Z
t
OEHZ
D(A1)
D(A2) D(A2 + 1) D(A2 + 1)
D(A2 + 2)
D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)
ata Out (Q)
BURST READ BURST WRITE
Single WRITE
Extended BURST WRITE
DON’T CARE UNDEFINED
Notes:
18.Full width write can be initiated by either GW
19.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP
Document #: 38-05690 Rev. *E Page 14 of 18
LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.
, ADSC, or ADV cycle is performed.
[+] Feedback
Timing Diagrams (continued)
t
Read/Write Timing
[17, 19, 20]
CYC
CY7C1365C
CLK
ADSP
ADSC
ADDRESS
BWE, BW[A:D]
CE
ADV
OE
Data In (D)
Data Out (Q)
t
t
CL
CH
t
t
ADH
ADS
t
t
AH
AS
t
CES
A2
t
CEH
A1 A5 A6
High-Z
Q(A1)
Q(A2)
A3 A4
t
OEHZ
t
WES
t
DS
D(A3)
t
t
DH
WEH
t
OELZ
t
CDV
Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)
D(A5) D(A6)
Note:
20.
GW
is HIGH.
Document #: 38-05690 Rev. *E Page 15 of 18
Single WRITE
BURST READBack-to-Back READs
DON’T CARE UNDEFINED
Back-to-Back
WRITEs
[+] Feedback
Timing Diagrams (continued)
A
ZZ Mode Timing
[21, 22]
CLK
CY7C1365C
t
ZZ
t
ZZREC
I
SUPPLY
LL INPUTS
ZZ
t
ZZI
I
DDZZ
t
RZZI
DESELECT or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz) Ordering Code
133 CY7C1365C-133AXC 51-85050
CY7C1365C-133AJXC 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1365C-133AXI 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1365C-133AJXI
100 CY7C1365C-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1365C-100AJXC 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1365C-100AXI
CY7C1365C-100AJXI
visit www.cypress.com for actual products offered.
Package
Diagram Package Typ e
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
(2 Chip Enable)
(3 Chip Enable)
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
(3 Chip Enable)
(2 Chip Enable)
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)
100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)
Operating
Range
Commercial
Industrial
Commercial
Industrial
Notes:
21.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
22.DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05690 Rev. *E Page 16 of 18
[+] Feedback
Package Diagram
R 0.08 MIN.
0.20 MAX.
0.25
GAUGE PLANE
0°-7°
0.60±0.15
1.00 REF.
20.00±0.10
22.00±0.20
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
14.00±0.10
100
1
30
31 50
0° MIN.
R 0.08 MIN.
0.20 MAX.
0.20 MIN.
A
DETAIL
81
80
0.30±0.08
0.65
TYP.
51
STAND-OFF
0.05 MIN.
0.15 MAX.
CY7C1365C
1.40±0.05
12°±1°
(8X)
SEATING PLANE
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
51-85050-*B
SEE DETAIL
0.20 MAX.
1.60 MAX.
0.10
A
Intel and Pentium are registered trademarks and i486 is a tr ademark of Intel Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05690 Rev. *E Page 17 of 18
© Cypress Semiconductor Corporation, 2006. The information contained herei n is subject to change without notice. Cypress S em ic onductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypres s does not auth orize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY7C1365C
Document History Page
Document Title: CY7C1365C 9-Mbit (256K x 32) Flow-Through Sync SRAM
Document Number: 38-05690
REV. ECN NO. Issue Date
** 286269 See ECN PCI New data sheet
*A 320834 See ECN PCI Added 133 MHz in the Ordering Information table
*B 377095 See ECN PCI Changed I
*C 408725 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from
*D 429278 See ECN NXR Added 2.5VI/O option
*E 501828 See ECN VKN Added the Maximum Rating for Supply Voltage on V
Orig. of
Change Description of Change
Changed Θ
6.13 °C/W respectively
Modified V
Corrected IDD, tCDV, tCH, tDOH and tCL for 100MHz to 180 mA, 8.5 ns, 4
and Θ
JA
OL, VOH
for TQFP Package from 25 and 9 °C/W to 29.41 and
JC
test conditions
ns, 2 ns and 4 ns respectively
Changed Snooze to Sleep in the ZZ Mode Electrical Characteristics and truth
table on page# 6
Added Industrial operating range
Updated Ordering Information Table
from 30 to 40 mA
Modified test condition in note# 9 from V
SB2
IH
< V
DD to VIH
“3901 North First Street” to “198 Champion Court”
Changed three state to tri-state
Converted from Preliminary to Final
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated the ordering information
Updated Ordering Information Table
Updated the Ordering Information table.
< V
DD
Relative to GND
DDQ
Document #: 38-05690 Rev. *E Page 18 of 18
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