Cypress Semiconductor CY7C1364C Specification Sheet

A

s

CY7C1364C

9-Mbit (256K x 32) Pipelined Sync SRAM

Features

• Registered inputs and outputs for pipelined operation

• 256K × 32 common I/O architecture

• 3.3V core power supply (V

• 2.5V/3.3V I/O power supply (V

• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel
Pentium

®

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Available in JEDEC-standard lead-free 100-Pin TQFP
package

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• “ZZ” Sleep Mode Option

DD

)

DDQ

)

®

Functional Description

[1]

The CY7C1364C SRAM integrates 256K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

), depth-expansion Chip Enables (CE2 and CE

1

Control inputs (ADSC
(BW
inputs include the Output Enable (OE

, and BWE), and Global Write (GW). Asynchronous

[A:D]

, ADSP, and ADV), Write Enables

) and the ZZ pin.

[2]

3

), Burst

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC

) are active. Subsequent

) or

burst addresses can be internally generated as controlled by
the Advance pin (ADV

).

Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW

causes all bytes to be written.

LOW

when active

The CY7C1364C operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

Logic Block Diagram-CY7C1364C (256K x 32)

0, A1, A

MODE

ADV

CLK

ADSC
ADSP

BW

D

BW

BW

BW

BWE

GW

C

B

A

CE

1

CE

2

CE

3

OE

ZZ

SLEEP

CONTROL

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
is not available on 2 Chip Enable TQFP package.

2. CE

3

ADDRESS
REGISTER

D

DQ

BYTE

WRITE REGISTER

C

DQ
BYTE

WRITE REGISTER

B

DQ

BYTE

WRITE REGISTER

DQA

BYTE

WRITE REGISTER

ENABLE

REGISTER

2

BURST

COUNTER

AND

CLR

LOGIC

PIPELINED

ENABLE

A

[1:0]

Q1

Q0

D

DQ

BYTE

WRITE DRIVER

C

DQ

BYTE

WRITE DRIVER

B

DQ

BYTE

WRITE DRIVER

A

DQ

BYTE

WRITE DRIVER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQ

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05689 Rev . *E Revised September 14, 2006

[+] Feedback

CY7C1364C

Selection Guide

250 MHz 200 MHz 166 MHz Unit

Maximum Access Time 2.8 3.0 3.5 ns
Maximum Operating Current 250 220 180 mA
Maximum CMOS Standby Current 40 40 40 mA

Pin Configuration

100-Pin TQFP Pinout (2 Chip Enables) (AJ version)

BYTE C

BYTE D

V

V

V

V

V

V

V

V

DQ
DQ

DDQ
SSQ

DQ
DQ
DQ
DQ

SSQ
DDQ

DQ
DQ

V

V
DQ
DQ

DDQ

SSQ

DQ
DQ
DQ
DQ

SSQ

DDQ

DQ
DQ

NC

NC

DD

NC

SS

NC

AACE1CE2BWDBWCBWBBWAA

100999897969594939291908988878685848382

1

C
C

2
3
4
5

C
C
C
C

6
7
8
9
10
11

C
C

12
13
14
15
16
17

D
D

18
19
20
21

D
D
D
D

22
23
24
25
26
27

D
D

28
29
30

VDDVSSCLKGWBWEOEADSC

CY7C1364C

ADSP

ADVAA

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

81

NC
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
V
NC
V
ZZ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
NC

DDQ
SSQ

SSQ
DDQ

SS

DD

DDQ
SSQ

SSQ
DDQ

B
B

B

BYTE B

B
B
B

B
B

A
A

A
A

BYTE A

A
A

A
A

Document #: 38-05689 Rev. *E Page 2 of 18

31323334353637383940414243444546474849

1

AAA

0

A

A

A

NC

NC

SS

DD

V

V

NC

NC

AAA

A

AAA

MODE

50

[+] Feedback

Pin Configuration (continued)

CY7C1364C

100-Pin TQFP Pinout (3 Chip Enables) (A version)

BYTE C

BYTE D

V

V

V

V

V

V

V

V

DQ
DQ

DDQ

SSQ

DQ
DQ
DQ
DQ

SSQ

DDQ

DQ
DQ

V

V
DQ
DQ

DDQ

SSQ

DQ
DQ
DQ
DQ

SSQ

DDQ

DQ
DQ

NC

NC

DD

NC

SS

NC

AACE1CE2BWDBWCBWBBWACE3VDDVSSCLKGWBWEOEADSC

100999897969594939291908988878685848382

1

C
C

2
3
4
5

C
C
C
C

6
7
8
9
10
11

C
C

12
13
14
15

CY7C1364C

16
17

D
D

18
19
20
21

D
D
D
D

22
23
24
25
26
27

D
D

28
29
30

ADSP

ADVAA

81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
V
NC
V
ZZ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
NC

DDQ
SSQ

SSQ
DDQ

SS

DD

DDQ
SSQ

SSQ
DDQ

B
B

B

BYTE B

B
B
B

B
B

A
A

A
A

BYTE A

A
A

A
A

31323334353637383940414243444546474849

1

AAA

0

A

A

A

NC

NC

SS

V

A

NC

AAA

DD

V

A

50

AAA

MODE

Document #: 38-05689 Rev. *E Page 3 of 18

[+] Feedback

Pin Definitions

Name TQFP I/O Description

, A1, A 37, 36, 32, 33, 34, 35, 43,

A

0

44, 45, 46, 47, 48, 49, 50,

Input-

Synchronous

81, 82, 99, 100

BW
BW

, BWB

A

, BW

C

D

93, 94, 95, 96 Input-

Synchronous

GW 88 Input-

Synchronous

BWE

87 Input-

Synchronous

CLK 89 Input-

Clock

CE

CE

CE

OE

1

2

3

(for 3 Chip Enable Version)

98 Input-

Synchronous

97 Input-

Synchronous

92

Input-

Synchronous

86 Input-

Asynchronous

ADV 83 Input-

Synchronous

ADSP

84 Input-

Synchronous

ADSC

85 Input-

Synchronous

ZZ 64 Input-

Asynchronous

DQs 52, 53, 56, 57, 58, 59, 62,

63, 68, 69, 72, 73, 74, 75,

I/O-

Synchronous
78, 79, 2, 3, 6, 7, 8, 9, 12,
13, 18, 19, 22, 23, 24, 25,
28, 29

V

DD

V

SS

15, 41, 65, 91 Power Supply Power supply inputs to the core of the device.
17, 40, 67, 90 Ground Ground for the core of the device.

Address Inputs used to select one of the 256K address locations.
Sampled at the rising edge of the CLK if ADSP
and CE

, CE2, and CE3 are sampled active. A

1

Byte Write Select In puts, active L OW. Qualified with BWE to conduct
byte writes to the SRAM. Sampled on the rising edge of CLK.

Global Write Enable Input, active LOW. When asserted LOW on the
rising edge of CLK, a global Write is conducted (ALL bytes are written,
regardless of the values on BW

[A:D]

Byte Write Enable Input, active LOW. Sampled on the rising edge of
CLK. This signal must be asserted LOW to conduct a Byte Write.

Clock Input. Used to capture all synchronous inputs to the device. Also
used to increment the burst counter when ADV
a burst operation.

Chip Enable 1 Input, active LOW . Sampled on the rising edge of CLK.
Used in conjunction with CE

is ignored if CE1 is HIGH. CE1 is sampled only when a new

ADSP

and CE3 to select/deselect the device.

2

external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.

Used in conjunction with

is sampled only when a new external address is loaded.

CE

2

CE

and

1

Chip Enable 3 Input, active LOW . Sampled on the rising edge of CLK.
Used in conjunction with CE
device.CE
is sampled only when a new external address is loaded.

is assumed active throughout this document for BGA. CE3

3

and CE2 to select/deselect the

1

Output Enable, asynchronous input, active LOW. Controls the
direction of the I/O pins. When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE

is masked during the first clock of a Read cycle when emerging

from a deselected state.

Advance Input signal, sampled on the rising edge of CLK, active
LOW. When asserted, it automatically increments the address in a burst

cycle.

Address Strobe from Processor, sampled on the rising edge of
CLK, active LOW. When asserted LOW, A is captured in the address

registers. A

are both asserted, only ADSP is recognized. ASDP is ignored

ADSC
when CE

are also loaded into the burst counter. When

[1:0]

is deasserted HIGH.

1

Address Strobe from Controller, sampled on the rising edge of
CLK, active LOW. When asserted LOW, A is captured in the address

registers. A
ADSC

are both asserted, only ADSP is recognized.

are also loaded into the burst counter. When ADSP and

[1:0]

ZZ “sleep” Input, active HIGH. This input, when High places the
device in a non-time-critical “sleep” condition with data integrity
preserved. For normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data
register that is triggered by the rising edge of CLK. As outputs, they
deliver the data contained in the memory location specified by “A”
during the previous clock rise of the Read cycle. The direction of the
pins is controlled by OE

. When OE is asserted LOW, the pins behave

as outputs. When HIGH, DQ are placed in a tri-state condi ti on.

CY7C1364C

or ADSC is active LOW,

feed the 2-bit counter.

[1:0]

and BWE).

is asserted LOW , during

to select/deselect the device.

CE

3

ADSP

and

Document #: 38-05689 Rev. *E Page 4 of 18

[+] Feedback

Pin Definitions (continued)

Name TQFP I/O Description

V

DDQ

V

SSQ

MODE 31 Input-

NC 1, 14, 16, 30, 38, 39, 42,

4, 1 1, 20, 27, 54, 61, 70, 77 I/O Power

Power supply for the I/O circuitry.

Supply

5, 10, 21, 26, 55, 60, 71, 76 I/O Ground Ground for the I/O circuitry.

Selects Burst Order. When tied to GND selects linear burst sequence.

Static

When tied to V
This is a strap pin and should remain static during device operation.

or left floating selects interleaved burst sequence.

DD

Mode pin has an internal pull-up.
No Connects. Not internally connected to the die

51, 66, 80

CY7C1364C

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.

The CY7C1364C supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
Enable (GW
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
is HIGH.

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP
(2) CE

1

signals (GW
if CE

is HIGH. The address presented to the address inputs

1

(A) is stored into the address advancement logic and the
address register while being presented to the memory array.
The corresponding data is allowed to propagate to the input of
the output registers. At the rising edge of the next clock the
data is allowed to propagate through the output re gister and
onto the data bus within t
exception occurs when the SRAM is emerging from a
deselected state to a selected state, its outputs are always
tri-stated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE
Consecutive single Read cycles are supported. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP

or ADSC signals, its output will tri-state immediately.

) or the Controller Address Strobe (ADSC).

) inputs. A Global Write

) overrides all Byte Write inputs and writes data to

[A:D]

) provide for easy bank

is ignored if CE

or ADSC is asserted LOW,

, CE2, CE3 are all asserted active, and (3) the Write

, BWE) are all deasserted HIGH. ADSP is ignored

if OE is active LOW. The only

CO

signal.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
(2) CE

, CE2, CE3 are all asserted active. The address

1

presented to A is loaded into the address register and the

is asserted LOW, and

address advancement logic while being delivered to the RAM
array. The Write signals (GW
inputs are ignored during this first cycle.

ADSP

-triggered Write accesses require two clock cycles to

complete. If GW

is asserted LOW on the second clock rise, the

, BWE, and BW

[A:D]

data presented to the DQ inputs is written into the corre­sponding address location in the memory array. If GW is HIGH ,
then the Write operation is controlled by BWE

and BW
signals. The CY7C1364C provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE
Write ( BW
bytes. Bytes not selected during a Byte Write operation will

) input, will selectively write to only the desired

[A:D]

) with the selected Byte

remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.

Because the CY7C1364C is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQ are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE

1

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi­tions are satisfied: (1) ADSC
deasserted HIGH, (3) CE
and (4) the appropriate combination of the Write inputs (GW

, and BW

BWE
the desired byte(s). ADSC

) are asserted active to conduct a Write to

[A:D]

is asserted LOW, (2) ADSP is

, CE2, CE3 are all asserted active,

1

-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the m emory array .
The ADV

input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQ is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.

Because the CY7C1364C is a common I/O device, the Output
Enable (OE

) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE

) and ADV

[A:D]

.

,

.

Document #: 38-05689 Rev. *E Page 5 of 18

[+] Feedback

CY7C1364C

Burst Sequences

The CY7C1364C provides a two-bit wraparound counter, fed
by A
sequence. The interleaved burst sequence is designed specif­ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.

Asserting ADV
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.

, that implements either an interleaved or linear burst

[1:0]

LOW at clock rise will automatically increment

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to e ntering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW

.

, CE2, CE3, ADSP, and ADSC must

1

after the ZZ input

ZZREC

Interleaved Burst Address Table
(MODE = Floating or V

First

Address

A

[1:0]

Second

Address

A

[1:0]

DD

)

Third

Address

A

[1:0]

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A

[1:0]

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Second

Address

A

[1:0]

Third

Address

A

[1:0]

ZZ Mode Electrical Characteristics

Parameter Description T est Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Sleep mode standby current ZZ > VDD – 0.2V 50 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ Active to Sleep current This parameter is sampled 2t

CYC

CYC

ZZ Inactive to exit Sleep current This parameter is sampled 0 ns

Fourth

Address

A

[1:0]

Fourth

Address

A

[1:0]

ns
ns
ns

Document #: 38-05689 Rev. *E Page 6 of 18

[+] Feedback

CY7C1364C

Truth Table

[3, 4, 5, 6, 7, 8]

Address

Next Cycle

Used ZZ CE

CE

3

CE

2

ADSP ADSC ADV OE DQ Write

1

Unselected None L X X H X L X X Tri-State X
Unselected None L H X L L X X X Tri-State X
Unselected None L X L L L X X X Tri-State X
Unselected None L H X L H L X X Tri-State X
Unselected None L X L L H L X X Tri-State X
Begin Read External L L H L L X X X Tri-State X
Begin Read External L L H L H L X X Tri-State Read
Continue Read Next L X X X H H L H Tri-State Read
Continue Read Next L X X X H H L L DQ Read
Continue Read Next L X X H X H L H Tri-State Read
Continue Read Next L X X H X H L L DQ Read
Suspend Read Current L X X X H H H H Tri-State Read
Suspend Read Current L X X X H H H L DQ Read
Suspend Read Current L X X H X H H H Tri-State Read
Suspend Read Current L X X H X H H L DQ Read
Begin Write Current L X X X H H H X Tri-St ate Write
Begin Write Current L X X H X H H X Tri-St ate Write
Begin Write External L L H L H H X X Tri-State Write
Continue Write Next L X X X H H H X Tri-State Write
Continue Write Next L X X H X H H X Tri-State Write
Suspend Write Current L X X X H H H X Tri-State Write
Suspend Write Current L X X H X H H X Tri-State Write
ZZ “Sleep” None H X X X X X X X Tri-State X

Notes:

3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

4. WRITE

5. The DQ pins are controlled by the current cycle and the

6. CE

7. The SRAM always initiates a Read cycle when ADSP

8. OE

= L when any one or more Byte Write Enable signals (BWA,BWB,BWC,BW

(BW

,BWB,BWC,BW

A

, CE2, and CE3 are available only in the TQFP package.

1

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the Write cycle.

is asynchronous and is not sampled with the clock rise. It is masked internally during W rite cycles. During a Read cycle al l dat a bit s are tri-st ate when OE is

inactive or when the device is deselected, and all data bits behave as output when OE

),

BWE

D

.

,

=

GW

H

signal. OE is asynchronous and is not sampled with the clock.

OE

is asserted, regardless of the state of GW , BWE, or BW

)

D

= L or GW = L. WRITE = H when all Byte Write Enable signals

and BWE

. Writes may occur only on subsequent clocks

[A:D]

is active (LOW).

Document #: 38-05689 Rev. *E Page 7 of 18

[+] Feedback

CY7C1364C

Truth Table for Read/Write

Function GW BWE BW

[3, 4]

D

BW

C

BW

B

BW

A

Read HHXXXX
Read HLHHHH
Write Byte A – DQ
Write Byte B – DQ

A

B

HLHHHL

HLHHLH
Write Bytes B, A H L H H L L
Write Byte C – DQ

C

HLHLHH
Write Bytes C, A H L H L H L
Write Bytes C, B H L H L L H
Write Bytes C, B, A H L H L L L
Write Byte D – DQ

D

HLLHHH
Write Bytes D, A H L L H H L
Write Bytes D, B H L L H L H
Write Bytes D, B, A H L L H L L
Write Bytes D, C H L L L H H
Write Bytes D, C, A H L L L H L
Write Bytes D, C, B HLLLLH
Write All Bytes HLLLLL
Write All Bytes LXXXXX

Document #: 38-05689 Rev. *E Page 8 of 18

[+] Feedback

CY7C1364C

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied ............................................–55°C to +125°C

Supply Voltage on V
Supply Voltage on V

Relative to GND........–0.5V to +4.6V

DD

Relative to GND...... –0.5V to +V

DDQ

DD

DC Voltage Applied to Outputs

in tri-state.................................... ... ......–0.5V to V

DDQ

+ 0.5V

Electrical Characteristics Over the Operating Range

DC Input Voltage................................... –0.5V to V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage .......................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current..................................................... >200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V –
Industrial –40°C to +85°C

[9, 10]

Ambient

Temperature V

5%/+10%

DD

+ 0.5V

DD

V

DDQ

2.5V – 5% to
V

DD

Parameter Description Test Conditions Min. Max. Unit

V
V

DD
DDQ

Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage for 3.3 V I/O 3.135 V

DD

for 2.5V I/O 2.375 2.625 V

V

OH

V

OL

V

IH

V

IL

Output HIGH Voltage for 3.3 V I/O, I

for 2.5V I/O, I

Output LOW Voltage for 3.3 V I/O, I

for 2.5V I/O, I

Input HIGH Voltage

[9]

for 3.3 V I/O 2.0 VDD + 0.3V V
for 2.5V I/O 1.7 V

Input LOW Voltage

[9]

for 3.3 V I/O –0.3 0.8 V

= –4.0 mA 2.4 V

OH

= –1.0 mA 2.0 V

OH

= 8.0 mA 0.4 V

OL

= 1.0 mA 0.4 V

OL

+ 0.3V V

DD

for 2.5V I/O –0.3 0.7 V

I

X

I

OZ

I

DD

Input Leakage Current

GND ≤ VI ≤ V

except ZZ and MODE
Input Current of MODE Input = V

Input = V

Input Current of ZZ Input = V

Input = V

SS
DD
SS
DD

Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply

Current

V

DD

f = f

= Max., I

= 1/t

MAX

DDQ

–5 5 µA

–30 µA

–5 µA

Output Disabled –5 5 µA

DDQ,

OUT

CYC

= 0 mA,

4-ns cycle, 250 MHz 250 mA

5-ns cycle, 200 MHz 220 mA

5 µA

30 µA

6-ns cycle, 166 MHz 180 mA

I

SB1

I

SB2

I

SB3

I

SB4

Notes:

9. Overshoot: V

10.T

Power-up

Automatic CE
Power-down
Current—TTL Inputs

Automatic CE
Power-down
Current—CMOS Inputs

Automatic CE
Power-down
Current—CMOS Inputs

Automatic CE
Power-down
Current—TTL Inputs

(AC) < VDD +1.5V (Pulse width less than t

IH

: Assumes a linear ramp from 0Vv to VDD(min.) within 200 ms. During this time VIH < VDD and V

V

= Max., Device Deselected,

DD

≥ VIH or VIN ≤ VIL,

V

IN

f = f
V

V
f = 0

V
or V
f = f

V
V
f = 0

= 1/t

MAX

= Max., Device Deselected,

DD

≤ 0.3V or VIN > V

IN

= Max., Device Deselected,

DD

IN
MAX

= Max., Device Deselected,

DD

≥ VIH or VIN ≤ VIL,

IN

CYC

DDQ

≤ 0.3V or VIN > V

= 1/t

CYC

/2), undershoot: VIL(AC) > –2V (Pulse width less than t

CYC

– 0.3V,

DDQ

– 0.3V ,

4-ns cycle, 250 MHz 130 mA
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz 110
All speeds 40 mA

4-ns cycle, 250 MHz 120 mA
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
All speeds 40 mA

DDQ

< VDD.

CYC

120

110

100

/2).

V

Document #: 38-05689 Rev. *E Page 9 of 18

[+] Feedback

CY7C1364C

Capacitance

[11]

100 TQFP

Parameter Description Test Conditions

C

Input Capacitance TA = 25°C, f = 1 MHz,

IN

C

CLK

C

I/O

Thermal Resistance

Clock Input Capacitance 5 pF
Input/Output Capacitance 5 pF

[11]

V

V

DD

DDQ

= 3.3V

= 2.5V

Max. Unit

5pF

Parameter Description Test Conditions 100 TQFP Package Unit

Θ

JA

Θ

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

Test conditions fo llow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51

29.41 °C/W

6.13 °C/W

AC Test Loads and Waveforms

3.3V I/O Test Load

OUTPUT

Z

0

2.5V I/O Test Load

OUTPUT

Z

0

3.3V

= 50Ω

R

VT= 1.5V

(a) (b)

= 50Ω

= 1.25V

V

T

R

= 50Ω

L

= 50Ω

L

OUTPUT

INCLUDING

JIG AND

SCOPE

2.5V

OUTPUT

INCLUDING

JIG AND

SCOPE

(a) (b)

5pF

5pF

R = 317Ω

R = 351Ω

R = 1667Ω

R =1538Ω

V

GND

V

GND

DDQ

DDQ

≤ 1 ns

≤ 1 ns

ALL INPUT PULSES

10%

10%

90%

ALL INPUT PULSES

90%

90%

(c)

90%

(c)

10%

≤ 1 ns

10%

≤ 1 ns

Note:

11.Tested initially and after any design or process change that may affect the se parameters

Document #: 38-05689 Rev. *E Page 10 of 18

[+] Feedback

CY7C1364C

Switching Characteristics Over the Operating Range

Parameter Description

t

POWER

Clock

t

CYC

t

CH

t

CL

Output Times

t

CO

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Set-up Times

t

AS

t

ADS

t

ADVS

t

WES

t

DS

t

CES

Hold Times

t

AH

t

ADH

t

ADVH

t

WEH

t

DH

t

CEH

VDD(Typical) to the First Access

Clock Cycle Time 4.0 5.0 6.0 ns
Clock HIGH 1.8 2.0 2.4 ns
Clock LOW 1.8 2.0 2.4 ns

Data Output Valid after CLK Rise 2.8 3.0 3.5 ns
Data Output Hold after CLK Rise 1.25 1.25 1.25 ns
Clock to Low-Z
Clock to High-Z

[15, 16, 17]

[15, 16, 17]

OE LOW to Output Valid 2.8 3.0 3.5 ns
OE LOW to Output Low-Z
OE HIGH to Output High-Z

Address Set-up before CLK Rise 1.25 1.5 1.5 ns
ADSC, ADSP Set-up before CLK Rise 1.25 1.5 1.5 ns
ADV Set-up before CLK Rise
GW, BWE, BW

Set-up before CLK Rise 1.25 1.5 1.5 ns

[A:D]

Data Input Set-up before CLK Rise 1.25 1.5 1.5 ns
Chip Enable Set-up before CLK Rise 1.25 1.5 1.5 ns

Address Hold after CLK Rise 0.4 0.5 0.5 ns
ADSP, ADSC Hold after CLK Rise 0.4 0.5 0.5 ns
ADV Hold after CLK Rise 0.4 0.5 0.5 ns
GW, BWE, BW

Hold after CLK Rise 0.4 0.5 0.5 ns

[A:D]

Data Input Hold after CLK Rise 0.4 0.5 0.5 ns
Chip Enable Hold after CLK Rise 0.4 0.5 0.5 ns

[14]

[15, 16, 17]

[15, 16, 17]

[12,13]

–250 –200 –166

UnitMin. Max. Min. Max. Min. Max.

1 11ms

1.25 1.25 1.25 ns

1.25 2.8 1.25 3.0 1.25 3.5 ns

0 0 0 ns

2.8 3.0 3.5 ns

1.25 1.5 1.5 ns

Notes:

12.Timing reference level is 1.5V when V

13.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

14.This part has a voltage regulator internally; t
can be initiated.

, t

15.t

CHZ

16.At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.

17.This parameter is sampled and not 100% tested.

CLZ,tOELZ

, and t

are specified with AC test conditions shown in p art (b) of A C Test Loads. Transition is measured ± 200 mV from ste ady-state voltage.

OEHZ

= 3.3V and is 1.25V when V

DDQ

POWER

OEHZ

Document #: 38-05689 Rev. *E Page 11 of 18

= 2.5V.

DDQ

is the time that the power needs to be supplied above VDD minimum initially before a Read or Write operation

is less than t

OELZ

and t

is less than t

CHZ

to eliminate bus contention between SRAMs when sharing the same

CLZ

[+] Feedback

Switching Waveforms

D

Read Cycle Timing

[18]

t

CYC

CY7C1364C

CLK

ADSP

ADSC

ADDRESS

GW, BWE,

BW[A:D]

CE

ADV

t

ADS

t

t

AS

CES

A1

t

CH

t

ADH

t

AH

t

CEH

t

CL

t

WES

t

t

ADH

ADS

A2 A3

t

WEH

t

t

ADVH

ADVS

Burst continued with
new base address

Deselect
cycle

ADV
suspends
burst.

OE

ata Out (Q)

Note:

18.On this diagram, when CE

t

t

t

CLZ

High-Z

is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

t

CO

OEHZ

Q(A1)

OEV

t

OELZ

t

CO

t

DOH

Q(A2) Q(A2 + 1) Q(A2 + 2)

t

CHZ

Q(A2) Q(A2 + 1)Q(A2 + 3)

Burst wraps around

Document #: 38-05689 Rev. *E Page 12 of 18

[+] Feedback

Switching Waveforms (continued)

D

Write Cycle Timing

[18,19]

t

CYC

CY7C1364C

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A :D]

GW

CE

t

t

CL

CH

t

t

ADH

ADS

t

ADS

t

t

AH

AS

A1

Byte write signals are
ignored for first cycle when
ADSP initiates burst

t

t

CEH

CES

t

ADH

ADSC extends burst

A2 A3

t

t

WEH

WES

t

ADS

t

ADH

t

WES

t

ADVS

t

WEH

t

ADVH

ADV

OE

Data In (D)

ata Out (Q)

Note:

19.

Full width Write can be initiated by either GW

High-Z

BURST READ BURST WRITE

t

OEHZ

t

t

DH

DS

D(A1)

Single WRITE

D(A2) D(A2 + 1) D(A2 + 1)

DON’T CARE

LOW; or by GW HIGH, BWE LOW and BW

ADV suspends burst

UNDEFINED

[A:D]

D(A2 + 2)

LOW.

D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

Extended BURST WRITE

Document #: 38-05689 Rev. *E Page 13 of 18

[+] Feedback

Switching Waveforms (continued)

D

Read/Write Cycle Timing

[18,20, 21]

t

CYC

CY7C1364C

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A:D]

CE

ADV

OE

Data In (D)

t

t

CL

CH

t

t

ADH

ADS

t

t

AH

AS

High-Z

t

CES

A2

t

CEH

t

CO

t

CLZ

t

OEHZ

t

WES

t

DS

A3

t

D(A3)

A1

A4 A5 A6

t

WEH

DH

t

OELZ

D(A5) D(A6)

ata Out (Q)

Notes:

20.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP
is HIGH.

21.GW

High-Z

Document #: 38-05689 Rev. *E Page 14 of 18

Q(A2)Q(A1)

Single WRITE

DON’T CARE UNDEFINED

Q(A4) Q(A4+1) Q(A4+2)

BURST READBack-to-Back READs

Q(A4+3)

Back-to-Back

WRITEs

, ADSC, or ADV cycle is performed.

[+] Feedback

Switching Waveforms (continued)

A

CLK

[22, 23]

t

ZZ

ZZ Mode Timing

CY7C1364C

t

ZZREC

I

SUPPLY

LL INPUTS

ZZ

t

ZZI

I

DDZZ

t

RZZI

DESELECT or READ Only

(except ZZ)

Outputs (Q)

High-Z

DON’T CARE

Notes:

22.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

23.DQs are in High-Z when exiting ZZ sleep mode.

Document #: 38-05689 Rev. *E Page 15 of 18

[+] Feedback

CY7C1364C

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

Speed

(MHz) Ordering Code

166 CY7C1364C-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1364C-166AJXC 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1364C-166AXI 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1364C-166AJXI 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

200 CY7C1364C-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1364C-200AJXC 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1364C-200AXI 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1364C-200AJXI 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

250 CY7C1364C-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1364C-250AJXC 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1364C-250AXI 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1364C-250AJXI 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

visit www.cypress.com for actual products offered.

Package
Diagram Part and Package Type

(3 Chip Enable)

(2 Chip Enable)

(3 Chip Enable)

(2 Chip Enable)

(3 Chip Enable)

(2 Chip Enable)

(3 Chip Enable)

(2 Chip Enable)

(3 Chip Enable)

(2 Chip Enable)

(3 Chip Enable)

(2 Chip Enable)

Operating

Range

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

Document #: 38-05689 Rev. *E Page 16 of 18

[+] Feedback

CY7C1364C

Package Diagram

100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)

16.00±0.20

14.00±0.10

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

20.00±0.10

22.00±0.20

100

1

30

31 50

0° MIN.

R 0.08 MIN.

0.20 MAX.

0.20 MIN.

A

DETAIL

81

80

0.30±0.08

0.65
TYP.

51

STAND-OFF

0.05 MIN.

0.15 MAX.

12°±1°

(8X)

SEATING PLANE

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

51-85050-*B

i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark
of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.

1.40±0.05

SEE DETAIL

0.20 MAX.

1.60 MAX.

0.10

A

Document #: 38-05689 Rev. *E Page 17 of 18

© Cypress Semiconductor Corporation, 2006. The information contained herein i s su bj ect to ch ange without notice. Cypress Semiconductor Corpo ration assu mes no resp onsib ility for th e us e
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypres s does not auth orize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

[+] Feedback

CY7C1364C

Document History Page

Document Title: CY7C1364C 9-Mbit (256K x 32) Pipelined Sync SRAM
Document Number: 38-05689

REV. ECN NO. Issue Date

** 286269 See ECN PCI New data sheet

*A 320834 See ECN PCI Changed 225 MHz into 250 MHz

*B 377095 See ECN PCI Change d I

*C 408725 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from

*D 429278 See ECN NXR Added 2.5 V I/O option

*E 501828 See ECN VKN Added the Maximum Rating for Supply Voltage on V

Orig. of
Change Description of Change

Changed Θ
respectively
Modified V
Added Industrial Operating Range

and Θ

JA

OL, VOH

for TQFP from 25 and 9 °C/W to 29.41 and 6.13 °C/W

JC

test conditions

Changed Snooze to Sleep in the ZZ Mode Electrical Characteristics
Shaded 250 MHz speed bin in the AC/DC table and Selection Guide
Added AJXC package in the Ordering Information
Updated Ordering Information Table

from 30 to 40 mA

Modified test condition in note# 9 from V

SB2

IH

< V

DD to VIH

“3901 North First Street” to “198 Champion Court”
Changed three-state to tri-state
Converted from Preliminary to Final
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated the ordering information

Included 2 Chip Enable Pinout
Updated Ordering Information Table

Updated the Ordering Information table.

< V

DD

Relative to GND

DDQ

Document #: 38-05689 Rev. *E Page 18 of 18

[+] Feedback