A
A
B
CY7C1360C
CY7C1362C
9-Mbit (256K x 36/512K x 18) Pipelined SRAM
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 166 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply (VDD)
• 2.5V/3.3V I/O operation (V
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Available in lead-free 100-Pin TQFP package, lead-free
and non lead-free 119-Ball BGA package and 165-Ball
FBGA package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan
DDQ
)
®
Functional Description
The CY7C1360C/CY7C1362C SRAM integrates 256K x 36
and 512K x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE
Enables (CE
ADV
and
(GW
). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW cause
The CY7C1360C/CY7C1362C operates from a +3.3V core
and CE
2
), Write Enables (BWX, and BWE), and Global Write
3
s all bytes to be written.
[1]
), depth-expansion Chip
[2]
), Burst Control inputs (ADSC, ADSP,
1
) are active. Subsequent
) or
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram – CY7C1362C (512K x 18)
0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
BW
BWE
GW
CE
CE2
CE3
OE
B
A
1
ADDRESS
REGISTER
DQB,DQP
B
WRITE REGISTER
DQA,DQP
A
WRITE REGISTER
ENABLE
REGISTER
A[1:0]
2
Q1
BURST
COUNTER AND
LOGIC
CLR
Q0
PIPELINED
ENABLE
DQB,DQP
B
WRITE DRIVER
DQA,DQP
A
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP
DQP
INPUT
REGISTERS
ZZ
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
is for A version of TQFP (3 Chip Enable option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.
2. CE
3
SLEEP
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05540 Rev . *H Revised September 14, 2006
[+] Feedback
.
A
Logic Block Diagram – CY7C1360C (256K x 36)
0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
BW
BW
BW
BWE
GW
CE
CE
CE
OE
D
C
B
A
1
2
3
ADDRESS
REGISTER
D ,
DQPD
DQ
BYTE
WRITE REGISTER
C ,
DQPC
DQ
BYTE
WRITE REGISTER
B ,
DQPB
DQ
BYTE
WRITE REGISTER
DQ
A ,
DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
2
BURST
COUNTER
AND
CLR
LOGIC
PIPELINED
ENABLE
A
[1:0]
Q1
Q0
D
,DQP
D
DQ
BYTE
WRITE DRIVER
C ,
DQPC
DQ
BYTE
WRITE DRIVER
B ,
DQPB
DQ
BYTE
WRITE DRIVER
DQ
A ,
DQPA
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
CY7C1360C
CY7C1362C
OUTPUT
BUFFERS
E
INPUT
REGISTERS
DQs
DQP
DQP
DQP
DQP
A
B
C
D
ZZ
SLEEP
CONTROL
Selection Guide
250 MHz 200 MHz 166 MHz Unit
Maximum Access Time 2.8 3.0 3.5 ns
Maximum Operating Current 250 220 180 mA
Maximum CMOS Standby Current 40 40 40 mA
Document #: 38-05540 Rev. *H Page 2 of 31
[+] Feedback
Pin Configurations
100-Pin TQFP Pinout (3 Chip Enables) (A Version)
CY7C1360C
CY7C1362C
DQP
DQC
DQc
V
DDQ
V
SSQ
DQC
DQC
DQC
DQC
V
SSQ
V
DDQ
DQC
DQC
NC
V
NC
V
DQD
DQD
V
DDQ
V
SSQ
DQD
DQD
DQD
DQD
V
SSQ
V
DDQ
DQD
DQD
DQPD
1CE2
A
A
BWD
BWC
CE
100999897969594939291908988878685848382
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DD
15
16
SS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
BWB
CY7C1360C
(256K X 36)
31323334353637383940414243444546474849
AAA
1A0
A
A
MODE
BWA
NC/72M
CE3VDDV
SS
V
NC/36M
SS
CLKGWBWEOEADSC
A
DD
V
NC/18M
ADSP
AAAAA
A
A
ADV
81
DQPB
80
DQB
79
DQB
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
DQB
DQB
DQB
DQB
V
SSQ
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SSQ
DQA
DQA
DQA
DQA
V
SSQ
V
DDQ
DQA
DQA
DQPA
A
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ
DQB
V
SSQ
V
DDQ
DQB
DQB
NC
V
NC
V
DQB
DQB
V
DDQ
V
SSQ
DQB
DQB
DQPB
NC
V
SSQ
V
DDQ
NC
NC
NC
B
DD
SS
50
A
A
1CE2
A
A
NCNCBWBBWA
CE
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1362C
(512K x 18)
CE3VDDV
SS
CLKGWBWEOEADSC
ADSP
31323334353637383940414243444546474849
AAA
MODE
1A0
A
A
NC/72M
NC/36M
A
DD
V
AAAAA
SS
V
NC/18M
ADV
A
A
81
A
80
NC
79
NC
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
NC
DQP
DQA
DQA
V
SSQ
V
DDQ
DQA
DQA
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SSQ
DQA
DQA
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
A
A
50
A
A
Document #: 38-05540 Rev. *H Page 3 of 31
[+] Feedback
Pin Configurations (continued)
100-Pin TQFP Pinout (2 Chip Enables) (AJ Version)
CY7C1360C
CY7C1362C
DQPC
DQC
DQC
V
DDQ
V
SSQ
DQC
DQC
DQC
DQC
V
SSQ
V
DDQ
DQC
DQC
NC
V
NC
V
DQD
DQD
V
DDQ
V
SSQ
DQD
DQD
DQD
DQD
V
SSQ
V
DDQ
DQD
DQD
DQPD
1CE2
A
A
BWD
BWC
CE
BWB
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DD
15
16
SS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1360C
(256K X 36)
31323334353637383940414243444546474849
AAA
1A0
A
A
MODE
SS
BWA
A
VDDV
CLKGWBWEOEADSC
ADSP
ADV
A
A
81
DQPB
80
DQB
79
DQB
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
DQB
DQB
DQB
DQB
V
SSQ
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SSQ
DQA
DQA
DQA
DQA
V
SSQ
V
DDQ
DQA
DQA
DQPA
A
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ
DQB
V
SSQ
V
DDQ
DQB
DQB
NC
V
NC
V
DQB
DQB
V
DDQ
V
SSQ
DQB
DQB
DQPB
NC
V
SSQ
V
DDQ
NC
NC
NC
B
DD
SS
50
A
DD
V
NC
NC/18M
AAAAA
SS
V
NC/36M
NC/72M
A
1CE2
A
A
NCNCBWBBWA
CE
A
VDDV
SS
CLKGWBWEOEADSC
ADSP
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1362C
(512K x 18)
31323334353637383940414243444546474849
AAA
MODE
1A0
A
A
SS
V
NC/72M
NC/36M
DD
V
NC
NC/18M
AAAAA
A
A
ADV
81
A
80
NC
79
NC
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
NC
DQP
DQA
DQA
V
SSQ
V
DDQ
DQA
DQA
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SSQ
DQA
DQA
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
A
A
50
A
A
Document #: 38-05540 Rev. *H Page 4 of 31
[+] Feedback
Pin Configurations (continued)
119-Ball BGA Pinout (2 Chip Enables with JTAG)
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DDQ
NC/288M
NC/144M
DQ
DQ
V
DDQ
DQ
DQ
V
DDQ
DQ
DQ
V
DDQ
DQ
DQ
NC
NC
V
DDQ
CY7C1360C
CY7C1362C
CY7C1360C (256K x 36)
2345671
AA AA
CE
2
A
AA
C
D
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
BW
V
SS
V
SS
V
SS
MODE
DQP
C
DQ
C
C
C
D
D
D
D
DQ
DQ
DQ
V
DD
DQ
DQ
DQ
DQ
DQP
C
C
C
C
D
D
D
D
A
AAA
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
C
GW
DD
CLK
D
NC
BWE
A1
A0
V
DD
A
V
V
V
BW
V
NC
V
BW
V
V
V
NC
SS
SS
SS
B
SS
SS
A
SS
SS
SS
A
AA
DQP
DQ
DQ
DQ
DQ
V
DD
DQ
DQ
DQ
DQ
DQP
A
NC/36MNC/72M
TDOTCKTDITMS
NC
B
B
B
B
B
A
A
A
A
A
V
DDQ
NC/576M
NC/1G
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
NC
NC/72M
V
DDQ
CY7C1362C (512K x 18)
2
AA AA
CE
2
NCDQ
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
DQP
B
A
345671
ADSP
A
AA
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
ADSC
V
DD
NC
CE
1
OE
ADV
B
GW
DD
CLK
NC
BWE
A1
A0
V
DD
A NC/36M A
V
V
V
V
V
NC
V
BW
V
V
V
NC
TDOTCKTDITMS
A
A
AA
SS
SS
SS
SS
SS
SS
SS
SS
SS
DQP
A
NC
DQ
A
NC
DQ
A
V
DD
NC
DQ
A
A
NC
DQ
A
NC
A
AA
NC
V
DDQ
NC/576M
NC/1G
NC
DQ
A
V
DDQ
DQ
A
NC
V
DDQ
DQ
A
NC
V
DDQ
NC
DQ
A
NC
ZZ
V
DDQ
Document #: 38-05540 Rev. *H Page 5 of 31
[+] Feedback
Pin Configurations (continued)
165-Ball FBGA Pinout (3 Chip Enable with JTAG)
2345671
NC/288M
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/144M
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
NC
MODE
A
A
NC
DQ
DQ
DQ
DQ
V
SS
DQ
DQ
DQ
DQ
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
C
C
C
C
V
V
V
DDQ
DDQ
DDQ
DDQ
NC
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
D
D
D
D
A
A
CY7C1360C
CY7C1362C
CY7C1360C (256K x 36)
891011
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
C
BW
D
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
B
A
CE
3
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/18M
A1
A0
BWE
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
ADSC
ADV
OE ADSP
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
V
V
V
V
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
A
NC/1G DQP
DQ
B
DQ
B
DQ
B
DQ
B
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
NC
NC/576M
B
DQ
B
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
AA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CY7C1362C (512K x 18)
2345671
NC/288M
NC/144M
NC
NC
NC V
NC
NC
NC
DQ
B
DQ
B
DQ
B
DQ
B
DQP
B
NC
MODE
A
A
NC
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
NC
NC
NC
NC
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
BW
1
B
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
A
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
A
CE
3
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/18M
A1
BWE
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
891011
ADSC
ADV
OE ADSP
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
V
V
V
V
V
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
A
NC/1G DQP
NC
NC
NC
NC
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
A
NC/576M
DQ
DQ
DQ
DQ
ZZ
NCV
NC
NC
NC
NC
A
AA
A
A
A
A
A
Document #: 38-05540 Rev. *H Page 6 of 31
[+] Feedback
Pin Definitions
Name I/O Description
A0, A1, A Input-
Synchronous
BW
, BW
A
BWC, BW
B
D
Input-
Synchronous
GW Input-
Synchronous
BWE
Input-
Synchronous
CLK Input-
Clock
CE
CE
CE
OE
1
2
[2]
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
ADV
Input-
Synchronous
ADSP Input-
Synchronous
ADSC
Input-
Synchronous
ZZ Input-
Asynchronous
DQs, DQP
V
DD
V
SS
V
SSQ
V
DDQ
X
I/O-
Synchronous
Power Supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
I/O Ground Ground for the I/O circuitry.
I/O Power Supply Power supply for the I/O circuitry.
MODE Input-
Static
TDO JTAG serial
output
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK if ADSP
are fed to the two-bit counter.
or ADSC is active LOW, and CE1, CE2, and CE
.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the
SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global Write is conducted (ALL bytes are written, regardless of the values on BW
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a Byte Write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
sampled only when a new external address is loaded.
and CE
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
address is loaded.
and CE
1
is asserted LOW, during a burst operation.
[2]
to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is
3
[2]
to select/deselect the device. CE2 is sampled only when a new external
3
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
connected for BGA. Where referenced, CE
BGA. CE
and CE2 to select/deselect the device. Not available for AJ package version. Not
1
is sampled only when a new external address is loaded.
3
3
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW . When
asserted LOW, addresses presented to the device are captured in the address registers. A
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP
A
0
is recognized. ASDP
is ignored when CE1 is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
A
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP
0
is recognized.
ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE
When HIGH, DQs and DQP
are placed in a tri-state condition.
X
. When OE is asserted LOW, the pins behave as outputs.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
left floating selects interleaved burst sequence. This is a strap pin and should remain static
during device operation. Mode pin has an internal pull-up.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP
packages.
CY7C1360C
CY7C1362C
[2]
are sampled active. A1, A0
3
and BWE).
X
[2]
is assumed active throughout this document for
DD
1
1
or
,
,
Document #: 38-05540 Rev. *H Page 7 of 31
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Pin Definitions (continued)
Name I/O Description
TDI JT AG serial input
Synchronous
TMS JT AG serial input
Synchronous
TCK JTAG-
Clock
NC – No Connects. Not internally connected to the die
NC (18,36,
– These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
72, 144, 288,
576, 1G)
Serial data-In to the JT AG circuit. Sampled on the rising edge of TCK. If the JT AG feature is
not being utilized, this pin can be disconnected or connected to VDD. This pin is not available
on TQFP packages.
Serial data-In to the JT AG circuit. Sampled on the rising edge of TCK. If the JT AG feature is
not being utilized, this pin can be disconnected or connected to V
on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be
connected to V
. This pin is not available on TQFP packages.
SS
288M, 576M, and 1G densities.
CY7C1360C
CY7C1362C
. This pin is not available
DD
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(250-MHz device).
The CY7C1360C/CY7C1362C supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP
) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE
) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW
) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
, CE2, CE
1
) provide for easy bank
selection and output tri-state control. ADSP
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP
CE
, CE2, CE
1
signals (GW
is HIGH. The address presented to the address inputs
if CE
1
(A) is stored into the address advancement logic and the
[2]
are all asserted active, and (3) the Write
3
, BWE) are all deasserted HIGH. ADSP is ignored
or ADSC is asserted LOW, (2)
address register while being presented to the memory array.
The corresponding data is allowed to propagate to the input of
the output registers. At the rising edge of the next clock the
data is allowed to propagate through the outp ut register and
onto the data bus within 2.8 ns (250-MHz device) if OE
active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its
outputs are always tri-stated during the first cycle of the
) is 2.8 ns
CO
[2]
) and an
3
is ignored if CE
is
access. After the first cycle of the access, the outputs are
controlled by the OE
signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by
the chip select and either ADSP
or ADSC signals, its output
will tri-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
(2) CE
, CE2, CE
1
presented to A is loaded into the address register and the
[2]
are all asserted active. The address
3
is asserted LOW, and
address advancement logic while being delivered to the
memory array. The Write signals (GW
ADV
inputs are ignored during this first cycle.
ADSP
-triggered Write accesses require two clock cycles to
complete. If GW
is asserted LOW on the second clock rise, the
, BWE, and BWX) and
data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HI GH,
then the Write operation is controlled by BWE
signals. The CY7C1360C/CY7C1362C provides Byte Write
capability that is described in the Write Cycle Descriptions
table. Asserting the Byte Write Enable input (BWE
selected Byte Write (BW
the desired bytes. Bytes not selected during a Byte Write
) input, will selectively write to only
X
operation will remain unaltered. A synchronous self-timed
Write mechanism has been provided to simplify the Write
operations.
Because the CY7C1360C/CY7C1362C is a common I/O
1
device, the Output Enable (OE
) must be deasserted HIGH
before presenting data to the DQs inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless
of the state of OE
.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC
deasserted HIGH, (3) CE
and (4) the appropriate combination of the Write inputs (GW
BWE
, and BWX) are asserted active to conduct a Write to the
desired byte(s). ADSC
is asserted LOW, (2) ADSP is
, CE2, CE
1
[2]
are all asserted active,
3
-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the m emory array .
The ADV
input is ignored during this cycle. If a global Write is
and BW
) with the
X
,
Document #: 38-05540 Rev. *H Page 8 of 31
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CY7C1360C
CY7C1362C
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because the CY7C1360C/CY7C1362C is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQs inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless
of the state of OE
.
Burst Sequences
The CY7C1360C/CY7C1362C provides a two-bit wraparound
counter, fed by A
or linear burst sequence. The interleaved burst sequence is
, A0, that implements either an interleaved
1
designed specifically to support Intel Pentium applications.
The linear burst sequence is designed to support processors
that follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Asserting ADV
LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
, CE2, CE
1
returns LOW.
[2]
, ADSP, and ADSC must
3
after the ZZ input
ZZREC
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
A1, A
0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
A1, A
)
DD
Third
Address
0
A1, A
0
Fourth
Address
A1, A
0
Linear Burst Address Table (MODE = GND)
First
Address
A1, A
0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
A1, A
0
Third
Address
A1, A
0
Fourth
Address
A1, A
0
ZZ Mode Electrical Characteristics
Parameter Description T est Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
Operation
Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State
Sleep Mode, Power Down None X X X H X X X X X X Tri-State
READ Cycle, Begin Burst External L H L L L X X X L L-H Q
READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
WRITE Cycle, Begin Burst External L H L L H L X L X L-H D
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE
5. The DQ pins are controlled by the current cycle and the OE
6. CE
7. The SRAM always initiates a read cycle when ADSP
8. OE
= L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
, CE2, and CE3 are available only in the TQFP package. BGA package has only two chip selects CE1 and CE2.
1
after the ADSP
don't care for the remainder of the Write cycle.
is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE
Sleep mode standby current ZZ > VDD – 0.2V 50 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ Active to sleep current This parameter is sampled 2t
CYC
CYC
ns
ns
ns
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
[3, 4, 5, 6, 7, 8]
Address
Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
signal. OE is asynchronous and is not sampled with the clock.
or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a
is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
is active (LOW).
Document #: 38-05540 Rev. *H Page 9 of 31
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CY7C1360C
CY7C1362C
Truth Table
[3, 4, 5, 6, 7, 8]
(continued)
Address
Operation
Used CE
CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
1
READ Cycle, Begin Burst External L H L L H L X H L L-H Q
READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
READ Cycle, Continue Burst Next X X X L H H L H L L-H Q
READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
READ Cycle, Continue Burst Next H X X L X H L H L L-H Q
READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D
WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D
READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q
READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q
READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D
WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D
Partial Truth Table for Read/Write
Function (CY7C1360C) GW BWE BW
[5, 9]
D
BW
C
BW
B
BW
A
Read HHXXXX
Read HLHHHH
Write Byte A – (DQ
Write Byte B – (DQ
and DQPA) HLHHHL
A
and DQPB)HLHHLH
B
Write Bytes B, A H L H H L L
Write Byte C – (DQ
and DQPC) HLHLHH
C
Write Bytes C, A H L H L H L
Write Bytes C, B H L H L L H
Write Bytes C, B, A H L H L L L
Write Byte D – (DQ
and DQPD) HLLHHH
D
Write Bytes D, A H L L H H L
Write Bytes D, B H L L H L H
Write Bytes D, B, A H L L H L L
Write Bytes D, C H L L L H H
Write Bytes D, C, A H L L L H L
Write Bytes D, C, B HLLLLH
Write All Bytes HLLLLL
Write All Bytes LXXXXX
Note:
9. Table only lists a partial listing of the byte write combinations. A ny combination of BW
is valid. Appropriate write will be done based on which byte write is active.
X
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CY7C1360C
CY7C1362C
Truth Table for Read/Write
Function (CY7C1362C)
[5, 9]
GW BWE BW
B
BW
Read H H X X
Read H L H H
Write Byte A – (DQ
Write Byte B – (DQ
and DQPA)HLHL
A
and DQPB)HLLH
B
Write Bytes B, A H L L L
Write All Bytes H L L L
Write All Bytes L X X X
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1360C/CY7C1362C incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
The CY7C1360C/CY7C1362C contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V
) to prevent clocking of the device. TDI and TMS are inter-
SS
nally pulled up and may be unconnected. They may alternately
be connected to V
left unconnected. Upon power-up, the device will come up in
through a pull-up resistor. TDO should be
DD
a reset state which will not interfere with the operation of the
device.TAP Controller State Diagram
The 0/1 next to each state represents the value of TMS at the
TEST-LOGIC
1
RESET
0
0
RUN-TEST/
IDLE
1
DR-SCAN
1 1
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
0 0
EXIT2-DR
UPDATE-DR
1 0
1
SELECT
0
0
0 0
1
1 1
0 0
0
1
1
SELECT
IR-SCAN
0
CAPTURE-IR
0
SHIFT-IR
1
EXIT1-IR
PAUSE-IR
1
EXIT2-IR
1
UPDATE-IR
1
0
1
0
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See Tap Controller Block Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
A
rising edge of TCK.
Document #: 38-05540 Rev. *H Page 11 of 31
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0
T
O
CY7C1360C
CY7C1362C
TAP Controller Block Diagram
Bypass Register
012
TDI TD
TCK
MS TAP CONTROLLER
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (V
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be pla ced betwee n the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V
SS
Selection
Circuitry
) when the BYPASS instruction is executed.
Instruction Register
Identification Register
Boundary Scan Register
S
Circuitr
012293031 ...
012..x ...
election
y
) for five
DD
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
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T
CY7C1360C
CY7C1362C
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the T AP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To g uarante e that the boun dary scan regi ster will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (t
captured correctly if there is no way in a design to stop (o r
and tCH). The SRAM clock input might not be
CS
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK
captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
Test Clock
(TCK)
t
t
TMSS
est Mode Select
(TMS)
Test Data-In
(TDI)
Test Data-Out
(TDO)
t
TDIS
t
t
TH
TL
TMSH
t
TDIH
DON’T CARE UNDEFINED
t
CYC
t
TDOX
t
TDOV
Document #: 38-05540 Rev. *H Page 13 of 31
[+] Feedback
T
F
T
F
CY7C1360C
CY7C1362C
TAP AC Switching Characteristics
Over the Operating Range
[10, 11]
Parameter Description Min. Max. Unit
Clock
t
TCYC
t
TF
t
TH
t
TL
TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH time 20 ns
TCK Clock LOW time 20 ns
Output Times
t
TDOV
t
TDOX
TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns
Set-up Times
t
TMSS
t
TDIS
t
CS
TMS Set-up to TCK Clock Rise 5 ns
TDI Set-up to TCK Clock Rise 5 ns
Capture Set-up to TCK Rise 5 ns
Hold Times
t
TMSH
t
TDIH
t
CH
3.3V TAP AC Test Conditions
Input pulse levels................................................ VSS to 3.3V
Input rise and fall times................................................ ...1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns
2.5V TAP AC Test Conditions
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage ............................1.25V
3.3V TAP AC Output Load Equivalent
1.5V
50Ω
DO
Z = 50Ω
O
20p
2.5V TAP AC Output Load Equivalent
1.25V
50Ω
DO
Z = 50Ω
O
20p
TAP DC Electrical Characteristics And Operating Conditions
R/tF
[12]
= 1 ns.
= 3.3V 2.4 V
DDQ
= 2.5V 2.0 V
DDQ
= 3.3V 2.9 V
DDQ
V
= 2.5V 2.1 V
DDQ
= 3.3V 0.4 V
DDQ
= 2.5V 0.4 V
DDQ
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)
Parameter Description Conditions Min. Max. Unit
V
OH1
V
OH2
V
OL1
Notes:
and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
10.t
CS
11.Test conditions are specified using the load in TAP AC test Conditions. t
12.All voltages referenced to V
Output HIGH Voltage IOH = –4.0 mA V
I
= –1.0 mA V
OH
Output HIGH Voltage IOH = –100 µA V
Output LOW Voltage IOL = 8.0 mA V
I
= 8.0 mA V
OL
(GND).
SS
Document #: 38-05540 Rev. *H Page 14 of 31
[+] Feedback
CY7C1360C
CY7C1362C
TAP DC Electrical Characteristics And Operating Conditions
DDQ
[12]
(continued)
DDQ
V
DDQ
DDQ
V
DDQ
DDQ
V
DDQ
= 3.3V 0.2 V
= 2.5V 0.2 V
= 3.3V 2.0 VDD + 0.3 V
= 2.5V 1.7 VDD + 0.3 V
= 3.3V –0.5 0.7 V
= 2.5V –0.3 0.7 V
–5 5 µA
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)
Parameter Description Conditions Min. Max. Unit
V
OL2
V
IH
V
IL
I
X
Output LOW Voltage IOL = 100 µA V
Input HIGH Volt age V
Input LOW Voltage V
Input Load Current GND < VIN < V
Identification Register Definitions
Instruction Field
(256KX36)
Revision Number (31:29) 000 000 Describes the version number
CY7C1360C
Device Depth (28:24)
[13]
01011 01011 Reserved for Internal Use
Device Width (23:18) 119-BGA 101000 101000 Defines memory type and architecture
Device Width (23:18) 165- FBGA 000000 000000 Defines memory type and architecture
Cypress Device ID (17:12) 1 00110 010110 D efines width and densi ty
Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor
ID Register Presence Indicator (0) 1 1 Indicates the presence of an ID register
CY7C1362C
(512KX18) Description
Scan Register Sizes
Register Name Bit Size (x36) Bit Size (x18)
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary Scan Order (119-ball BGA package) 71 71
Boundary Scan Order (165-ball FBGA package) 71 71
Identification Codes
Instruction Code Description
EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note:
13.Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05540 Rev. *H Page 15 of 31
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CY7C1360C
CY7C1362C
165-ball FBGA Boundary Scan Order
CY7C1360C (256K x 36) CY7C1362C (512K x 18)
Bit# ball ID
Name Bit# ball ID
1 B6 CLK 37 R6 A0 1 B6 CLK 37 R6 A0
Signal
2B7GW
3A7BWE
4B8OE
5A8ADSC
6B9ADSP
7A9ADV
38 P6 A1 2 B7 GW 38 P6 A1
39 R4 A 3 A7 BWE 39 R4 A
40 P4 A 4 B8 OE 40 P4 A
41 R3 A 5 A8 ADSC 41 R3 A
42 P3 A 6 B9 ADSP 42 P3 A
43 R1 MODE 7 A9 ADV 43 R1 MODE
8B10 A 44 N1 DQP
9A10 A 45 L2 DQ
10 C11 DQP
11 E10 DQ
12 F10 DQ
13 G10 DQ
14 D10 DQ
15 D11 DQ
16 E11 DQ
17 F11 DQ
18 G11 DQ
46 K2 DQ
B
47 J2 DQ
B
48 M2 DQ
B
49 M1 DQ
B
50 L1 DQ
B
51 K1 DQ
B
52 J1 DQ
B
53 Internal Internal 17 F11 DQ
B
54 G2 DQ
B
19 H11 ZZ 55 F2 DQ
20 J10 DQ
21 K10 DQ
22 L10 DQ
23 M10 DQ
24 J11 DQ
25 K11 DQ
26 L1 1 DQ
27 M11 DQ
28 N11 DQP
56 E2 DQ
A
57 D2 DQ
A
58 G1 DQ
A
59 F1 DQ
A
60 E1 DQ
A
61 D1 DQ
A
62 C1 DQP
A
63 B2 A 27 Internal Internal 63 B2 A
A
64 A2 A 28 Internal Internal 64 A2 A
A
29 R11 A 65 A3 CE
30 R10 A 66 B3 CE
31 P10 A 67 B4 BW
32 R9 A 68 A4 BW
33 P9 A 69 A5 BW
34 R8 A 70 B5 BW
35 P8 A 71 A6 CE
36 P11 A 36 P11 A
Signal
Name Bit# ball ID
D
D
D
D
D
D
D
D
D
C
C
C
C
C
C
C
C
C
1
2
D
C
B
A
3
8 B10 A 44 Internal Internal
9 A10 A 45 Internal Internal
10 A11 A 46 Internal Internal
11 Internal Internal 47 Internal Internal
12 Internal Internal 48 N1 DQP
13 Internal Internal 49 M1 DQ
14 C11 DQP
15 D11 DQ
16 E11 DQ
18 G11 DQ
19 H11 ZZ 55 F2 DQ
20 J10 DQ
21 K10 DQ
22 L10 DQ
23 M10 DQ
24 Internal Internal 60 Internal Internal
25 Internal Internal 61 Internal Internal
26 Internal Internal 62 Internal Internal
29 R11 A 65 A3 CE
30 R10 A 66 B3 CE
31 P10 A 67 Internal Internal
32 R9 A 68 Internal Internal
33 P9 A 69 A4 BW
34 R8 A 70 B5 BW
35 P8 A 71 A6 CE
Signal
Name Bit# ball ID
A
A
A
A
A
A
A
A
A
50 L1 DQ
51 K1 DQ
52 J1 DQ
53 Internal Internal
54 G2 DQ
56 E2 DQ
57 D2 DQ
58 Internal Internal
59 Internal Internal
Signal
Name
B
B
B
B
B
B
B
B
B
1
2
B
A
3
Document #: 38-05540 Rev. *H Page 16 of 31
[+] Feedback
CY7C1360C
CY7C1362C
119-ball BGA Boundary Scan Order
CY7C1360C (256K x 36) CY7C1362C (512K x 18)
Bit# ball ID
1
K4
2H4 GW
3M4BWE
4F4 OE
5B4ADSC
6A4ADSP
7G4ADV
Name Bit# ball ID
CLK 37 P4 A0 1
38 N4 A1 2 H4 GW 38 N4 A1
39 R6 A 3 M4 BWE 39 R6 A
40 T5 A 4 F4 OE 40 T5 A
41 T3 A 5 B4 ADSC 41 T3 A
42 R2 A 6 A4 ADSP 42 R2 A
43 R3 MODE 7 G4 ADV 43 R3 MODE
8C3 A 44 P2 DQP
9B3 A 45 P1 DQ
Signal
10 D6 DQP
11 H7 DQ
12 G6 DQ
13 E6 DQ
14 D7 DQ
15 E7 DQ
16 F6 DQ
17 G7 DQ
18 H6 DQ
46 L2 DQ
B
47 K1 DQ
B
48 N2 DQ
B
49 N1 DQ
B
50 M2 DQ
B
51 L1 DQ
B
52 K2 DQ
B
53 Internal Internal 17 G7 DQ
B
54 H1 DQ
B
19 T7 ZZ 55 G2 DQ
20 K7 DQ
21 L6 DQ
22 N6 DQ
23 P7 DQ
24 N7 DQ
25 M6 DQ
26 L7 DQ
27 K6 DQ
28 P6 DQP
56 E2 DQ
A
57 D1 DQ
A
58 H2 DQ
A
59 G1 DQ
A
60 F2 DQ
A
61 E1 DQ
A
62 D2 DQP
A
63 C2 A 27 Internal Internal 63 C2 A
A
64 A2 A 28 Internal Internal 64 A2 A
A
29 T4 A 65 E4 CE
30 A3 A 66 B2 CE
31 C5 A 67 L3 BWD 31 C5 A 67 Internal Internal
32 B5 A 68 G3 BW
33 A5 A 69 G5 BW
34 C6 A 70 L5 BW
35 A6 A 71 Internal Internal 35 A6 A 71 Internal Internal
36 B6 A 36 B6 A
Signal
Name Bit# ball ID
K4
D
D
D
D
D
D
D
D
D
C
C
C
C
C
C
C
C
C
1
2
C
B
A
8 C3 A 44 Internal Internal
9 B3 A 45 Internal Internal
10 T2 A 46 Internal Internal
1 1 Internal Internal 47 Internal Internal
12 Internal Internal 48 P2 DQP
13 Internal Internal 49 N1 DQ
14 D6 DQP
15 E7 DQ
16 F6 DQ
18 H6 DQ
19 T7 ZZ 55 G2 DQ
20 K7 DQ
21 L6 DQ
22 N6 DQ
23 P7 DQ
24 Internal Internal 60 Internal Internal
25 Internal Internal 61 Internal Internal
26 Internal Internal 62 Internal Internal
29 T6 A 65 E4 CE
30 A3 A 66 B2 CE
32 B5 A 68 Internal Internal
33 A5 A 69 G3 BW
34 C6 A 70 L5 BW
Signal
Signal
Name Bit# ball ID
CLK 37 P4 A0
A
A
A
A
A
A
A
A
A
50 M2 DQ
51 L1 DQ
52 K2 DQ
53 Internal Internal
54 H1 DQ
56 E2 DQ
57 D1 DQ
58 Internal Internal
59 Internal Internal
Name
B
B
B
B
B
B
B
B
B
1
2
B
A
Document #: 38-05540 Rev. *H Page 17 of 31
[+] Feedback
CY7C1360C
CY7C1362C
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
Supply Voltage on V
Relative to GND........–0.5V to +4.6V
DD
Relative to GND......–0.5V to +V
DDQ
DD
DC Voltage Applied to Outputs
in Tri-State..........................................–0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range
DC Input Voltage............................ ... ...–0.5V to VDD + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range
Commercial 0°C to +70°C 3.3V –
Industrial –40°C to +85°C
[14, 15]
Ambient
Temperature V
5%/+10%
DD
V
DDQ
2.5V – 5% to
V
DD
Parameter Description Test Conditions Min. Max. Unit
V
V
DD
DDQ
Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage for 3.3V I/O 3.135 V
DD
for 2.5V I/O 2.375 2.625 V
V
OH
V
OL
V
IH
Output HIGH Voltage for 3.3V I/O, I
for 2.5V I/O, I
Output LOW Voltage for 3.3V I/O, I
for 2.5V I/O, I
Input HIGH Voltage
[14]
for 3.3V I/O 2.0 VDD + 0.3V V
= –4.0 mA 2.4 V
OH
= –1.0 mA 2.0 V
OH
= 8.0 mA 0.4 V
OL
= 1.0 mA 0.4 V
OL
for 2.5V I/O 1.7 VDD + 0.3V V
V
IL
Input LOW Voltage
[14]
for 3.3V I/O –0.3 0.8 V
for 2.5V I/O –0.3 0.7 V
I
X
I
OZ
I
DD
Input Leakage Current
GND ≤ VI ≤ V
except ZZ and MODE
Input Current of MODE Input = V
Input = V
Input Current of ZZ Input = V
Input = V
SS
DD
SS
DD
Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply
Current
V
DD
f = f
= Max., I
= 1/t
MAX
DDQ
–5 5 µA
–30 µA
–5 µA
Output Disabled –5 5 µA
DDQ,
OUT
CYC
= 0 mA,
4-ns cycle, 250 MHz 250 mA
5-ns cycle, 200 MHz 220 mA
5 µA
30 µA
6-ns cycle, 166 MHz 180 mA
I
SB1
I
SB2
I
SB3
I
SB4
Notes:
14.Overshoot: V
15.T
: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and V
Power-up
Automatic CE
Power-down
Current—TTL Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—TTL Inputs
(AC) < VDD +1.5V (Pulse width less than t
IH
V
= Max, Device Deselected,
DD
V
≥ VIH or VIN ≤ V
IN
f = f
= 1/t
MAX
V
= Max, Device Deselected,
DD
V
≤ 0.3V or VIN > V
IN
f = 0
V
= Max, Device Deselected, or
DD
V
≤ 0.3V or VIN > V
IN
f = f
= 1/t
MAX
V
= Max, Device Deselected,
DD
V
≥ VIH or VIN ≤ VIL, f = 0
IN
/2), undershoot: VIL(AC) > –2V (Pulse width less than t
CYC
IL
CYC
DDQ
DDQ
CYC
– 0.3V,
– 0.3V
4-ns cycle, 250 MHz 130 mA
5-ns cycle, 200 MHz 120 mA
6-ns cycle, 166 MHz 110 mA
All speeds 40 mA
4-ns cycle, 250 MHz 120 mA
5-ns cycle, 200 MHz 110 mA
6-ns cycle, 166 MHz 100 mA
All Speeds 40 mA
/2).
CYC
< VDD.
DDQ
V
Document #: 38-05540 Rev. *H Page 18 of 31
[+] Feedback
CY7C1360C
CY7C1362C
Capacitance
[16]
Parameter Description Test Conditions
C
Input Capacitance TA = 25°C, f = 1 MHz,
IN
C
CLK
C
I/O
Clock Input Capacitance 5 5 5 pF
Input/Output Capacitance 5 7 7 pF
Thermal Resistance
[16]
V
V
DD
DDQ
= 3.3V
= 2.5V
Parameter Description Test Conditions
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51.
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
Z
0
2.5V I/O Test Load
OUTPUT
Z
0
3.3V
= 50Ω
R
VT= 1.5V
(a) (b)
= 50Ω
V
T
R
= 1.25V
= 50Ω
L
= 50Ω
L
OUTPUT
INCLUDING
JIG AND
SCOPE
2.5V
OUTPUT
INCLUDING
JIG AND
SCOPE
(a) (b)
5pF
5pF
R = 317Ω
R = 1667Ω
R = 351Ω
R =1538Ω
100 TQFP
Max.
119 BGA
Max.
165 FBGA
Max. Unit
555pF
100 TQFP
Package
119 BGA
Package
165 FBGA
Package Unit
29.41 34.1 16.8 °C/W
6.13 14.0 3 °C/W
V
DDQ
GND
≤ 1 ns
ALL INPUT PULSES
10%
90%
90%
10%
≤ 1 ns
(c)
V
GND
DDQ
≤ 1 ns
ALL INPUT PULSES
10%
90%
90%
10%
≤ 1 ns
(c)
Note:
16.Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05540 Rev. *H Page 19 of 31
[+] Feedback
CY7C1360C
CY7C1362C
Switching Characteristics Over the Operating Range
Parameter Description
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
t
AH
t
ADH
t
ADVH
t
WEH
t
DH
t
CEH
VDD(Typical) to the First Access
Clock Cycle Time 4.0 5.0 6.0 ns
Clock HIGH 1.8 2.0 2.4 ns
Clock LOW 1.8 2. 0 2.4 ns
Data Output Valid after CLK Rise 2.8 3.0 3.5 ns
Data Output Hold after CLK Rise 1.25 1.25 1.25 ns
Clock to Low-Z
Clock to High-Z
[20, 21, 22]
[20, 21, 22]
OE LOW to Output Valid 2.8 3.0 3.5 ns
OE LOW to Output Low-Z
OE HIGH to Output High-Z
Address Set-up before CLK Rise 1.4 1. 5 1.5 ns
ADSC, ADSP Set-up before CLK Rise 1.4 1.5 1.5 ns
ADV Set-up before CLK Rise 1.4 1.5 1.5 ns
GW, BWE, BWX Set-up before CLK Rise 1.4 1.5 1.5 ns
Data Input Set-up before CLK Rise 1.4 1.5 1.5 ns
Chip Enable Set-up before CLK Rise 1.4 1.5 1.5 ns
Address Hold after CLK Rise 0.4 0.5 0.5 ns
ADSP, ADSC Hold after CLK Rise 0.4 0.5 0.5 ns
ADV Hold after CLK Rise 0.4 0.5 0.5 ns
GW, BWE, BWX Hold after CLK Rise 0.4 0.5 0.5 ns
Data Input Hold after CLK Rise 0.4 0.5 0.5 ns
Chip Enable Hold after CLK Rise 0.4 0.5 0.5 ns
[19]
[20, 21, 22]
[20, 21, 22]
[17, 18]
–250 –200 –166
UnitMin. Max. Min. Max. Min. Max.
111ms
1.25 1.25 1.25 ns
1.25 2.8 1.25 3.0 1.25 3.5 ns
000ns
2.8 3.0 3.5 ns
Notes:
17.Timing reference level is 1.5V when V
18.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
19.This part has a voltage regulator internally; t
can be initiated.
, t
20.t
CHZ
21.At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention con dition, but ref lect p aramete rs guarante ed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
22.This parameter is sampled and not 100% tested.
CLZ,tOELZ
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
= 3.3V and is 1.25V when V
DDQ
POWER
OEHZ
Document #: 38-05540 Rev. *H Page 20 of 31
= 2.5V.
DDQ
is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation
is less than t
OELZ
and t
is less than t
CHZ
to eliminate bus contention between SRAMs when sharing th e same
CLZ
[+] Feedback
Switching Waveforms
D
Read Cycle Timing
[23]
t
CYC
CY7C1360C
CY7C1362C
CLK
ADSP
ADSC
ADDRESS
GW, BWE,
BWx
CE
ADV
OE
ata Out (Q)
t
ADS
t
t
AS
CES
t
t
CL
CH
t
ADH
t
t
ADH
ADS
t
AH
A1
t
WES
t
CEH
High-Z
A2 A3
t
WEH
t
t
ADVH
ADVS
ADV
suspends
burst.
t
t
t
CLZ
t
CO
Single READ BURST READ
OEHZ
Q(A1)
OEV
t
OELZ
t
CO
t
DOH
Q(A2) Q(A2 + 1) Q(A2 + 2)
Burst continued with
new base address
Deselect
cycle
t
CHZ
Q(A2) Q(A2 + 1)Q(A2 + 3)
Burst wraps around
to its initial state
Note:
23.On this diagram, when CE
is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05540 Rev. *H Page 21 of 31
DON’T CARE
UNDEFINED
[+] Feedback
Switching Waveforms (continued)
D
Write Cycle Timing
[23, 24]
t
CYC
CY7C1360C
CY7C1362C
CLK
ADSP
ADSC
ADDRESS
BWE,
BW
GW
CE
t
t
CL
CH
t
t
ADH
ADS
t
t
ADH
ADS
t
t
AH
AS
A1
Byte write signals are
ignored for first cycle when
ADSP initiates burst
X
t
t
CEH
CES
A2 A3
t
t
WEH
WES
ADSC extends burst
t
ADS
t
ADH
t
WES
t
ADVS
t
WEH
t
ADVH
ADV
ADV suspends burst
OE
t
t
DH
DS
Data In (D)
ata Out (Q)
Note:
24.
Full width Write can be initiated by either GW
High-Z
BURST READ BURST WRITE
t
OEHZ
D(A1)
Single WRITE
LOW; or by GW HIGH, BWE LOW and BWX LOW.
D(A2) D(A2 + 1) D(A2 + 1)
DON’T CARE
UNDEFINED
D(A2 + 2)
D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)
Extended BURST WRITE
Document #: 38-05540 Rev. *H Page 22 of 31
[+] Feedback
Switching Waveforms (continued)
D
Read/Write Cycle Timing
[23, 25, 26]
t
CYC
CY7C1360C
CY7C1362C
CLK
ADSP
ADSC
ADDRESS
BWE,
BW
X
CE
ADV
OE
Data In (D)
t
t
CL
CH
t
t
ADH
ADS
t
t
AH
AS
High-Z
t
CES
A2
t
CEH
t
CO
t
CLZ
t
OEHZ
t
WES
t
DS
A3
t
t
D(A3)
A1
A4 A5 A6
WEH
DH
t
OELZ
D(A5) D(A6)
ata Out (Q)
Notes:
25.The data bus (Q) remains in high-Z following a Write cycle, unless a new Read access is initiated by ADSP
is HIGH.
26.GW
High-Z
Document #: 38-05540 Rev. *H Page 23 of 31
Q(A2)Q(A1)
Single WRITE
DON’T CARE UNDEFINED
Q(A4) Q(A4+1) Q(A4+2)
BURST READBack-to-Back READs
Q(A4+3)
Back-to-Back
WRITEs
or ADSC.
[+] Feedback
Switching Waveforms (continued)
A
ZZ Mode Timing
[27, 28]
CLK
CY7C1360C
CY7C1362C
t
ZZ
t
ZZREC
ZZ
I
SUPPLY
LL INPUTS
(except ZZ)
Outputs (Q)
t
ZZI
I
DDZZ
High-Z
t
RZZI
DESELECT or READ Only
DON’T CARE
Notes:
27.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
28.DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05540 Rev. *H Page 24 of 31
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CY7C1360C
CY7C1362C
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz) Ordering Code
166 CY7C1360C-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1362C-166AXC
CY7C1360C-166AJXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1362C-166AJXC
CY7C1360C-166BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1362C-166BGC
CY7C1360C-166BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1362C-166BGXC
CY7C1360C-166BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1362C-166BZC
CY7C1360C-166BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1362C-166BZXC
CY7C1360C-166AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1362C-166AXI
CY7C1360C-166AJXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1362C-166AJXI
CY7C1360C-166BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1362C-166BGI
CY7C1360C-166BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1362C-166BGXI
CY7C1360C-166BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1362C-166BZI
CY7C1360C-166BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1362C-166BZXI
visit www.cypress.com for actual products offered.
Package
Diagram Part and Package Type
(3 Chip Enable)
(2 Chip Enable)
(3 Chip Enable)
(2 Chip Enable)
Operating
Range
Commercial
Industrial
Document #: 38-05540 Rev. *H Page 25 of 31
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CY7C1360C
CY7C1362C
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
200 CY7C1360C-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1362C-200AXC
CY7C1360C-200AJXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1362C-200AJXC
CY7C1360C-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1362C-200BGC
CY7C1360C-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1362C-200BGXC
CY7C1360C-200BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1362C-200BZC
CY7C1360C-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1362C-200BZXC
CY7C1360C-200AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1362C-200AXI
CY7C1360C-200AJXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1362C-200AJXI
CY7C1360C-200BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1362C-200BGI
CY7C1360C-200BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1362C-200BGXI
CY7C1360C-200BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1362C-200BZI
CY7C1360C-200BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1362C-200BZXI
visit www.cypress.com for actual products offered.
Commercial
(3 Chip Enable)
(2 Chip Enable)
Industrial
(3 Chip Enable)
(2 Chip Enable)
Document #: 38-05540 Rev. *H Page 26 of 31
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CY7C1360C
CY7C1362C
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
250 CY7C1360C-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1362C-250AXC
CY7C1360C-250AJXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1362C-250AJXC
CY7C1360C-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1362C-250BGC
CY7C1360C-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1362C-250BGXC
CY7C1360C-250BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1362C-250BZC
CY7C1360C-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1362C-250BZXC
CY7C1360C-250AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1362C-250AXI
CY7C1360C-250AJXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
CY7C1362C-250AJXI
CY7C1360C-250BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1362C-250BGI
CY7C1360C-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1362C-250BGXI
CY7C1360C-250BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1362C-250BZI
CY7C1360C-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1362C-250BZXI
visit www.cypress.com for actual products offered.
Commercial
(3 Chip Enable)
(2 Chip Enable)
Industrial
(3 Chip Enable)
(2 Chip Enable)
Document #: 38-05540 Rev. *H Page 27 of 31
[+] Feedback
Package Diagrams
R 0.08 MIN.
0.20 MAX.
0.25
GAUGE PLANE
0°-7°
0.60±0.15
1.00 REF.
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
14.00±0.10
20.00±0.10
22.00±0.20
100
1
30
31 50
0° MIN.
R 0.08 MIN.
0.20 MAX.
0.20 MIN.
A
DETAIL
81
80
0.30±0.08
0.65
TYP.
51
STAND-OFF
0.05 MIN.
0.15 MAX.
SEATING PLANE
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
12°±1°
(8X)
CY7C1360C
CY7C1362C
1.40±0.05
0.20 MAX.
1.60 MAX.
0.10
51-85050-*B
SEE DETAIL
A
Document #: 38-05540 Rev. *H Page 28 of 31
[+] Feedback
Package Diagrams (continued)
A1 CORNER
2165437
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
119-Ball PBGA (14 x 22 x 2.4 mm) (51-85115)
Ø1.00(3X) REF.
1.27
19.50
20.32
22.00±0.20
10.16
CY7C1360C
CY7C1362C
Ø0.05 M C
Ø0.25MCAB
Ø0.75±0.15(119X)
2143657
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
0.70 REF.
12.00
30° TYP.
0.90±0.05
0.25 C
SEATING PLANE
C
0.56
2.40 MAX.
0.15 C
0.60±0.10
A
B
0.15(4X)
3.81
7.62
14.00±0.20
51-85115-*B
1.27
Document #: 38-05540 Rev. *H Page 29 of 31
[+] Feedback
Package Diagrams (continued)
TOP VIEW
TOP VIEW
PIN 1 CORNER
PIN 1 CORNER
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
15.00±0.10
A
0.53±0.05
0.25 C
0.36
B
J
K
L
M
N
P
R
B
0.53±0.05
C
0.36
J
K
L
M
N
P
R
SEATING PLANE
C
13.00±0.10
13.00±0.10
SEATING PLANE
15.00±0.10
A
0.25 C
165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D
165-Ball FBGA (13 x 15 x 1.4 mm) (51-85 180)
1110986754321
1110986754321
14.00
15.00±0.10
15.00±0.10
A
A
0.15(4X)
1.40 MAX.
0.15 C
0.15 C
1.40 MAX.
0.35±0.06
0.35±0.06
11
11
1.00
1.00
14.00
7.00
7.00
5.00
B
B
0.15(4X)
NOTES :
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE WEIGHT : 0.475g
PACKAGE CODE : BB0AC
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
BOTTOM VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.25MCAB
Ø0.50 (165X)
5.00
10.00
13.00±0.10
13.00±0.10
PIN1CORNER
Ø0.05 M C
-0.06
Ø0.25 M C A B
+0.14
Ø0.50 (165X)
1.00
10.00
51-85180-*A
CY7C1360C
CY7C1362C
PIN 1 CORNER
-0.06
1
2345678910
+0.14
2345678910
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1.00
51-85180-*A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel C orporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05540 Rev. *H Page 30 of 31
© Cypress Semiconductor Corporation, 2006. The information contained herein i s su bj ect to ch an ge wi t hout notice. Cypress Semiconductor Corporation assumes no responsib ility for th e u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypre ss does not auth orize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1360C
CY7C1362C
Document History Page
Document Title: CY7C1360C/CY7C1362C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
Document Number: 38-05540
REV. ECN NO. Issue Date
** 241690 See ECN RKF New data sheet
*A 278130 See ECN RKF Changed Boundary Scan order to match the B rev of these devices
*B 248929 See ECN VBL Changed ISB1 and ISB3 from DC Characteristics table as follows:
*C 323636 See ECN PCI Changed frequency of 225 MHz into 250 MHz
*D 332879 See ECN PCI Unshaded 200 and 166 MHz speed bins in the AC/DC Table and Selection
*E 357258 See ECN PCI Changed from Preliminary to Final
*F 3770 95 See ECN PCI Modified test condition in note# 16 from V
*G 408298 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from
*H 501793 See ECN VKN Added the Maximum Rating for Supply Voltage on V
Orig. of
Change Description of Change
Changed TQFP pkg to Lead-free TQFP in Ordering Information section
Added comment of Lead-free BG and BZ packages availability
ISB1: 225 MHz -> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA
ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA
Changed IDDZZ to 50 mA
Added BG and BZ pkg lead-free part numbers to ordering info section
Added t
Changed Θ
6.13 °C/W respectively
Changed Θ
14.0 °C/W respectively
Changed Θ
3.0 °C/W respectively
of 4.0 ns for 250 MHz
CYC
JA
JA
JA
and Θ
and Θ
and Θ
for TQFP Package from 25 and 9 °C/W to 29.41 and
JC
for BGA Package from 25 and 6 °C/W to 34.1 and
JC
for FBGA Package from 27 and 6 °C/W to 16.8 and
JC
Modified address expansion as per JEDEC Standard
Removed comment of Lead-free BG and BZ packages availability
Guide
Added Address Expansion pins in the Pin Definition Table
Changed Device Width (23:18) for 119-BGA from 000000 to 101000
Added separate row for 165 -FBGA Device Width (23:18)
Modified V
Updated Ordering Information Table
, VOH test conditions
OL
Removed Shading on 250MHz Speed Bin in Selection Guide and AC/DC
Table
Changed I
Updated Ordering Information Table
from 30 to 40 mA
SB2
DDQ
< V
“3901 North First Street” to “198 Champion Court”
Changed three
-state to tri-state on page# 9 & page# 10
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in
the Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
Changed t
AC Switching Characteristics table.
, t
from 25 ns to 20 ns and t
TH
TL
from 5 ns to 10 ns in TAP
TDOV
Updated the Ordering Information table.
DD to VDDQ
Relative to GND
DDQ
≤ V
DD
Document #: 38-05540 Rev. *H Page 31 of 31
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