Cypress Semiconductor CY7C132, CY7C136A, CY7C136, CY7C142, CY7C146 User Manual

2K x 8 Dual-Port Static RAM

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Features

R/W

L

BUSY

L

CE

L

OE

L

A

10L

A

0L

A

0R

A

10R

R/W

R

CE

R

OE

R

CE

R

OE

R

CE

L

OE

L

R/W

L

R/W

R

I/O

7L

I/O

0L

I/O

7R

I/O

0R

BUSY

R

INT

L

INT

R

ARBITRATION

LOGIC

(7C132/7C136 ONLY)

AND

INTERRUPTLOGIC

(7C136/7C146ONLY)

CONTROL

I/O

CONTROL

I/O

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS
DECODER

[2]

[3]

[3]

[2]

Logic Block Diagram

Notes

1. CY7C136 and CY7C136A are functionally identical.

2. CY7C132/CY7C136/CY7C136A (Master): BUSY

is open drain output and requires pull up resistor . CY7C142/CY7C146 (Slave): BUSY is input.

3. Open drain outputs; pull up resistor required.

Functional Description

■ True dual-ported memory cells that enable simultaneous reads

of the same memory location

■ 2K x 8 organization

■ 0.65 micron CMOS for optimum speed and power

■ High speed access: 15 ns

■ Low operating power: I

■ Fully asynchronous operation

■ Automatic power down

■ Master CY7C132/CY7C136/CY7C136A

= 110 mA (maximum)

CC

[1]

easily expands data

bus width to 16 or more bits using slave CY7C142/CY7C146

■ BUSY output flag on CY7C132/CY7C136/CY7C136A;

BUSY input on CY7C142/CY7C146

■ INT flag for port to port communication (52-Pin PLCC/PQFP

versions)

■ CY7C136, CY7C136A, and CY7C146 available in 52-pin

PLCC and 52-pin PQFP packages

■ Pb-free packages available

The CY7C132, CY7C136, CY7C136A, CY7C142, and CY7C146
are high speed CMOS 2K x 8 dual-port static RAMs. Two ports
are provided to permit independent access to any location in
memory. The CY7C132, CY7C136, and CY7C136A can be used
as either a standalone 8-bit dual-port static RAM or as a
MASTER dual-port RAM, in conjunction with the
CY7C142/CY7C146 SLAVE dual-port device. They are used in
systems that require 16-bit or greater word widths. This is the
solution to applications that require shared or buffered data, such
as cache memory for DSP, bit-slice, or multiprocessor designs.

Each port has independent control pins; chip enable (CE
enable (R/W
on each port. In addition, an interrupt flag (INT
each port of the 52-pin PLCC version. BUSY

), and output enable (OE). BUSY flags are provided

) is provided on

signals that the port

), write

is trying to access the same location currently being accessed
by the other port. On the PLCC version, INT

is an interrupt flag
indicating that data is placed in an unique location (7FF for the
left port and 7FE for the right port).

An automatic power down feature is controlled independently on
each port by the chip enable (CE

) pins.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-06031 Rev. *E Revised March 24, 2009

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CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Pinouts

1

V

CC

OE

R

A

0R

8
9
10
11
12
13
14
15
16
17
18
19
20

46
45
44
43
42
41
40
39
38
37
36
35
34

2122 23 24 25 26 27 28 29 30 31 32 33

7 6 5 4 3 2 52 51 50 49 48 47

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

NC
I/O

7R

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

I/O

2L

I/O

3L

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

4L5L6L

7L

0R1R2R3R4R5R6R

NC

GND

OE

BUSY

INT

A

R/W

CE

R/W

BUSY

INT

0L

L

L

L

L

L

CE

R

R

R

R

7C136/7C136A

7C146

A

10L

A

10R

46
1
2
3
4
5
6
7
8
9
10
11
12
13

39
38
37
36
35
34
33
32
31
30
29
28
27

1415 16 17 18 19 20 21 22 23 24 25 26

52 51 50 49 48 47 45 44 43 42 41 40

V

CC

OE

BUSY

INT

A

R/W

CE

R/W

BUSY

INT

0L

L

L

L

L

LCER

R

R

R

OE

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

NC
I/O

7R

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

I/O

2L

I/O

3L

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

4L5L6L

7L

0R1R2R3R4R5R6R

NC

GND

7C136/7C136A

7C146

A

10L

A

10R

Note:

4. 15 ns and 25 ns version available in PQFP and PLCC packages only.

Figure 1. 52-Pin PLCC (Top View) Figure 2. 52-Pin PQFP (Top View)

Selection Guide

[4]

7C132-30
7C136-30
7C142-30
7C146-30

7C132-35
7C136-35
7C142-35
7C146-35

7C132-45
7C136-45
7C142-45
7C146-45

Specification

Maximum Access Time

7C132-25
7C136-15
7C146-15

[4]

7C136-25

7C142-25

7C146-25

15 25 30 35 45 55 ns
Maximum Operating Current Com’l/Ind 190 170 170 120 120 110 mA
Maximum Standby Current Com’l/Ind

Shaded areas contain preliminary information.

75 65 65 45 45 35 mA

7C132-55
7C136-55
7C136A-55
7C142-55
7C146-55

Unit

Document #: 38-06031 Rev. *E Page 2 of 15

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CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Maximum Ratings

Notes

5. BUSY

and INT pins only.

6. Duration of the short circuit should not exceed 30 seconds.

7. At f = f

MAX

, address and data inputs are cycling at the maximum frequency of read cycle of 1/trc and using AC Test Waveforms input levels of GND to 3V.

Exceeding maximum ratings may impair the useful life of th e
device. These user guidelines are not tested.

Storage Temperature ..................................... −65°C to +150°C

Ambient Temperature with

Power Applied.................................................. −55°C to +125°C

Supply Voltage to Ground Potential

(Pin 48 to Pin 24)................................................. −0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State.....................................................−0.5V to +7.0V

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions

V

V

V

V

I
I

I

I

I

OH

OL

IH

IL

IX
OZ

OS

CC

SB1

Output HIGH
voltage

Output LOW
voltage

Input HIGH
voltage

Input LOW
voltage

Input load current GND < VI < V
Output leakage

current
Output short

circuit current
VCC Operating

Supply Current
Standby current

both ports, TTL
Inputs

I

SB2

Standby Current
One Port,
TTL Inputs

I

SB3

Standby Current
Both Ports,
CMOS Inputs

I

SB4

Standby Current
One Port,
CMOS Inputs

Shaded areas contain preliminary information.

VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 2.4 V

IOL = 4.0 mA 0.4 0.4 0.4 0.4 V

= 16.0 mA

I

OL

[5]

CC

GND < VO < VCC, Output Disabled –5 +5 −5+5−5+5−5+5μA

VCC = Max., V

[6]

= GND –350 −350 −350 −350 mA

OUT

CE = VIL, Outputs Open,

MAX

[7]

f = f
CEL and CER > VIH,

f = f
CE

[7]

MAX

or CER > VIH,

L

Active Port Outputs Open,
f = f

Both Ports CE
CE
or V

One Port CE
V
Active Port Outputs Open, f = f

[7]

MAX

and

> VCC – 0.2V , VIN > VCC – 0.2V

R

< 0.2V , f = 0

IN

> VCC – 0.2V or VIN < 0.2V ,

IN

L

or CER > VCC – 0.2V ,

L

MAX

DC Input Voltage................................................. −3.5V to +7.0V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch up Current.................................................... > 200 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%

[4]

7C132-35,45
7C136-35,45
7C142-35,45
7C146-35,45

7C136-15
7C146-15

7C132-30

[4]

7C136-25, 30
7C142-30
7C146-25, 30

Min Max Min Max Min Max Min Max

0.5 0.5 0.5 0.5

2.2 2.2 2.2 2.2 V

0.8 0.8 0.8 0.8 V

–5 +5 −5+5−5+5−5+5μA

Com’l/

190 170 120 110 mA

Ind’l
Com’l/

75 65 45 35 mA

Ind’l

Com’l/

135 115 90 75 mA

Ind’l

Com’l/

15 15 15 15 mA

Ind’l

Com’l/

125 105 85 70 mA

Ind’l

[7]

7C132-55
7C136-55
7C136A-55
7C142-55
7C146-55

CC

Unit

Document #: 38-06031 Rev. *E Page 3 of 15

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CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

3.0V

5V

OUTPUT

R1 893Ω

R2
347Ω

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

90%

10%

<5ns

<5ns

5V

OUTPUT

R1 893Ω

R2
347Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT 1.4V

Equivalent to: TH ÉVENIN

EQUIVALENT

5V

281Ω

30 pF

BUSY

OR
INT

BUSY Output Load

(CY7C132/CY7C136 Only)

10%

ALL INPUT PULSES

250Ω

Notes

8. Test conditions assume signal transition t imes of 5 ns or le ss, t iming re ference levels of 1. 5V, input pulse levels of 0 to 3.0V and output loading of th e specified I

OL/IOH,

and 30 pF load capacitance.

9. AC test conditions use V

OH

= 1.6V and VOL = 1.4V.

10.At any given temperature and voltage condition for any given device, t

HZCE

is less than t

LZCE

and t

HZOE

is less than t

LZOE

.

11. t

LZCE

, t

LZWE

, t

HZOE

, t

LZOE, tHZCE,

and t

HZWE

are tested with CL = 5pF as in (b) of AC Test Loads and Waveforms. Transition is measured ± 500 mV from steady state

voltage.

Capacitance

This parameter is guaranteed but not tested.

Parameter Description Test Conditions Max Unit

C
C

IN
OUT

Input Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0V 15 pF
Output Capacitance 10 pF

Figure 3. AC Test Loads and Waveforms

Switching Characteristics

Over the Operating Range (Speeds -15, -25, -30)

Parameter Description

Read Cycle

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

t

PU

t

PD

Shaded areas contain preliminary information.

Document #: 38-06031 Rev. *E Page 4 of 15

Read Cycle Time 15 25 30 ns
Address to Data Valid

[9]

Data Hold from Address Change 0 00ns
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up

[9]
[9]

[7, 10]

[7, 10, 11]

[7, 10]

[7, 10, 11]

[7]

CE HIGH to Power Down

[8]

[7]

[4]

7C132-30
7C136-30
7C142-30
7C146-30

7C136-15

7C146-15

[4]

7C132-25

7C136-25
7C142-25
7C146-25

Min Max Min Max Min Max

15 25 30 ns

15 25 30 ns
10 15 20 ns

3 33ns

10 15 15 ns

3 55ns

10 15 15 ns

0 00ns

15 25 25 ns

Unit

[+] Feedback

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Switching Characteristics

Notes

12.The internal write time of the memory is defined by the overlap of CE

LOW and R/W LOW. Both signals must be LOW t o initiate a write and eit her signal can terminate

a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.

13.These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.

14.CY7C142/CY7C146 only.

15.A write operation on Port A, where Port A has priority , leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY

on Port B goes HIGH.
Port B’s address toggled.
CE

for Port B is toggled.

R/W

for Port B is toggled during valid read.

16.52-pin PLCC and PQFP versions only.

Over the Operating Range (Speeds -15, -25, -30)

Parameter Description

Write Cycle

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

HZWE

t

LZWE

Busy/Interrupt Timing

t

BLA

t

BHA

t

BLC

t

BHC

t

PS

t

WB

t

WH

t

BDD

t

DDD

t

WDD

Interrupt Timing

t

WINS

t

EINS

t

INS

t

OINR

t

EINR

t

INR

Shaded areas contain preliminary information.

[12]

Write Cycle Time 15 25 30 ns
CE LOW to Write End 12 20 25 ns
Address Setup to Write End 12 20 25 ns
Address Hold from Write End 2 22ns
Address Setup to Write Start 0 00ns
R/W Pulse Width 12 15 25 ns
Data Setup to Write End 10 15 15 ns
Data Hold from Write End 0 00ns
R/W LOW to High Z
R/W HIGH to Low Z

[7]
[7]

BUSY LOW from Address Match 15 20 20 ns
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW 15 20 20 ns
BUSY HIGH from CE HIGH

[13]

Port Set Up for Priority 5 55ns
R/W LOW after BUSY LOW

[14]

R/W HIGH after BUSY HIGH 13 20 30 ns
BUSY HIGH to Valid Data 15 25 30 ns
Write Data V alid to Read Data Valid Note 15 Note 15 Note 15 ns
Write Pulse to Data Delay Note 15 Note 15 Note 15 ns

[16]

R/W to INTERRUPT Set Time 15 25 25 ns
CE to INTERRUPT Set Time 15 25 25 ns
Address to INTERRUPT Set Time 15 25 25 ns
OE to INTERRUPT Reset Time
CE to INTERRUPT Reset T i me
Address to INTERRUPT Reset Time

[8]

(continued)

[13]

[13]
[13]

[13]

[4]

7C132-30
7C136-30
7C142-30
7C146-30

Unit

7C136-15

7C146-15

[4]

7C132-25

7C136-25
7C142-25
7C146-25

Min Max Min Max Min Max

10 15 15 ns

0 00ns

15 20 20 ns

15 20 20 ns

0 00ns

15 25 25 ns
15 25 25 ns
15 25 25 ns

Document #: 38-06031 Rev. *E Page 5 of 15

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