CY7C1355C
CY7C1357C
9-Mbit (256K x 36/512K x 18)
Flow-Through SRAM with NoBL™ Architecture
Features
• No Bus Latency™ (NoBL™) architecture eliminates
dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with ze ro
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply (V
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard and lead-free 100-Pin
TQFP, lead-free and non lead-free 119-Ball BGA
package and 165-Ball FBGA package
• Three chip enables for simple depth expansion.
• Automatic Power-down feature avail able using ZZ
mode or CE deselect
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst Capability—linear or interleaved burst order
• Low standby powe r
) pin to enable clock and suspend
DDQ
)
Functional Description
The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18
Synchronous Flow-through Burst SRAM designed specifically
to support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The
CY7C1355C/CY7C1357C is equipped with the advanced No
Bus Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified b y
the Clock Enable (CEN
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
[1]
) signal, which when deasserted
, CE2, CE3) and an
1
) provide for easy bank
Selection Guide
Maximum Access Time 6.5 7.5 ns
Maximum Operating Current 250 180 mA
Maximum CMOS Standby Cur rent 40 40 mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05539 Rev . *E Revised September 14, 2006
133 MHz 100 MHz Unit
[+] Feedback
1
A
B
C
D
C
C
A
B
C
C
Logic Block Diagram – CY7C1355C (256K x 36)
A0, A1, A
MODE
LK
EN
2
C
ADV/LD
BW
BW
BW
BW
WE
CE1
CE2
CE3
ZZ
A
B
C
D
OE
CE
ADDRESS
REGISTER
A1
A0
ADV/LD
C
WRITE ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
D1
D0
Logic Block Diagram – CY7C1357C (512K x 18)
BURST
LOGIC
CY7C1355C
CY7C1357C
A1'
Q1
A0'
Q0
O
U
T
P
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
G
E
DQs
DQP
DQP
DQP
DQP
WRITE
DRIVERS
MEMORY
ARRAY
REGISTER
INPUT
S
E
N
S
E
A
M
P
S
E
ADDRESS
REGISTER
ADV/LD
C
A1
A0
D1
D0
BURST
LOGIC
Q1
Q0
A1'
A0'
LK
EN
A0, A1, A
MODE
C
CE
WRITE ADDRESS
REGISTER
O
U
T
P
ADV/LD
BW
A
BW
B
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
E
DQs
DQP
DQP
G
CE1
CE2
CE3
ZZ
OE
READ LOGIC
SLEEP
CONTROL
INPUT
REGISTER
E
Document #: 38-05539 Rev. *E Page 2 of 28
[+] Feedback
Pin Configurations
100-Pin TQFP Pinout
CY7C1355C
CY7C1357C
BYTE C
BYTE D
DQP
DQ
DQ
V
DDQ
V
DQ
DQ
DQ
DQ
V
V
DDQ
DQ
DQ
Vss/DNU
V
NC
V
DQ
DQ
V
DDQ
V
DQ
DQ
DQ
DQ
V
V
DDQ
DQ
DQ
DQP
SS
SS
DD
SS
SS
SS
1CE2
A
CE
A
1009998979695949392919089888786
1
C
2
C
3
C
4
5
6
C
7
C
8
C
9
C
10
11
12
C
13
C
14
15
16
17
18
D
19
D
20
21
22
D
23
D
24
D
25
D
26
27
28
D
29
D
30
D
C
BWDBW
BWBBWACE3VDDV
CY7C1355C
SS
CLKWECEN
OE
ADV/LD
NC/18M
85
A
A
848382
A
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQP
DQ
DQ
V
DDQ
V
SS
DQ
DQ
DQ
DQ
V
SS
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SS
DQ
DQ
DQ
DQ
V
SS
V
DDQ
DQ
DQ
DQP
B
B
B
B
BYTE B
B
B
B
B
B
A
A
A
A
BYTE A
A
A
A
A
A
31323334353637
A
MODE
Document #: 38-05539 Rev. *E Page 3 of 28
383940414243444546
A
A
A
A1
A0
NC/288M
SS
V
NC/144M
DD
V
NC/72M
A
NC/36M
474849
A
A
A
50
A
A
A
[+] Feedback
Pin Configurations (continued)
100-Pin TQFP Pinout
CY7C1355C
CY7C1357C
BYTE B
NC
NC
NC
V
DDQ
V
NC
NC
DQ
DQ
V
V
DDQ
DQ
DQ
Vss/DNU
V
NC
V
DQ
DQ
V
DDQ
V
DQ
DQ
DQP
NC
V
V
DDQ
NC
NC
NC
SS
SS
DD
SS
SS
SS
1CE2
A
A
100
99989796959493929190898887868584838281
CE
NC
1
2
3
4
5
6
7
8
B
9
B
10
11
12
B
13
B
14
15
16
17
18
B
19
B
20
21
22
B
23
B
24
B
25
26
27
28
29
30
NC
BBWA
BW
CE3VDDV
CY7C1357C
SS
CLKWECEN
OE
ADV/LD
A
NC/18M
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQP
DQ
DQ
V
SS
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SS
DQ
DQ
NC
NC
V
SS
V
DDQ
NC
NC
NC
A
A
A
A
A
BYTE A
A
A
A
A
31323334353637383940414243
A
MODE
Document #: 38-05539 Rev. *E Page 4 of 28
44454647484950
A
A
A
A1
A0
NC/288M
NC/144M
SS
DD
V
V
NC/72M
NC/36M
A
A
A
A
A
A
A
[+] Feedback
Pin Configurations (continued)
119-Ball BGA Pinout (3 Chip Enables with JTAG)
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DDQ
NC/576M
NC/1G
DQ
DQ
V
DDQ
DQ
DQ
V
DDQ
DQ
DQ
V
DDQ
DQ
DQ
NC/144M
NC
V
DDQ
CY7C1355C
CY7C1357C
CY7C1355C (256K x 36)
2345671
AA AANC/18M V
CE
2
DQP
DQ
DQ
DQ
DQ
V
DD
DQ
DQ
DQ
DQ
DQP
C
C
C
C
C
D
D
D
D
D
C
C
C
C
D
D
D
D
A
A
AA
V
SS
V
SS
V
SS
BW
C
V
SS
NC V
V
SS
BW
D
V
SS
V
SS
V
SS
MODE
ADV/LD
V
DD
NC
CE
1
OE
A
WE
DD
CLK
NC
CEN
A1
A0
V
DD
AAA
A
V
V
V
BW
V
NC
V
BW
V
V
V
NC
TDOTCKTDITMS
SS
SS
SS
SS
SS
SS
SS
SS
CE
3
AA
DQP
DQ
B
DQ
B
DQ
DQ
V
DQ
DQ
DQ
DQ
B
B
DD
A
A
A
A
B
A
DQP
A
NC/36MNC/72M
NC
B
A
DDQ
NC
NC
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC/288M
ZZ
V
DDQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/576M
NC/1G
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
NC/144M
NC/72M
V
DDQ
CY7C1357C (512K x 18)
2
AA AANC/18M V
CE
2
NCDQ
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
DQP
B
A
345671
A
ADV/LD
AA
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
V
DD
NC
CE
1
OE
B
A
WE
DD
CLK
NC
CEN
A1
A0
V
DD
A NC/36M A
A
V
V
V
V
V
NC
V
BW
V
V
V
NC
TDOTCKTDITMS
SS
SS
SS
SS
SS
SS
SS
SS
SS
CE
3
AA
DQP
A
NC
DQ
A
NC
DQ
A
V
DD
NC
DQ
A
A
NC
DQ
A
NC
A
AA
NC
DDQ
NC
NC
NC
DQ
A
V
DDQ
DQ
A
NC
V
DDQ
DQ
A
NC
V
DDQ
NC
DQ
A
NC/288M
ZZ
V
DDQ
Document #: 38-05539 Rev. *E Page 5 of 28
[+] Feedback
Pin Configurations (continued)
165-Ball FBGA Pinout (3 Chip enable with JTAG)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/576M
NC/1G
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
NC/144M
MODE
A
A
NC
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
CY7C1355C
CY7C1357C
CY7C1355C (256K x 36)
891011
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
BW
V
V
V
V
V
V
V
V
V
V
B
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
C
D
NC
TDI
TMS
CE
CLK
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCK
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
NC/18M
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
NC
NC DQP
DQ
DQ
DQ
DQ
DQ
B
DQ
B
DQ
B
DQ
B
NC
A
A
A
A
DQ
DQ
DQ
DQ
DQP
NC/288M
DQ
DQ
DQ
DQ
NC
A
B
B
B
B
B
ZZ
A
A
A
A
A
AA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CY7C1357C (512K x 18)
2345671
NC/576M
NC/1G
NC
NC
NC V
NC
NC
NC
DQ
B
DQ
B
DQ
B
DQ
B
DQP
B
NC/144M
MODE
A
A
NC
DQ
B
DQ
B
DQ
B
DQ
B
NC
NC
NC
NC
NC
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
BW
1
B
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
A
CE
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
891011
A
A
NC
NC DQP
NC
NC
NC
NC
NC
DQ
DQ
DQ
DQ
NC
A
A
A
A
A
DQ
DQ
DQ
DQ
ZZ
NCV
NC
NC
NC
NC
NC/288M
A
A
A
A
A
A
AA
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCK
A
NC/18M
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
Document #: 38-05539 Rev. *E Page 6 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Pin Definitions
Name I/O Description
, A1, A Input-
A
0
, BW
BW
A
BWC, BW
WE
B
D
Synchronous
Input-
Synchronous
Input-
Synchronous
ADV/LD Input-
Synchronous
CLK Input-
Clock
CE
CE
CE
OE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CEN Input-
Synchronous
ZZ Input-
Asynchronous
DQ
DQP
s
X
I/O-
Synchronous
I/O-
Synchronous
MODE Input Strap Pin Mode Input. Selects th e burst order of t he device. When tied to Gnd selects linear burst
V
V
V
DD
DDQ
SS
Power Supply Power supply inputs to the core of the device.
I/O Power
Supply
Ground Ground for the device.
TDO JTAG serial output
Synchronous
TDI JT AG serial input
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK. A
are fed to the two-bit burst counter.
[1:0]
Byte Write Inputs, active LOW. Qualified with WE to conduct Writes to the SRAM. Sampled
on the rising edge of CLK.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW .
This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN
is asserted LOW) the internal burst counter is advanced. When LOW,
a new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
. CLK is only recognized if CEN is active LOW.
CEN
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
, and CE3 to select/deselect the device.
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE2 to select/deselect the device.
1
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic
block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE
is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state, when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by
the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN
does not deselect the device, CEN
can be used to extend the previous cycle when required.
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integri ty preserved. For norm al operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous
Read cycle. The direction of the pins is controlled by OE
pins behave as outputs. When HIGH, DQ
outputs are automatically tri-stated during the data portion of a Write sequence, during the
and DQPX are placed in a tri-state condition.The
s
. When OE is asserted LOW, the
clock rise of the
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE
.
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During
Write sequences, DQP
sequence. When tied to V
is controlled by BWX correspondingly.
X
or left floating selects interleaved burst sequence.
DD
Power supply for the I/O circuitry.
Serial data-out to the JT AG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin should be left unconnected. This pin is not available on
TQFP packages.
Serial data-In to the JT AG circuit. Sampled on the rising edge of TCK. If the JT AG feature
is not being utilized, this pin can be left floating or connected to V
This pin is not available on TQFP packages.
through a pull up resistor.
DD
Document #: 38-05539 Rev. *E Page 7 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Pin Definitions (continued)
Name I/O Description
TMS JT AG serial input
Synchronous
TCK JTAG
Clock
NC – No Connects. Not internally connected to the die. 18 Mbit, 36 Mbit, 72 Mbit, 144 Mbit, 288
/DNU Ground/DNU This pin can be connected to Ground or should be left floating.
V
SS
Functional Overview
The CY7C1355C/CY7C1357C is a synchronous flow-through
burst SRAM designed specifically to eliminate wait states
during Write-Read transitions. All synchronous inputs pass
through input registers controlled by the rising edge of the
clock. The clock signal is qualified with the Clock Enable input
signal (CEN
nized and all internal states are maintained. All synchronous
operations are qualified with CEN
from the clock rise (t
Accesses can be initiated by asserting all three Chip Enables
(CE
1
Enable (CEN
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed Writ e
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory arra y
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 7.5
ns (133-MHz device) provided OE
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
). If CEN is HIGH, the clock signal is not recog-
) is 6.5 ns (133-MHz device).
CDV
, CE2, CE3) active at the rising edge of the clock. If Clock
) is active LOW and ADV/LD is asserted LOW,
should be driven LOW once the device has been
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and 4) ADV/LD is asserted
Serial data-In to the JT AG circuit. Sampled on the rising edge of TCK. If the JT AG feature
is not being utilized, this pin can be disconnected or connected to V
available on TQFP packages.
. This pin is not
DD
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to V
. This pin is not available on TQFP packages.
SS
Mbit, 576 Mbit and 1G are address expansion pins and are not internally connected to the
die.
Burst Read Accesses
The CY7C1355C/CY7C1357C has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Reads without reasserting the address
inputs. ADV/LD
must be driven LOW in order to load a new
address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter i s
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
. Maximum access delay
burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal
burst counter regardless of the state of chip enable inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
). BWX can be used to
). All
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address bus
are ALL asserted active, and (3) the Write signal WE
3
is asserted LOW, (2) CE1, CE2,
is loaded into the address register. The write signals are
latched into the Control Logic block. The data lines are
) simplify depth expansion.
automatically tri-stated regardless of the state of the OE
signal. This allows the external logic to present the data on
DQs and DQPX.
On the next clock rise the data presented to DQs and DQP
(or a subset for byte write operations, see Truth Table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
is asserted LOW, (2) CE1, CE2,
The data written during the Write operation is controlled by
BW
signals. The CY7C1355C/CY7C1357C provides byte
X
write capability that is described in the Truth Table. Asserting
the Write Enable input (WE) with the selected Byte Write
Select input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations. Byte Write
is active LOW. After the first
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple Byte Write operations.
Because the CY7C1355C/CY7C1357C is a common I/O
device, data should not be driven into the device while the
outputs are active. The Output Enable (OE
) can be deasserted
HIGH before presenting data to the DQs and DQP
Doing so will tri-state the output drivers. As a safety
input
inputs.
X
X
Document #: 38-05539 Rev. *E Page 8 of 28
[+] Feedback
CY7C1355C
CY7C1357C
precaution, DQs and DQ PX are automatically tri-stat ed during
the data portion of a write cycle, regardless of the state of OE
Burst Write Accesses
The CY7C1355C/CY7C1357C has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Write operations without reasserting the
address inputs. ADV/LD
must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE
inputs are ignored and the burst counter is incremented.
WE
The correct BW
burst write, in order to write the correct bytes of data.
inputs must be driven in each cycle of the
X
, CE2, and CE3) and
1
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
Interleaved Burst Address Table
.
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
A1: A0
Third
Address
A1: A0
guaranteed. The device must be deselected prior to e ntering
the “sleep” mode. CE
for the duration of t
.
.
, CE2, and CE3, must remain inactive
1
after the ZZ input returns LOW.
ZZREC
ZZ Mode Electrical Characteristics
Parameter Description T est Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
Sleep mode standby current ZZ > VDD – 0.2V 50 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
CYC
CYC
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
[2, 3, 4, 5, 6, 7, 8]
Fourth
Address
A1: A0
Fourth
Address
A1: A0
ns
ns
ns
Operation
Used CE1CE2CE3ZZ ADV/LD WE BWXOE CEN CLK DQ
Deselect Cycle None H X X L L X X X L L->H Tri-State
Deselect Cycle None X X H L L X X X L L->H Tri-State
Deselect Cycle None X L X L L X X X L L->H Tri-State
Continue Deselect Cycle None X X X L H X X X L L->H Tri-State
READ Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q)
READ Cycle (Continue Burst) Next X X X L H X X L L L->H Data Out (Q)
NOP/DUMMY READ (Begin Burst) External L H L L L H X H L L->H Tri-State
DUMMY READ (Continue Burst) Next X X X L H X X H L L->H Tri-State
WRITE Cycle (Begin Burst) External L H L L L L L X L L->H Data In (D)
WRITE Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D)
Address
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW
Selects are asserted, see Truth Table for details.
3. Write is defined by BW
4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQs and DQP
6. CEN
= H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE
8. OE
is asynchronous and is not sampled with the clock rise. It is masked internally during W rite cycles. During a Read cycle DQs and DQPX = Tri-state when OE
is inactive or when the device is deselected, and DQs and DQP
, and WE. See Truth Table for Read/Write.
X
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
X
x = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write
.
= data when OE is active.
X
Document #: 38-05539 Rev. *E Page 9 of 28
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CY7C1355C
CY7C1357C
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Address
Operation
Used CE1CE2CE3ZZ ADV/LD WE BWXOE CEN CLK DQ
NOP/WRITE ABORT (Begin Burst) None L H L L L L H X L L->H Tri-State
WRITE ABORT (Continue Burst) Next X X X L H X H X L L->H Tri-State
IGNORE CLOCK EDGE (Stall) Current X X X L X X X X H L->H –
SLEEP MODE None X X X H X X X X X X Tri-State
Partial Truth Table for Read/Write
Function (CY7C1355C) WE BW
[2, 3, 9]
A
BW
B
BW
C
BW
Read H X X X X
Write No bytes written L H H H H
Write Byte A – ( DQ
Write Byte B – (DQ
Write Byte C – (DQ
Write Byte D – (DQ
and DQPA)LLHHH
A
and DQPB)LHLHH
B
and DQPC)LHHLH
C
and DQPD)LHHHL
D
Write All Bytes L L L L L
Truth Table for Read/Write
Function (CY7C1357C) WE BW
[2, 3,9]
A
BW
B
Read H X X
Write - No bytes written L H H
Write Byte A – ( DQ
Write Byte B – (DQ
and DQPA)LHH
A
and DQPB)LHH
B
Write All Bytes L L L
D
Note:
9. Table only lists a partial listi ng of the byte write combinat ions. Any combination of BW
is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05539 Rev. *E Page 10 of 28
[+] Feedback
T
O
CY7C1355C
CY7C1357C
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1355C/CY7C1357C incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.
The CY7C1355C/CY7C1357C contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(V
SS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alternately be connected to V
DD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1 1
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
0 0
EXIT2-DR
UPDATE-DR
1 0
1
0
0
0 0
1
1 1
0 0
0
1
1
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
SELECT
1
0
0
1
0
1
1
0
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
012
TDI TD
TCK
MS TAP CONTROLLER
Selection
Circuitry
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
Instruction Register
012293031 ...
Identification Register
012..x ...
Boundary Scan Register
S
election
Circuitr
y
The 0/1 next to each state represents the value of TMS at the
rising edge of the TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05539 Rev. *E Page 11 of 28
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO bal l on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
[+] Feedback
CY7C1355C
CY7C1357C
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be pla ced betwee n the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V
SS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.The IDCODE instruction is
loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next comman d is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1 149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value th at will be
captured. Repeatable results may not be possible.
To guarante e th at the boun dary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (t
captured correctly if there is no way in a design to stop (o r
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
and tCH). The SRAM clock input might not be
CS
Document #: 38-05539 Rev. *E Page 12 of 28
[+] Feedback
TAP Timing
123456
T
Test Clock
(TCK)
est Mode Select
(TMS)
Test Data-In
(TDI)
Test Data-Out
(TDO)
t
TMSS
t
TDIS
t
t
TH
TL
t
TMSH
t
TDIH
DON’T CARE UNDEFINED
t
CYC
t
TDOX
t
TDOV
CY7C1355C
CY7C1357C
TAP AC Switching Characteristics
Over the Operating Range
[10, 11]
Parameter Description Min. Max. Unit
Clock
t
TCYC
t
TF
t
TH
t
TL
TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH Time 20 ns
TCK Clock LOW Time 20 ns
Output Times
t
TDOV
t
TDOX
TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns
Set-up Times
t
TMSS
t
TDIS
t
CS
TMS Set-Up to TCK Clock Rise 5 ns
TDI Set-Up to TCK Clock Rise 5 ns
Capture Set-Up to TCK Rise 5 ns
Hold Times
t
TMSH
t
TDIH
t
CH
Notes:
and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
10.t
CS
11.Test conditions are specified using the load in TAP AC Test Conditions. t
TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns
R/tF
= 1 ns.
Document #: 38-05539 Rev. *E Page 13 of 28
[+] Feedback
T
F
T
F
CY7C1355C
CY7C1357C
3.3V TAP AC Test Conditions
Input pulse levels................................................ VSS to 3.3V
Input rise and fall times................................................ ...1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
1.5V
50Ω
DO
Z = 50Ω
O
20p
2.5V TAP AC Test Conditions
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time ................................................. .. ..1 ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Te st load termination supply voltage ............................1.25V
2.5V TAP AC Output Load Equivalent
1.25V
50Ω
DO
Z = 50Ω
O
20p
TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.3V ± 0.165V unless
otherwise noted)
[12]
Parameter Description Conditions Min. Max. Unit
V
V
V
V
V
V
I
X
OH1
OH2
OL1
OL2
IH
IL
Output HIGH Voltage IOH = –4.0 mA, V
= –1.0 mA, V
I
OH
DDQ
DDQ
= 3.3V
= 2.5V
Output HIGH Voltage IOH = –100 µA V
Output LOW Voltage IOL = 8.0 mA V
I
= 8.0 mA V
OL
Output LOW Voltage IOL = 100 µA V
Input HIGH Voltage V
Input LOW Voltage V
Input Load Current GND < VIN < V
DDQ
= 3.3V 2.9 V
DDQ
V
= 2.5V 2.1 V
DDQ
= 3.3V 0.4 V
DDQ
= 2.5V 0.4 V
DDQ
= 3.3V 0.2 V
DDQ
V
= 2.5V 0.2 V
DDQ
= 3.3V 2.0 VDD + 0.3 V
DDQ
V
= 2.5V 1.7 VDD + 0.3 V
DDQ
= 3.3V –0.5 0.7 V
DDQ
V
= 2.5V –0.3 0.7 V
DDQ
2.4 V
2.0 V
–5 5 µA
Identification Register Definitions
Instruction Field
Revision Number (31:29) 010 010 Describes the version number
Device Depth (28:24) 01010 01010 Reserved for Internal Use
Device Width (23:18) 001001 001001 Defines memory type and architecture
Cypress Device ID (17:12) 100110 010110 Defines width and density
Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor
ID Register Presence Indicator (0) 1 1 Indicates the presence of an ID register
Note:
12.All voltages referenced to V
Document #: 38-05539 Rev. *E Page 14 of 28
SS
(GND).
CY7C1355C
(256Kx36)
CY7C1357C
(512Kx18) Description
[+] Feedback
CY7C1355C
CY7C1357C
Scan Register Sizes
Register Name Bit Size (x36) Bit Size (x18)
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary Scan Order (119-ball BGA package) 69 69
Boundary Scan Order (165-ball FBGA package) 69 69
Identification Codes
Instruction Code Description
EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and
SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
TDO. This operation does not affect SRAM operations.
Forces all SRAM output drivers to a High-Z state.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
operations.
Document #: 38-05539 Rev. *E Page 15 of 28
[+] Feedback
CY7C1355C
CY7C1357C
119-ball BGA Boundary Scan Order
CY7C1355C (256K x 36) CY7C1357C (512K x 18)
Bit# ball ID
1
K4
2H4 WE
3M4CEN
4F4 OE
5B4ADV/LD
Name Bit# ball ID
CLK 37 R6 A 1
38 T5 A 2 H4 WE 38 T5 A
39 T3 A 3 M4 CEN 39 T3 A
40 R2 A 4 F4 OE 40 R2 A
41 R3 MODE 5 B4 ADV/LD 41 R3 MODE
6G4 A 42 P2 DQP
7C3 A 43 P1 DQ
8 B3 A 44 L2 DQ
Signal
9D6DQP
10 H7 DQ
11 G6 DQ
12 E6 DQ
13 D7 DQ
14 E7 DQ
15 F6 DQ
16 G7 DQ
17 H6 DQ
45 K1 DQ
B
46 N2 DQ
B
47 N1 DQ
B
48 M2 DQ
B
49 L1 DQ
B
50 K2 DQ
B
51 Internal Internal 15 F6 DQ
B
52 H1 DQ
B
53 G2 DQ
B
18 T7 ZZ 54 E2 DQ
19 K7 DQ
20 L6 DQ
21 N6 DQ
22 P7 DQ
23 N7 DQ
24 M6 DQ
25 L7 DQ
26 K6 DQ
27 P6 DQP
55 D1 DQ
A
56 H2 DQ
A
57 G1 DQ
A
58 F2 DQ
A
59 E1 DQ
A
60 D2 DQP
A
61 C2 A 25 Internal Internal 61 C2 A
A
62 A2 A 26 Internal Internal 62 A2 A
A
63 E4 CE
A
28 T4 A 64 B2 CE
29 A3 A 65 L3 BW
30 C5 A 66 G3 BW
31 B5 A 67 G5 BWB 31 B5 A 67 Internal Internal
32 A5 A 68 L5 BW
33 C6 A 69 B6 CE
34 A6 A 34 A6 A
35 P4 A0 35 P4 A0
36 N4 A1 36 N4 A1
Signal
Name Bit# ball Id
K4
D
D
D
D
D
D
D
D
D
C
C
C
C
C
C
C
C
C
1
2
D
C
A
3
6 G4 A 42 Internal Internal
7 C3 A 43 Internal Internal
8 B3 A 44 Internal Internal
9 T2 A 45 Internal Internal
10 Internal Internal 46 P2 DQP
11 Internal Internal 47 N1 DQ
12 Internal Internal 48 M2 DQ
13 D6 DQP
14 E7 DQ
16 G7 DQ
17 H6 DQ
18 T7 ZZ 54 E2 DQ
19 K7 DQ
20 L6 DQ
21 N6 DQ
22 P7 DQ
23 Internal Internal 59 Internal Internal
24 Internal Internal 60 Internal Internal
27 Internal Internal 63 E4 CE
28 T6 A 64 B2 CE
29 A3 A 65 Internal Internal
30 C5 A 66 G3 BW
32 A5 A 68 L5 BW
33 C6 A 69 B6 CE
Signal
Name Bit# ball Id
CLK 37 R6 A
49 L1 DQ
A
A
A
A
A
A
A
A
A
50 K2 DQ
51 Internal Internal
52 H1 DQ
53 G2 DQ
55 D1 DQ
56 Internal Internal
57 Internal Internal
58 Internal Internal
Signal
Name
B
B
B
B
B
B
B
B
B
1
2
B
A
3
Document #: 38-05539 Rev. *E Page 16 of 28
[+] Feedback
CY7C1355C
CY7C1357C
165-ball FBGA Boundary Scan Order
CY7C1355C (256K x 36) CY7C1357C (512K x 18)
Bit# ball ID
Name Bit# ball ID
1 B6 CLK 37 R4 A 1 B6 CLK 37 R4 A
Signal
2B7WE
3A7CEN
4B8 OE
5A8ADV/LD
38 P4 A 2 B7 WE 38 P4 A
39 R3 A 3 A7 CEN 39 R3 A
40 P3 A 4 B8 OE 40 P3 A
41 R1 MODE 5 A8 ADV/LD 41 R1 MODE
6 A9 A 42 N1 DQP
7B10 A 43 L2 DQ
8A10 A 44 K2 DQ
9C11DQP
10 E10 DQ
11 F10 DQ
12 G10 DQ
13 D10 DQ
14 D11 DQ
15 E11 DQ
16 F11 DQ
17 G11 DQ
45 J2 DQ
B
46 M2 DQ
B
47 M1 DQ
B
48 L1 DQ
B
49 K1 DQ
B
50 J1 DQ
B
51 Internal Internal 15 E11 DQ
B
52 G2 DQ
B
53 F2 DQ
B
18 H11 ZZ 54 E2 DQ
19 J10 DQ
20 K10 DQ
21 L10 DQ
22 M10 DQ
23 J11 DQ
24 K11 DQ
25 L11 DQ
26 M11 DQ
27 N11 DQP
55 D2 DQ
A
56 G1 DQ
A
57 F1 DQ
A
58 E1 DQ
A
59 D1 DQ
A
60 C1 DQP
A
61 B2 A 25 Internal Internal 61 B2 A
A
62 A2 A 26 Internal Internal 62 A2 A
A
63 A3 CE
A
28 R11 A 64 B3 CE
29 R10 A 65 B4 BW
30 P10 A 66 A4 BW
31 R9 A 67 A5 BW
32 P9 A 68 B5 BW
33 R8 A 69 A6 CE
34 P8 A 34 P8 A
35 R6 A0 35 R6 A0
36 P6 A1 36 P6 A1
Signal
Name Bit# ball ID
D
D
D
D
D
D
D
D
D
C
C
C
C
C
C
C
C
C
1
2
D
C
B
A
3
6 A9 A 42 Internal Internal
7 B10 A 43 Internal Internal
8 A10 A 44 Internal Internal
9 A11 A 45 Internal Internal
10 Internal Internal 46 N1 DQP
1 1 Internal Internal 47 M1 DQ
12 Internal Internal 48 L1 DQ
13 C11 DQP
14 D11 DQ
16 F11 DQ
17 G11 DQ
18 H11 ZZ 54 E2 DQ
19 J10 DQ
20 K10 DQ
21 L10 DQ
22 M10 DQ
23 Internal Internal 59 Internal Internal
24 Internal Internal 60 Internal Internal
27 Internal Internal 63 A3 CE
28 R11 A 64 B3 CE
29 R10 A 65 Internal Internal
30 P10 A 66 Internal Internal
31 R9 A 67 A4 BW
32 P9 A 68 B5 BW
33 R8 A 69 A6 CE
Signal
Name Bit# ball ID
49 K1 DQ
A
A
A
A
A
A
A
A
A
50 J1 DQ
51 Internal Internal
52 G2 DQ
53 F2 DQ
55 D2 DQ
56 Internal Internal
57 Internal Internal
58 Internal Internal
Signal
Name
B
B
B
B
B
B
B
B
B
1
2
B
A
3
Document #: 38-05539 Rev. *E Page 17 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
Supply Voltage on V
Relative to GND........–0.5V to +4.6V
DD
Relative to GND......–0.5V to +V
DDQ
DD
DC Voltage Applied to Outputs
in Tri-State...........................................–0.5V to V
DDQ
+ 0.5V
Electrical Characteristics Over the Operating Range
DC Input Voltage.................... ... ............–0.5V to V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current....................................................> 200 mA.
Operating Range
Range
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
Industrial –40°C to +85°C
[13, 14]
Ambient
T emperature V
DD
DD
V
to V
+ 0.5V
DDQ
DD
Parameter Description Test Conditions Min. Max. Unit
V
V
DD
DDQ
Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage for 3.3V I/O 3.135 V
DD
for 2.5V I/O 2.375 2.625
V
OH
V
OL
Output HIGH Voltage for 3.3V I/O, I
for 2.5V I/O, I
= −4.0 mA 2.4 V
OH
= −1.0 mA 2.0 V
OH
Output LOW Voltage for 3.3V I/O, IOL= 8.0 mA 0.4 V
for 2.5V I/O, IOL= 1.0 mA 0.4 V
V
IH
V
IL
Input HIGH Voltage
Input LOW Voltage
[13]
for 3.3V I/O 2.0 VDD + 0.3V V
for 2.5V I/O 1.7 V
[13]
for 3.3V I/O –0.3 0.8 V
+ 0.3V V
DD
for 2.5V I/O –0.3 0.7 V
I
X
I
OZ
I
DD
I
SB1
I
SB2
I
SB3
I
SB4
Input Leakage Current
GND ≤ VI ≤ V
except ZZ and MODE
Input Current of MODE Input = V
Input = V
Input Current of ZZ Input = V
Input = V
SS
DD
SS
DD
Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply
Current
Automatic CE
Power-down
Current—TTL Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—TTL Inputs
V
= Max., I
DD
f = f
V
V
f = f
V
V
f = 0, inputs static
V
V
f = f
V
V
static
= 1/t
MAX
= Max, Device Deselected,
DD
≥ VIH or VIN ≤ V
IN
, inputs switching
MAX
= Max, Device Deselected,
DD
≤ 0.3V or VIN > VDD – 0.3V,
IN
= Max, Device Deselected, or
DD
≤ 0.3V or VIN > V
IN
, inputs switching
MAX
= Max, Device Deselected,
DD
≥ VIH or VIN ≤ VIL, f = 0, inputs
IN
DDQ
–5 5 µA
–30 µA
–5 µA
Output Disabled –5 5 µA
DDQ,
OUT
CYC
= 0 mA,
7.5-ns cycle, 133 MHz 250 mA
10-ns cycle, 100 MHz 180 mA
All speeds 110 mA
IL
All speeds 40 mA
All speeds 100 mA
– 0.3V
DDQ
All Speeds 40 mA
5 µA
30 µA
V
Notes:
13.Overshoot: V
14.T
Power-up
(AC) < VDD +1.5V (Pulse width less than t
IH
: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and V
Document #: 38-05539 Rev. *E Page 18 of 28
/2), undershoot: VIL(AC) > –2V (Pulse width less than t
CYC
DDQ
< VDD.
CYC
/2).
[+] Feedback
CY7C1355C
CY7C1357C
Capacitance
[15]
Parameter Description Test Conditions
C
Input Capacitance TA = 25°C, f = 1 MHz,
IN
C
C
CLK
I/O
Clock Input Capacitance 5 5 5 pF
Input/Output Capacitance 5 7 7 pF
Thermal Resistance
[15]
V
V
DD
DDQ
= 3.3V.
= 2.5V
Parameter Description Test Conditions
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA/JESD51.
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
= 50Ω
Z
0
VT= 1.5V
(a)
R
= 50Ω
L
3.3V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
R = 317Ω
(b)
R = 351Ω
100 TQFP
Max.
119 BGA
Max.
165 FBGA
Max. Unit
555pF
100 TQFP
Package
119 BGA
Package
165 FBGA
Package Unit
29.41 34.1 16.8 °C/W
6.31 14.0 3.0 °C/W
V
DDQ
GND
≤ 1 ns
ALL INPUT PULSES
10%
90%
90%
10%
≤ 1 ns
(c)
2.5V I/O Test Load
OUTPUT
= 50Ω
Z
0
= 1.25V
V
T
R
L
(a) (b)
Note:
15.Tested initially and after any design or process change that may affect these parameters
2.5V
OUTPUT
= 50Ω
5pF
INCLUDING
JIG AND
SCOPE
R = 1667Ω
R = 1538Ω
V
DDQ
GND
≤ 1 ns
ALL INPUT PULSES
10%
90%
90%
10%
≤ 1 ns
(c)
Document #: 38-05539 Rev. *E Page 19 of 28
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CY7C1355C
CY7C1357C
Switching Characteristics Over the Operating Range
Parameter Description
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CDV
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
t
AS
t
ALS
t
WES
t
CENS
t
DS
t
CES
Hold Times
t
AH
t
ALH
t
WEH
t
CENH
t
DH
t
CEH
VDD(Typical) to the First Access
Clock Cycle Time 7.5 10 ns
Clock HIGH 3.0 4.0 ns
Clock LOW 3.0 4.0 ns
Data Output Valid after CLK Rise 6.5 7.5 ns
Data Output Hold after CLK Rise 2.0 2.0 ns
Clock to Low-Z
Clock to High-Z
[19, 20, 21]
[19, 20, 21]
OE LOW to Output Valid 3.5 3.5 ns
OE LOW to Output Low-Z
OE HIGH to Output High-Z
Address Set-up before CLK Rise 1.5 1.5 ns
ADV/LD Set-up before CLK Rise 1.5 1.5 ns
WE, BWX Set-up before CLK Rise 1.5 1.5 ns
CEN Set-up before CLK Rise 1.5 1.5 ns
Data Input Set-up before CLK Rise 1.5 1.5 ns
Chip Enable Set-Up before CLK Rise 1.5 1.5 ns
Address Hold after CLK Rise 0.5 0.5 ns
ADV/LD Hold after CLK Rise 0.5 0.5 ns
WE, BWX Hold after CLK Rise 0.5 0.5 ns
CEN Hold after CLK Rise 0.5 0.5 ns
Data Input Hold after CLK Rise 0.5 0 .5 ns
Chip Enable Hold after CLK Rise 0.5 0.5 ns
[18]
[19, 20, 21]
[19, 20, 21]
[16, 17]
–133 –100
UnitMin. Max. Min. Max.
11ms
00ns
3.5 3.5 ns
00ns
3.5 3.5 ns
Notes:
16.Timing reference level is 1.5V when V
17.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18.This part has a voltage regulator internally; t
can be initiated.
, t
19.t
CHZ
20.At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect paramete rs gu arantee d o ver wo rst case use r con ditions. Device is desi gned
to achieve High-Z prior to Low-Z under the same system conditions.
21.This parameter is sampled and not 100% tested.
CLZ,tOELZ
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
= 3.3V and is 1.25V when V
DDQ
POWER
OEHZ
Document #: 38-05539 Rev. *E Page 20 of 28
= 2.5V.
DDQ
is the time that the power needs to be supplied above VDD(minimum) initially , before a Read or W rite operation
is less than t
OELZ
and t
is less than t
CHZ
to eliminate bus contention between SRAMs when sharing the same
CLZ
[+] Feedback
Switching Waveforms
123456789
10
C
Read/Write Waveforms
[22, 23, 24]
CLK
t
t
CENS
CENH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
X
t
CH
t
CYC
CY7C1355C
CY7C1357C
t
CL
ADDRESS
A1 A2
t
t
AS
AH
DQ
D(A1) D(A2) Q(A4)Q(A3)
t
t
DS
DH
A3
t
CDV
t
CLZ
D(A2+1)
OE
OMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
A4
t
DOH
READ
Q(A4)
t
OEHZ
BURST
READ
Q(A4+1)
A5 A6 A7
t
t
OEV
Q(A4+1)
t
OELZ
WRITE
D(A5)
CHZ
t
DOH
D(A5)
READ
Q(A6)
WRITE
D(A7)
DON’T CARE UNDEFINED
Notes:
For this waveform ZZ is tied LOW.
22.
23.When CE
24.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Inte rleaved). Burst operations are optional.
is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
D(A7)Q(A6)
DESELECT
Document #: 38-05539 Rev. *E Page 21 of 28
[+] Feedback
Switching Waveforms (continued)
123456789
10
C
NOP, STALL and DESELECT Cycles
[22, 23, 25]
t
CYC
CLK
t
CENS
t
CENH
t
CH
t
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
X
CL
CY7C1355C
CY7C1357C
ADDRESS
DQ
A1 A2
t
t
AS
AH
D(A1) D(A2) Q(A4)Q(A3)
t
t
DS
DH
A3
t
CDV
t
CLZ
D(A2+1)
OE
OMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
A4
t
DOH
READ
Q(A4)
t
OEHZ
Q(A4+1)
BURST
READ
A5 A6 A7
t
OEV
Q(A4+1)
t
OELZ
WRITE
t
t
D(A5)
CHZ
D(A5)
DOH
READ
Q(A6)
WRITE
D(A7)
DON’T CARE UNDEFINED
Note:
25.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN
being used to create a pause. A write is not performed during this cycle.
D(A7)Q(A6)
DESELECT
Document #: 38-05539 Rev. *E Page 22 of 28
[+] Feedback
Switching Waveforms (continued)
A
ZZ Mode Timing
[26, 27]
CLK
CY7C1355C
CY7C1357C
t
ZZ
t
ZZREC
ZZ
I
SUPPLY
LL INPUTS
(except ZZ)
Outputs (Q)
t
ZZI
I
DDZZ
High-Z
t
RZZI
DESELECT or READ Only
DON’T CARE
Notes:
26.Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
27.DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05539 Rev. *E Page 23 of 28
[+] Feedback
Ordering Information
CY7C1355C
CY7C1357C
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz) Ordering Code
133 CY7C1355C-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1357C-133AXC
CY7C1355C-133BGC 51-85115 11 9-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1357C-133BGC
CY7C1355C-133BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1357C-133BGXC
CY7C1355C-133BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1357C-133BZC
CY7C1355C-133BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1357C-133BZXC
CY7C1355C-133AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial
CY7C1357C-133AXI
CY7C1355C-133BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1357C-133BGI
CY7C1355C-133BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1357C-133BGXI
CY7C1355C-133BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1357C-133BZI
CY7C1355C-133BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1357C-133BZXI
100 CY7C1355C-100AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1357C-100AXC
CY7C1355C-100BGC 51-85115 11 9-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1357C-100BGC
CY7C1355C-100BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1357C-100BGXC
CY7C1355C-100BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1357C-100BZC
CY7C1355C-100BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1357C-100BZXC
CY7C1355C-100AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial
CY7C1357C-100AXI
CY7C1355C-100BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1357C-100BGI
CY7C1355C-100BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1357C-100BGXI
CY7C1355C -100BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1357C-100BZI
CY7C1355C-100BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1357C-100BZXI
visit www.cypress.com for actual products offered.
Package
Diagram Part and Package Type
Operating
Range
Document #: 38-05539 Rev. *E Page 24 of 28
[+] Feedback
Package Diagrams
R 0.08 MIN.
0.20 MAX.
0.25
GAUGE PLANE
0°-7°
0.60±0.15
1.00 REF.
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
14.00±0.10
81
80
0.30±0.08
0.65
TYP.
51
STAND-OFF
0.05 MIN.
0.15 MAX.
SEATING PLANE
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
20.00±0.10
22.00±0.20
100
1
30
31 50
0° MIN.
R 0.08 MIN.
0.20 MAX.
0.20 MIN.
A
DETAIL
12°±1°
(8X)
CY7C1355C
CY7C1357C
1.40±0.05
0.20 MAX.
1.60 MAX.
0.10
51-85050-*B
SEE DETAIL
A
Document #: 38-05539 Rev. *E Page 25 of 28
[+] Feedback
Package Diagrams (continued)
A1 CORNER
2165437
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
Ø1.00(3X) REF.
1.27
19.50
20.32
22.00±0.20
10.16
CY7C1355C
CY7C1357C
Ø0.05 M C
Ø0.25MCAB
Ø0.75±0.15(119X)
2143657
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
0.70 REF.
12.00
30° TYP.
0.90±0.05
0.25 C
SEATING PLANE
C
0.56
2.40 MAX.
0.15 C
0.60±0.10
A
B
0.15(4X)
3.81
7.62
14.00±0.20
51-85115-*B
1.27
Document #: 38-05539 Rev. *E Page 26 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Package Diagrams (continued)
165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D
165-Ball FBGA (13 x 15 x 1.4 mm) (51-85 180)
TOP VIEW
TOP VIEW
PIN 1 CORNER
15.00±0.10
A
0.25 C
15.00±0.10
A
0.53±0.05
0.25 C
0.36
B
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
B
0.53±0.05
C
0.36
PIN 1 CORNER
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
SEATING PLANE
C
13.00±0.10
13.00±0.10
SEATING PLANE
1110986754321
1110986754321
14.00
15.00±0.10
15.00±0.10
A
A
0.15(4X)
1.40 MAX.
0.15 C
0.15 C
1.40 MAX.
0.35±0.06
0.35±0.06
11
1.00
1.00
14.00
7.00
7.00
B
B
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Techno logy, Inc. All product and company names mentioned in this document are the trademarks of their respective holders
11
5.00
BOTTOM VIEW
5.00
10.00
13.00±0.10
BOTTOM VIEW
Ø0.05 M C
Ø0.05 M C
Ø0.25MCAB
-0.06
Ø0.25 M C A B
Ø0.50 (165X)
+0.14
Ø0.50 (165X)
10.00
13.00±0.10
PIN1CORNER
-0.06
+0.14
1.00
1.00
PIN 1 CORNER
1
2345678910
2345678910
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
N
N
P
P
R
R
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
51-85180-*A
51-85180-*A
Document #: 38-05539 Rev. *E Page 27 of 28
© Cypress Semiconductor Corporation, 2006. The information contained herei n is su bj ect to change without notice. Cypress Semiconduct or Corpo ration assu mes no resp onsib ility for th e us e
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypres s does not auth orize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1355C
CY7C1357C
Document History Page
Document Title: CY7C1355C/CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05539
REV. ECN NO. Issue Date
** 242032 See ECN RKF New data sheet
*A 332059 See ECN PCI Changed Boundary Scan Order to match the B rev of these devices
*B 351895 See ECN PCI Changed I
*C 377095 See ECN PCI Modified test condition in note# 14 from V
*D 408298 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from
*E 501793 See ECN VKN Added the Maximum Rating for Supply Voltage on V
Orig. of
Change Description of Change
Removed description on Extest Output Bus Tri-state
Removed 117 MHz Speed Bin
Changed I
Changed I
Address expansion pins/balls in the pinouts for all packages are modified as
from 35 mA to 50 mA on Pg # 9
DDZZ
SB1
and I
from 40 mA to 110 and 100 mA respectively
SB3
per JEDEC standard
Modified V
Corrected I
or V
Changed Θ
OL, VOH
SB4
≤ VIL) in the Electrical Characteristic Table on Pg #18
IN
6.13 °C/W
test conditions
Test Condition from (VIN ≥ V
and ΘJc for TQFP Package from 25 and 9 °C/W to 29.41 and
JA
– 0.3V or VIN ≤ 0.3V) to (VIN ≥ VIH
DD
respectively
Changed Θ
°C/W
and ΘJc for BGA Package from 25 and 6 °C/W to 34.1 and 14.0
JA
respectively
Changed Θ
°C/W respectively
JA
and Θ
for FBGA Package from 27 and 6 °C/W to 16.8 and 3.0
Jc
Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA
Packages
Updated Ordering Information Table
Changed from Preliminary to Final
from 30 to 40 mA
Updated Ordering Information Table
SB2
IH
< V
DD to VIH
“3901 North First Street” to “198 Champion Court”
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Changed three-state to tri-state
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
Changed t
Switching Characteristics table.
, t
from 25 ns to 20 ns and t
TH
TL
from 5 ns to 10 ns in TAP AC
TDOV
Updated the Ordering Information table.
< V
DD
Relative to GND
DDQ
Document #: 38-05539 Rev. *E Page 28 of 28
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