p
a
b
c
d
C
CY7C1354C
CY7C1356C
9-Mbit (256K x 36/512K x 18)
Pi
elined SRAM with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200, and 166 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 3.3V power supply (VDD)
• 3.3V or 2.5V I/O power supply (V
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
• Clock Enable (CEN
) pin to suspend operation
• Synchronous self-timed writes
• Available in lead-free 100-Pin TQFP package, lead-free
and non lead-free 119-Ball BGA package and 165-Ball
FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability–linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
DDQ
)
Functional Description
[1]
The CY7C1354C and CY7C1356C are 3.3V, 256K x 36 and
512K x 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL™) logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations
with no wait states. The CY7C1354C and CY7C1356C are
equipped with the advanced (NoBL) logic requi red to enable
consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1354C and CY7C1356C are
pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
–BWd for CY7C1354C and BWa–BWb for CY7C1356C)
a
and a Write Enable (WE
) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Logic Block Diagram–CY7C1354C (256K x 36)
A0, A1, A
MODE
C
CLK
EN
ADV/LD
BW
a
BW
b
BW
c
BW
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
d
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
ADV/LD
REGISTER 2
C
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
I
M
S
T
P
E
S
R
S
E
E
REGISTER 0
INPUT
O
D
U
T
A
P
T
U
A
T
B
S
T
E
E
R
I
N
G
E
DQs
U
DQP
F
DQP
F
DQP
E
DQP
R
S
E
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05538 Rev . *G Revised September 14, 2006
[+] Feedback
a
b
C
Logic Block Diagram–CY7C1356C (512K x 18)
CY7C1354C
CY7C1356C
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
ADV/LD
WRITE ADDRESS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
Sleep
Control
C
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
U
T
P
S
U
E
T
N
S
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
E
REGISTER 0
INPUT
O
U
T
P
D
U
A
T
T
A
B
DQs
U
S
F
T
E
E
R
I
N
G
E
DQP
F
DQP
E
R
S
E
CLK
A0, A1, A
MODE
C
EN
ADV/LD
BW
a
BW
b
WE
OE
CE1
CE2
CE3
ZZ
Selection Guide
250 MHz 200 MHz 166 MHz Unit
Maximum Access Time 2.8 3.2 3.5 ns
Maximum Operating Current 250 220 180 mA
Maximum CMOS Standby Current 40 40 40 mA
Document #: 38-05538 Rev. *G Page 2 of 28
[+] Feedback
Pin Configurations
a
100-Pin TQFP Pinout
CY7C1354C
CY7C1356C
DQPc
DQc
DQc
V
DDQ
V
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
V
DDQ
DQd
DQd
DQPd
1CE2
A
A
CE
BWa
BWd
BWc
BWb
CE3VDDV
SS
CLKWECEN
100999897969594939291908988878685848382
1
2
3
4
5
SS
6
7
8
9
10
11
12
13
14
15
16
CY7C1354C
(256K × 36)
17
18
19
20
21
22
23
24
25
SS
26
27
28
29
30
31323334353637383940414243444546474849
OE
ADV/LD
A
NC(18)
A
A
81
DDQ
SS
SS
DDQ
SS
DD
DDQ
SS
SS
DDQ
NC
NC
NC
V
DDQ
V
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
NC
V
DD
NC
V
DQb
DQb
V
DDQ
V
DQb
DQb
DQPb
NC
V
V
DDQ
NC
NC
NC
SS
SS
SS
SS
DQPb
80
DQb
79
DQb
78
V
77
V
76
DQb
75
DQb
74
DQb
73
DQb
72
V
71
V
70
DQb
69
DQb
68
V
67
NC
66
V
65
ZZ
64
DQa
63
DQa
62
V
61
V
60
DQa
59
DQa
58
DQa
57
DQa
56
V
55
V
54
DQa
53
DQa
52
DQPa
51
50
1CE2
A
A
CE
NC
NC
BWa
BWb
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CY7C1356C
(512K × 18)
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
SS
CE3VDDV
CLKWECENOENC(18)
A
ADV/LD
A
A
81
A
80
NC
79
NC
78
V
77
DDQ
V
SS
76
NC
75
DQP
74
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
AAA
MODE
0
A
A1A
SS
DD
V
V
NC(288)
NC(144)
AAA
A
NC(36)
NC(72)
A
A
A
A
AAA
MODE
1A0
A
AAA
A
DD
SS
V
V
NC(144)
NC(288)
A
NC(36)
NC(72)
A
A
Document #: 38-05538 Rev. *G Page 3 of 28
[+] Feedback
Pin Configurations (continued)
V
A
NC/576M
B
NC/1G
C
D
E
V
F
G
H
V
J
K
L
V
M
N
P
NC/144M
R
T
V
U
DDQ
DQ
DQ
DDQ
DQ
DQ
DDQ
DQ
DQ
DDQ
DQ
DQ
NC
DDQ
c
c
c
c
d
d
d
d
119-Ball BGA Pinout
CY7C1354C (256K × 36)
2345671
AA AANC/18M V
CE
2
A
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQd
DQ
d
DQP
d
A
NC/72M
TMS
A
A
V
SS
V
SS
V
SS
BW
V
SS
NC
V
SS
BW
V
SS
V
SS
V
SS
MODE
A
ADV/LD
V
DD
NC DQP
CE
1
OE
c
A
WE
V
DD
CLK
NC
d
CEN
A1
A0 V
V
DD
A NC/36M
TCK
ACE3NC
AANC
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
BW
V
SS
V
SS
SS
DQ
DQ
DQ
b
DQ
DD
DQ
DQ
a
DQ
DQ
DQP
NC
A
NCTDI TDO V
CY7C1354C
CY7C1356C
DDQ
DQ
b
b
b
b
b
a
a
a
a
a
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC/288MA
ZZ
DDQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/576M
NC/1G
b
NC
V
DDQ
NC
DQ
b
V
DDQ
NC
DQ
b
V
DDQ
DQ
b
NC
NC/144M
NC/72M
V
DDQ
CY7C1356C (512K x 18)
2345671
AA AANC/18M V
CE
A
NCDQ
DQ
NC
DQ
NC
V
DD
DQ
NC
DQ
NC
DQP
A
A
TMS
2
b
b
b
b
b
A
A
V
SS
V
SS
V
SS
BW
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
ADV/LD
V
DD
NC NCDQP
CE
1
OE
b
AVSSNC
WE
V
DD
CLK
NC NC
CEN
A1
A0 V
V
DD
NC/36M
A
AANC
V
SS
V
SS
V
SS
V
SS
NC V
SS
BW
a
V
SS
V
SS
SS
NC
A
TCK
CE
3
a
NC
DQ
a
DQ
a
DD
NCV
DQ
a
NC V
DQ
a
NC
A
A
NCTDI TDO V
DDQ
NC
DQ
a
V
DDQ
DQ
a
NC
V
DDQ
DQ
a
DDQ
NC
DQ
a
NC/288M
ZZ
DDQ
Document #: 38-05538 Rev. *G Page 4 of 28
[+] Feedback
Pin Configurations (continued)
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/576M
NC/1G
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
NC
DQ
d
DQ
d
DQ
d
DQ
d
DQP
d
NC/144M
MODE
NC/576M
NC/1G
NC
NC
NC V
NC
NC
NC
DQ
b
DQ
b
DQ
b
DQ
b
DQP
b
NC/144M
MODE
A
A
NC
DQ
c
DQ
c
DQ
c
DQ
c
NC
DQ
d
DQ
d
DQ
d
DQ
d
NC
NC/72M
NC/36M
2345671
A
A
NC
DQ
b
DQ
b
DQ
b
DQ
b
NC
NC
NC
NC
NC
NC
NC/72M
NC/36M
CE
CE2
V
V
V
V
V
NC
V
V
V
V
V
CE
CE2
V
V
V
V
V
NC
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
CY7C1354C
CY7C1356C
165-Ball FBGA Pinout
CY7C1354C (256K × 36)
891011
V
V
V
V
V
V
V
V
V
V
A AADV/LD
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
NC DQP
DQ
b
DQ
b
DQ
b
DQ
b
NC
DQ
a
DQ
a
DQ
a
DQ
a
NC
A
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
c
BW
d
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
CE
b
CLK
a
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
CEN
3
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
OE NC/18M
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
CY7C1356C (512K × 18)
891011
BW
1
b
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
BW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
CE
CLK
a
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCKA0
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
A A
NC/18M NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
NC DQP
NC
NC
NC
NC
NC
DQ
a
DQ
a
DQ
a
DQ
a
NC
A
NC
NC
b
DQ
b
DQ
b
DQ
b
DQ
b
ZZ
DQ
a
DQ
a
DQ
a
DQ
a
DQP
a
NC/288M
AA
A
a
DQ
a
DQ
a
DQ
a
DQ
a
ZZ
NCV
NC
NC
NC
NC
NC/288M
AA
Document #: 38-05538 Rev. *G Page 5 of 28
[+] Feedback
CY7C1354C
CY7C1356C
Pin Definitions
Pin Name I/O Type Pin Description
A0, A1
A
,BWb,
BW
a
BW
,BWd,
c
WE
ADV/LD
CLK Input-
CE
1
CE
2
CE
3
OE Input-
CEN
DQ
S
DQP
X
MODE Input Strap Pin Mode Input. Selects the burst order of the device. T ied HIGH selects the interleaved burst order.
TDO JTAG serial
TDI JTAG serial input
TMS T est Mode Select
TCK JTAG-Clock Clock input to the JTAG circuitry.
V
DD
V
DDQ
V
SS
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE
Sampled on the rising edge of CLK. BW
BW
controls DQc and DQPc, BWd controls DQd and DQPd.
c
controls DQa and DQPa, BWb controls DQb and DQPb,
a
to conduct writes to the SRAM.
Write Enable Input, active LOW. Sampled on the ri sing edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN
is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD
be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
CLK is only recognized if CEN
Chip Enable 1 Input, active LOW . Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW . Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE2 to select/deselect the device.
1
is active LOW.
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
Asynchronous
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a Write sequence, during the first clock when emerging from a deselected
state and when the device has been deselected.
Input-
Synchronous
I/O-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
deselect the device, CEN
can be used to extend the previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by addresses during the previous clock rise of the Read cycle. The direction of the pins
is controlled by OE
as outputs. When HIGH, DQ
ically tri-stated during the data portion of a write sequence, during the first clock when emerging
and the internal control logic. When OE is asserted LOW, the pins can behave
–DQd are placed in a tri-state condition. The outputs are automat-
a
from a deselected state, and when the device is deselected, regardless of the state of OE.
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ
write sequences, DQP
, and DQPd is controlled by BWd.
BW
c
is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by
a
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
output
Synchronous
Serial data-In to the JTAG circuit. Sampled on the risi ng edge of TCK.
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground Ground for the device. Should be connected to ground of the system.
should
does not
During
[a:d].
.
Document #: 38-05538 Rev. *G Page 6 of 28
[+] Feedback
Pin Definitions (continued)
Pin Name I/O Type Pin Description
NC – No connects. This pin is not connected to the die.
NC (18, 36,
72, 144, 288,
576, 1G)
ZZ Input-
– These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
288M, 576M and 1G densities.
ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep”
Asynchronous
condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
CY7C1354C
CY7C1356C
Functional Overview
The CY7C1354C and CY7C1356C are synchronous-pipelined
Burst NoBL SRAMs designed specifically to eliminate wait
states during Write/Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of
the clock. The clock signal is qualified with the Clock Enable
input signal (CEN
recognized and all internal states are maintained. All
synchronous operations are qualified with CEN
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
) is 2.8 ns (250-MHz device).
CO
Accesses can be initiated by asserting all three Chip Enables
(CE
, CE2, CE3) active at the rising edge of the clock. If Clock
1
Enable (CEN
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE
Writes are simplified with on-chip synchronous self-timed
Write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.8 ns
(250-MHz device) provided OE
clock of the read access the output buffers are controlled by
OE
and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will tri-state following the
next clock rise.
). If CEN is HIGH, the clock signal is not
. All data
) is active LOW and ADV/LD is asserted LOW,
). BW
can be used to
[d:a]
). All
, CE2, CE3) and an
1
) simplify depth expansion.
is asserted LOW, (2) CE1, CE2,
is active LOW. After the first
Burst Read Accesses
The CY7C1354C and CY7C1356C have an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD
must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter i s
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to A0–A16 is loaded
are ALL asserted active, and (3) the Write signal WE
3
is asserted LOW, (2) CE1, CE2,
into the Address Register. The write signals are latched into
the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
allows the external logic to present the data on DQ
(DQ
CY7C1356C). In addition, the address for the subsequent
a,b,c,d
/DQP
for CY7C1354C and DQ
a,b,c,d
input signal. This
and DQP
a,b
/DQP
a,b
for
access (Read/Write/Deselect) is latched into the address
register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ
(DQ
CY7C1356C) (or a subset for byte write operations, see Write
a,b,c,d
/DQP
for CY7C1354C and DQ
a,b,c,d
a,b
and DQP
/DQP
a,b
for
Cycle Description table for details) inputs is latched into the
device and the Write is complete.
The data written during the Write operation is controlled by BW
(BW
signals. The CY7C1354C/CY7C1356C provides Byte Write
for CY7C1354C and BW
a,b,c,d
for CY7C1356C)
a,b
capability that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE
Write Select (BW
) input will selectively write to only the desired
) with the selected Byte
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the Write operations. Byte Write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple Byte Write operations.
Document #: 38-05538 Rev. *G Page 7 of 28
[+] Feedback
CY7C1354C
CY7C1356C
Because the CY7C1354C and CY7C1356C are common I/O
devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQ
(DQ
CY7C1356C) inputs. Doing so will tri-state the output drivers.
As a safety precaution, DQ
CY7C1354C and DQ
automatically tri-stated during the data portion of a write cycle,
a,b,c,d
/DQP
for CY7C1354C and DQ
a,b,c,d
and DQP
/DQP
a,b
a,b
(DQ
a,b,c,d
for CY7C1356C) are
and DQP
/DQP
a,b
/DQP
a,b
a,b,c,d
for
for
regardless of the state of OE.
Burst Write Accesses
The CY7C1354C/CY7C1356C has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four WRITE operations without reasserting the
address inputs. ADV/LD
must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD
quent clock rise, the chip enables (CE
WE
inputs are ignored and the burst counter is incremented.
The correct BW
CY7C1356C) inputs must be driven in each cycle of the burst
(BW
a,b,c,d
is driven HIGH on the subse-
, CE2, and CE3) and
1
for CY7C1354C and BW
a,b
for
write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
the duration of t
, CE2, and CE3, must remain inactive for
1
after the ZZ input returns LOW.
ZZREC
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
DD
)
Third
Address
Fourth
Address
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
Third
Address
Fourth
Address
clock cycles are required to enter into or exit from this “sleep”
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
Deselect Cycle None H L L X X X L L-H Tri-State
Continue Deselect Cycle None X L H X X X L L-H Tri-State
Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q)
Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q)
NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State
Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State
Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D)
Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D)
Sleep mode standby current ZZ > VDD − 0.2V 50 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
[2, 3, 4, 5, 6, 7, 8]
Address
Operation
Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ
CYC
CYC
ns
ns
ns
Notes:
2. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE
Valid si gnifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
3. Write is defined by WE
4. When a write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE
= H inserts wait states.
6. CEN
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycle s. During a read cycle DQs and DQPX = Tri-state when OE
8. OE
is inactive or when the device is deselected, and DQs = data when OE
and BWX. See Write Cycle Description table for details.
Document #: 38-05538 Rev. *G Page 8 of 28
stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx =
signal.
.
is active.
[+] Feedback
CY7C1354C
CY7C1356C
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Address
Operation
Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ
NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-State
WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State
IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H SLEEP MODE None X H X X X X X X Tri-State
Partial Write Cycle Description
Function (CY7C1354C)
[2, 3, 4, 9]
WE
BW
d
BW
c
BW
b
BW
a
Read H X X X X
Write –No bytes written L H H H H
Write Byte a – (DQ
Write Byte b – (DQ
and DQPa) LHHHL
a
and DQPb)LHHLH
b
Write Bytes b, a L H H L L
Write Byte c – (DQ
and DQPc)LHLHH
c
Write Bytes c, a L H L H L
Write Bytes c, b L H L L H
Write Bytes c, b, a L H L L L
Write Byte d – (DQ
and DQPd)LLHHH
d
Write Bytes d, a L L H H L
Write Bytes d, b LLHLH
Write Bytes d, b, a L L H L L
Write Bytes d, c L L L H H
Write Bytes d, c, a L L L H L
Write Bytes d, c, b L L L L H
Write All Bytes L L L L L
Partial Write Cycle Description
[2, 3, 4, 9]
Function (CY7C1356C)
Read Hxx
Write – No Bytes Written L H H
Write Byte a − (DQ
Write Byte b – (DQ
and DQP
a
and DQP
b
a)
b)
Write Both Bytes L L L
Note:
9. Table only lists a partial listin g of the byte write combinat ions. Any combination of BW
Document #: 38-05538 Rev. *G Page 9 of 28
WE
BW
b
BW
a
LHL
LLH
is valid. Appropriate write will be done based on which byte write is active.
X
[+] Feedback
T
O
CY7C1354C
CY7C1356C
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354C/CY7C1356C incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.
The CY7C1354C/CY7C1356C contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V
) to prevent clocking of the device. TDI and TMS are inter-
SS
nally pulled up and may be unconnected. They may alternately
be connected to V
left unconnected. Upon power-up, the device will come up in
through a pull-up resistor. TDO should be
DD
a reset state which will not interfere with the operation of the
device.
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1 1
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
0 0
EXIT2-DR
UPDATE-DR
1 0
1
0
0
0 0
1
1 1
0 0
0
1
1
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
SELECT
0
0
1
1
1
1
0
0
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
012
TDI TD
TCK
MS TAP CONTROLLER
Selection
Circuitry
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (V
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
Instruction Register
012293031 ...
Identification Register
012..x ...
Boundary Scan Register
S
election
Circuitr
y
DD
) for five
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05538 Rev. *G Page 10 of 28
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO bal l on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
[+] Feedback
CY7C1354C
CY7C1356C
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be pla ced betwee n the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V
) when the BYPASS instruction is executed.
SS
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1 149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TA P
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction reg ister
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1 149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To g uarantee that the boundary scan regi ster will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (t
captured correctly if there is no way in a design to stop (o r
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
and tCH). The SRAM clock input might not be
CS
Document #: 38-05538 Rev. *G Page 11 of 28
[+] Feedback
123456
T
CY7C1354C
CY7C1356C
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
TAP Timing
Test Clock
(TCK)
t
est Mode Select
(TMS)
t
Test Data-In
(TDI)
Test Data-Out
(TDO)
TMSS
TDIS
t
t
TMSH
t
TDIH
TH
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
t
TL
t
CYC
t
TDOX
t
TDOV
DON’T CARE UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range
[10, 11]
Parameter Description Min. Max. Unit
Clock
t
TCYC
t
TF
t
TH
t
TL
TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH time 20 ns
TCK Clock LOW time 20 ns
Output Times
t
TDOV
t
TDOX
TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns
Set-up Times
t
TMSS
t
TDIS
t
CS
TMS Set-up to TCK Clock Rise 5 ns
TDI Set-up to TCK Clock Rise 5 ns
Capture Set-up to TCK Rise 5 ns
Hold Times
t
TMSH
t
TDIH
t
CH
Notes:
and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
10.t
CS
11.Test conditions are specified using the load in TAP AC test Conditions. t
TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns
= 1 ns.
R/tF
Document #: 38-05538 Rev. *G Page 12 of 28
[+] Feedback
T
F
T
F
CY7C1354C
CY7C1356C
3.3V TAP AC Test Conditions
Input pulse levels................................................ VSS to 3.3V
Input rise and fall times................................................ ...1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
1.5V
50Ω
DO
Z = 50Ω
O
20p
2.5V TAP AC Test Conditions
Input pulse levels.................................................VSS to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Test loa d termination supply voltage ............................1.25V
2.5V TAP AC Output Load Equivalent
1.25V
50Ω
DO
Z = 50Ω
O
20p
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)
Parameter Description Test Conditions Min. Max. Unit
V
V
V
V
V
V
I
OH1
OH2
OL1
OL2
IH
IL
X
Output HIGH Voltage IOH = –4.0 mA, V
I
= –1.0 mA, V
OH
Output HIGH Voltage IOH = –100 µA V
Output LOW Voltage IOL = 8.0 mA V
Output LOW Voltage IOL = 100 µA V
Input HIGH Voltage V
Input LOW Voltage V
Input Load Current GND < VIN < V
[12]
= 3.3V 2.4 V
DDQ
= 2.5V 2.0 V
DDQ
= 3.3V 2.9 V
DDQ
V
= 2.5V 2.1 V
DDQ
= 3.3V 0.4 V
DDQ
V
= 2.5V 0.4 V
DDQ
= 3.3V 0.2 V
DDQ
V
= 2.5V 0.2 V
DDQ
= 3.3V 2.0 VDD + 0.3 V
DDQ
V
= 2.5V 1.7 VDD + 0.3 V
DDQ
= 3.3V –0.3 0.8 V
DDQ
V
= 2.5V –0.3 0.7 V
DDQ
DDQ
–5 5 µA
Identification Register Definitions
Instruction Field CY7C1354C CY7C1356C Description
Revision Number (31:29) 000 000 Reserved for version number.
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor.
ID Register Presence (0) 1 1 Indicate the presence of an ID register.
Notes:
12.All voltages referenced to V
13.Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05538 Rev. *G Page 13 of 28
[13]
(GND).
SS
01011001000100110 01011001000010110 Reserved for future use.
[+] Feedback
CY7C1354C
CY7C1356C
Scan Register Sizes
Register Name Bit Size (x36) Bit Size (x18)
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary Scan Order (119-ball BGA package) 69 69
Boundary Scan Order (165-ball FBGA package) 69 69
Identification Codes
Instruction Code Description
EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 11 1 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
TDO. Forces all SRAM outputs to High-Z state.
operation does not affect SRAM operation.
Forces all SRAM output drivers to a High-Z state.
Does not affect the SRAM operation.
Document #: 38-05538 Rev. *G Page 14 of 28
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CY7C1354C
CY7C1356C
Boundary Scan Exit Order (256K × 36)
Bit # 119-ball ID 165-ball ID
1K4 B6
2H4 B7
3M4 A7
4F4 B8
5B4 A8
6G4 A9
7C3 B10
8B3 A10
9D6 C11
10 H7 E10
11 G6 F10
12 E6 G10
13 D7 D10
14 E7 D11
15 F6 E11
16 G7 F11
17 H6 G11
18 T7 H11
19 K7 J10
20 L6 K10
21 N6 L10
22 P7 M10
23 N7 J11
24 M6 K11
25 L7 L11
26 K6 M11
27 P6 N11
28 T4 R11
29 A3 R10
30 C5 P10
31 B5 R9
32 A5 P9
33 C6 R8
34 A6 P8
35 P4 R6
36 N4 P6
37 R6 R4
38 T5 P4
39 T3 R3
40 R2 P3
41 R3 R1
42 P2 N1
43 P1 L2
Boundary Scan Exit Order (256K × 36) (continued)
Bit # 119-ball ID 165-ball ID
44 L2 K2
45 K1 J2
46 N2 M2
47 N1 M1
48 M2 L1
49 L1 K1
50 K2 J1
51 Not Bonded
(Preset to 1)
52 H1 G2
53 G2 F2
54 E2 E2
55 D1 D2
56 H2 G1
57 G1 F1
58 F2 E1
59 E1 D1
60 D2 C1
61 C2 B2
62 A2 A2
63 E4 A3
64 B2 B3
65 L3 B4
66 G3 A4
67 G5 A5
68 L5 B5
69 B6 A6
Not Bonded
(Preset to 1)
Document #: 38-05538 Rev. *G Page 15 of 28
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CY7C1354C
CY7C1356C
Boundary Scan Exit Order (512K × 18)
Bit # 119-ball ID 165-ball ID
1K4 B6
2H4 B7
3M4 A7
4F4 B8
5B4 A8
6G4 A9
7C3B10
8B3A10
9T2A11
10 Not Bonded
(Preset to 0)
11 Not Bonded
(Preset to 0)
12 Not Bonded
(Preset to 0)
13 D6 C11
14 E7 D11
15 F6 E11
16 G7 F11
17 H6 G11
18 T7 H11
19 K7 J10
20 L6 K10
21 N6 L10
22 P7 M10
23 Not Bonded
(Preset to 0)
24 Not Bonded
(Preset to 0)
25 Not Bonded
(Preset to 0)
26 Not Bonded
(Preset to 0)
27 Not Bonded
(Preset to 0)
28 T6 R11
29 A3 R10
30 C5 P10
31 B5 R9
32 A5 P9
33 C6 R8
34 A6 P8
35 P4 R6
36 N4 P6
37 R6 R4
38 T5 P4
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Boundary Scan Exit Order (512K × 18) (continued)
Bit # 119-ball ID 165-ball ID
39 T3 R3
40 R2 P3
41 R3 R1
42 Not Bonded
(Preset to 0)
43 Not Bonded
(Preset to 0)
44 Not Bonded
(Preset to 0)
45 Not Bonded
(Preset to 0)
46 P2 N1
47 N1 M1
48 M2 L1
49 L1 K1
50 K2 J1
51 Not Bonded
(Preset to 1)
52 H1 G2
53 G2 F2
54 E2 E2
55 D1 D2
56 Not Bonded
(Preset to 0)
57 Not Bonded
(Preset to 0)
58 Not Bonded
(Preset to 0)
59 Not Bonded
(Preset to 0)
60 Not Bonded
(Preset to 0)
61 C2 B2
62 A2 A2
63 E4 A3
64 B2 B3
65 Not Bonded
(Preset to 0
66 G3 Not Bonded
67 Not Bonded
(Preset to 0
68 L5 B5
69 B6 A6
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 1)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
(Preset to 0)
A4
Document #: 38-05538 Rev. *G Page 16 of 28
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CY7C1354C
CY7C1356C
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
Supply Voltage on V
DC to Outputs in Tri-State...................–0.5V to V
Relative to GND........–0.5V to +4.6V
DD
Relative to GND......–0.5V to +V
DDQ
DDQ
DD
+ 0.5V
Electrical Characteristics Over the Operating Range
DC Input Voltage...................................–0.5V to VDD + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%
Industrial –40°C to +85°C
[14, 15]
Ambient
Temperature V
DD
V
to V
DDQ
Parameter Description Test Conditions Min. Max. Unit
V
V
DD
DDQ
Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage for 3.3V I/O 3.135 V
DD
for 2.5V I/O 2.375 2.625 V
V
OH
V
OL
Output HIGH Voltage for 3.3V I/O, I
for 2.5V I/O, I
= −4.0 mA 2.4 V
OH
= −1.0 mA 2.0 V
OH
Output LOW Voltage for 3.3V I/O, IOL= 8.0 mA 0.4 V
for 2.5V I/O, IOL= 1.0 mA 0.4 V
V
IH
V
IL
Input HIGH Voltage for 3.3V I/O 2.0 VDD + 0.3V V
Input LOW Voltage
for 2.5V I/O 1.7 V
[16]
for 3.3V I/O –0.3 0.8 V
+ 0.3V V
DD
for 2.5V I/O –0.3 0.7 V
I
X
I
OZ
I
DD
Input Leakage Current
GND ≤ VI ≤ V
except ZZ and MODE
Input Current of MODE Input = V
Input = V
Input Current of ZZ Input = V
Input = V
SS
DD
SS
DD
Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply V
DD
f = f
= Max., I
= 1/t
MAX
DDQ
–5 5 µA
–30 µA
–5 µA
Output Disabled –5 5 µA
DDQ,
OUT
CYC
= 0 mA,
4-ns cycle, 250 MHz 250 mA
5-ns cycle, 200 MHz 220 mA
5 µA
30 µA
6-ns cycle, 166 MHz 180 mA
I
SB1
I
SB2
I
SB3
I
SB4
Notes:
14.Overshoot: V
15.T
Power-up
16.Tested initially and af ter any design or process changes that may affect these parameters.
Automatic CE
Power-down
Current—TTL Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—TTL Inputs
(AC) < V
IH
: Assumes a linear ramp from 0V to V
+1.5V (Pulse width less than t
DD
Max. VDD, Device Deselected,
V
≥ VIH or VIN ≤ VIL, f = f
IN
= 1/t
CYC
Max. VDD, Device Deselected,
V
≤ 0.3V or VIN > V
IN
f = 0
DDQ
− 0.3V,
Max. VDD, Device Deselected,
≤ 0.3V or VIN > V
V
IN
f = f
MAX
= 1/t
CYC
DDQ
− 0.3V,
Max. VDD, Device Deselected,
V
≥ VIH or VIN ≤ VIL, f = 0
IN
/2), undershoot: VIL(AC)> –2V (Pulse width less than t
CYC
(min.) within 200 ms. During this time VIH < VDD and V
DD
4-ns cycle, 250 MHz 130 mA
MAX
5-ns cycle, 200 MHz 120 mA
6-ns cycle, 166 MHz 110 mA
All speed grades 40 mA
4-ns cycle, 250 MHz 120 mA
5-ns cycle, 200 MHz 110 mA
6-ns cycle, 166 MHz 100 mA
All speed grades 40 mA
DDQ
< VDD.
CYC
/2).
DD
V
Document #: 38-05538 Rev. *G Page 17 of 28
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CY7C1354C
CY7C1356C
Capacitance
[16]
Parameter Des cription Test Conditions
C
Input Capacitance TA = 25°C, f = 1 MHz,
IN
C
CLK
C
I/O
Clock Input Capacitance 5 5 5 pF
Input/Output Capacitance 5 7 7 pF
Thermal Resistance
[16]
V
DD
= 3.3V V
DDQ
= 2.5V
Parameter Des cription Test Conditions
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test cond itions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA/JESD51.
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
= 50Ω
Z
0
2.5V I/O Test Load
OUTPUT
= 50Ω
Z
0
3.3V
OUTPUT
= 50Ω
R
L
VT= 1.5V
(a) (b)
2.5V
OUTPUT
= 50Ω
R
L
= 1.25V
V
T
(a) (b)
5pF
INCLUDING
JIG AND
SCOPE
5pF
INCLUDING
JIG AND
SCOPE
R = 317Ω
R = 1667Ω
100 TQFP
Max.
R = 351Ω
R = 1538Ω
119 BGA
Max.
165 FBGA
Max. Unit
555pF
100 TQFP
Max.
119 BGA
Max.
165 FBGA
Max. Unit
29.41 34.1 16.8 °C/W
6.13 14.0 3.0 °C/W
V
DDQ
GND
≤ 1 ns
ALL INPUT PULSES
10%
90%
90%
10%
≤ 1 ns
(c)
V
GND
DDQ
≤ 1 ns
ALL INPUT PULSES
10%
90%
90%
10%
≤ 1 ns
(c)
Document #: 38-05538 Rev. *G Page 18 of 28
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CY7C1354C
CY7C1356C
Switching Characteristics Over the Operating Range
Parameter Description
[17]
t
Power
Clock
t
CYC
F
MAX
t
CH
t
CL
t
EOV
t
CLZ
Output Times
t
CO
t
EOV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Set-up Times
t
AS
t
DS
t
CENS
t
WES
t
ALS
t
CES
Hold Times
t
AH
t
DH
t
CENH
t
WEH
t
ALH
t
CEH
VCC (typical) to the First Access Read or Write 1 1 1 ms
Clock Cycle Time 4.0 5 6 ns
Maximum Operating Frequency 250 200 166 MHz
Clock HIGH 1.8 2.0 2.4 ns
Clock LOW 1.8 2.0 2.4 ns
OE LOW to Output Valid 2.8 3.2 3.5 ns
Clock to Low-Z
[20, 21, 22]
Data Output Valid after CLK Rise 2.8 3.2 3.5 ns
OE LOW to Output Valid 2.8 3.2 3.5 ns
Data Output Hold after CLK Rise 1.25 1.5 1.5 ns
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
[20, 21, 22]
[20, 21, 22]
[20, 21, 22]
[20, 21, 22]
Address Set-up before CLK Rise 1.4 1.5 1.5 ns
Data Input Set-up before CLK Rise 1.4 1.5 1.5 ns
CEN Set-up before CLK Rise 1.4 1.5 1.5 ns
WE, BWx Set-up before CLK Rise
ADV/LD Set-up before CLK Rise 1.4 1.5 1.5 ns
Chip Select Set-up 1.4 1.5 1.5 ns
Address Hold after CLK Rise 0.4 0.5 0.5 ns
Data Input Hold after CLK Rise 0.4 0.5 0.5 ns
CEN Hold after CLK Rise 0.4 0.5 0.5 ns
WE, BWx Hold after CLK Rise 0.4 0.5 0.5 ns
ADV/LD Hold after CLK Rise 0.4 0.5 0.5 ns
Chip Select Hold after CLK Rise 0.4 0.5 0.5 ns
[18, 19]
–250 –200 –166
UnitMin. Max. Min. Max. Min. Max.
1.25 1.5 1.5 ns
1.25 2.8 1.5 3.2 1.5 3.5 ns
1.25 1.5 1.5 ns
2.8 3.2 3.5 ns
000ns
1.4 1.5 1.5 ns
Notes:
17.This part has a voltage regulator internally; t
initiated.
18.Timing reference level is 1.5V when V
19.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
, t
, t
20.t
CHZ
CLZ
21.At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect p arame ter s gua rant eed over worst case user co nditions. Device is de si gned
to achieve High-Z prior to Low-Z under the same system conditions.
22.This parameter is sampled and not 100% tested.
EOLZ
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
EOHZ
power
= 3.3V and is 1.25V when V
DDQ
EOHZ
Document #: 38-05538 Rev. *G Page 19 of 28
is the time power needs to be supplied above VDD minimum initially, befo re a Read or W rite ope ration can be
= 2.5V.
DDQ
is less than t
EOLZ
and t
is less than t
CHZ
to eliminate bus contention between SRAMs when sharing the same
CLZ
[+] Feedback
Switching Waveforms
123456789
10
A
CT
6)
t
CENS
t
CES
[23, 24, 25]
t
CENH
t
CEH
Read/Write Timing
CLK
CEN
CE
ADV/LD
WE
BW
X
CY7C1354C
CY7C1356C
t
CYC
t
t
CL
CH
DDRESS
Data
Out (DQ)
OE
A1 A2
t
t
AS
AH
WRITE
D(A1)
WRITE
D(A2)
A3
t
t
DS
DH
D(A1) D(A2) D(A5)Q(A4)Q(A3)
BURST
WRITE
D(A2+1)
READ
Q(A3)
A4
t
CO
t
D(A2+1)
READ
Q(A4)
CLZ
t
BURST
READ
Q(A4+1)
DOH
A5 A6 A7
t
OEV
Q(A4+1)
t
OEHZ
t
OELZ
WRITE
D(A5)
READ
Q(A6)
DON’T CARE UNDEFINED
Notes:
23.For this waveform ZZ is tied low.
24.When CE
25.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Inte rleaved). Burst operations are optional.
is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
t
CHZ
t
DOH
WRITE
D(A7)
Q(A
DESELE
Document #: 38-05538 Rev. *G Page 20 of 28
[+] Feedback
Switching Waveforms (continued)
45678910
123
NOP,STALL and DESELECT Cycles
CLK
CEN
CE
ADV/LD
WE
BW
X
[23, 24, 26]
CY7C1354C
CY7C1356C
ADDRESS
A1
A2
Data
In-Out (DQ)
READ
D(A1)
Note:
26.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN
Q(A2)
STALL NOP READ
A3 A4
D(A1) Q(A2) Q(A3)
READ
Q(A3)
A5
D(A4)
WRITE
D(A4)
STALLWRITE
DESELECT CONTINUE
Q(A5)
DON’T CARE UNDEFINED
being used to create a pause. A write is not performed during this cycle.
t
CHZ
Q(A5)
DESELECT
Document #: 38-05538 Rev. *G Page 21 of 28
[+] Feedback
Switching Waveforms (continued)
A
ZZ Mode Timing
[27, 28]
CY7C1354C
CY7C1356C
CLK
ZZ
I
SUPPLY
LL INPUTS
(except ZZ)
Outputs (Q)
27.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
28.I/Os are in High-Z when exiting ZZ sleep mode.
t
ZZ
t
ZZI
I
DDZZ
High-Z
DON’T CARE
t
ZZREC
t
RZZI
DESELECT or READ Only
Document #: 38-05538 Rev. *G Page 22 of 28
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CY7C1354C
CY7C1356C
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz) Ordering Code
166 CY7C1354C-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1356C-166AXC
CY7C1354C-166BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356C-166BGC
CY7C1354C-166BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1356C-166BGXC
CY7C1354C-166BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356C-166BZC
CY7C1354C-166BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1356C-166BZXC
CY7C1354C-166AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
CY7C1356C-166AXI
CY7C1354C-166BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356C-166BGI
CY7C1354C-166BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1356C-166BGXI
CY7C1354C-166BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356C-166BZI
CY7C1354C-166BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1356C-166BZXI
200 CY7C1354C-200AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1356C-200AXC
CY7C1354C-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356C-200BGC
CY7C1354C-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1356C-200BGXC
CY7C1354C-200BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356C-200BZC
CY7C1354C-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1356C-200BZXC
CY7C1354C-200AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
CY7C1356C-200AXI
CY7C1354C-200BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356C-200BGI
CY7C1354C-200BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1356C-200BGXI
CY7C1354C-200BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356C-200BZI
CY7C1354C-200BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1356C-200BZXI
visit www.cypress.com for actual products offered.
Package
Diagram Part and Package Type
Operating
Range
Document #: 38-05538 Rev. *G Page 23 of 28
[+] Feedback
CY7C1354C
CY7C1356C
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
250 CY7C1354C-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1356C-250AXC
CY7C1354C-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356C-250BGC
CY7C1354C-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1356C-250BGXC
CY7C1354C-250BZC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356C-250BZC
CY7C1354C-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1356C-250BZXC
CY7C1354C-250AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
CY7C1356C-250AXI
CY7C1354C-250BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356C-250BGI
CY7C1354C-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1356C-250BGXI
CY7C1354C-250BZI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356C-250BZI
CY7C1354C-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1356C-250BZXI
visit www.cypress.com for actual products offered.
Document #: 38-05538 Rev. *G Page 24 of 28
[+] Feedback
Package Diagrams
R 0.08 MIN.
0.20 MAX.
0.25
GAUGE PLANE
0°-7°
0.60±0.15
1.00 REF.
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
14.00±0.10
81
80
0.30±0.08
0.65
TYP.
51
STAND-OFF
0.05 MIN.
0.15 MAX.
12°±1°
(8X)
SEATING PLANE
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
20.00±0.10
22.00±0.20
100
1
30
31 50
0° MIN.
R 0.08 MIN.
0.20 MAX.
0.20 MIN.
A
DETAIL
CY7C1354C
CY7C1356C
1.40±0.05
0.20 MAX.
1.60 MAX.
0.10
51-85050-*B
SEE DETAIL
A
Document #: 38-05538 Rev. *G Page 25 of 28
[+] Feedback
Package Diagrams (continued)
A1 CORNER
2165437
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
Ø1.00(3X) REF.
1.27
19.50
20.32
22.00±0.20
10.16
CY7C1354C
CY7C1356C
Ø0.05 M C
Ø0.25MCAB
Ø0.75±0.15(119X)
2143657
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
0.70 REF.
12.00
30° TYP.
0.90±0.05
0.25 C
SEATING PLANE
C
0.56
2.40 MAX.
0.15 C
0.60±0.10
A
B
0.15(4X)
3.81
7.62
14.00±0.20
51-85115-*B
1.27
Document #: 38-05538 Rev. *G Page 26 of 28
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CY7C1354C
CY7C1356C
Package Diagrams (continued)
165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D
165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)
TOP VIEW
TOP VIEW
PIN 1 CORNER
PIN 1 CORNER
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
15.00±0.10
A
0.53±0.05
0.25 C
0.36
B
J
K
L
M
N
P
R
B
0.53±0.05
C
0.36
J
K
L
M
N
P
R
SEATING PLANE
C
13.00±0.10
13.00±0.10
SEATING PLANE
15.00±0.10
A
0.25 C
NoBL and No Bus Latency are trademarks of C ypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders
1110986754321
1110986754321
14.00
15.00±0.10
15.00±0.10
A
A
0.15(4X)
1.40 MAX.
0.15 C
0.15 C
1.40 MAX.
0.35±0.06
0.35±0.06
11
1.00
1.00
14.00
7.00
7.00
B
B
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
11
5.00
BOTTOM VIEW
5.00
10.00
13.00±0.10
BOTTOM VIEW
Ø0.05 M C
Ø0.05 M C
Ø0.25MCAB
-0.06
Ø0.25 M C A B
Ø0.50 (165X)
+0.14
Ø0.50 (165X)
10.00
13.00±0.10
PIN1CORNER
-0.06
2345678910
+0.14
1.00
1.00
PIN 1 CORNER
1
2345678910
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
N
N
P
P
R
R
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
51-85180-*A
51-85180-*A
Document #: 38-05538 Rev. *G Page 27 of 28
© Cypress Semiconductor Corporation, 2006. The information contained herein is su bj ect to ch an ge wi t hou t notice. Cypress Semiconductor Corporation assumes no responsibility for th e u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypre ss does not aut horize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1354C
CY7C1356C
Document History Page
Document Title: CY7C1354C/CY7C1356C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05538
REV. ECN No. Issue Date
** 242032 See ECN RKF New data sheet
*A 278130 See ECN RKF Changed Boundary Scan order to match the B Rev of these devices
*B 284431 See ECN VBL Changed ISB1 and ISB3 from DC Characteristic table as follows
*C 320834 See ECN PCI Changed 225 MHz to 250 MHz
*D 351895 See ECN PCI Changed I
*E 377095 See ECN PCI Modified test condition in note# 15 from V
*F 408298 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from
*G 501793 See ECN VKN Added the Maximum Rating for Supply Voltage on V
Orig. of
Change Description of Change
Changed TQFP pkg to Lead-free TQFP in Ordering Information section
Added comment of Lead-free BG and BZ packages availability
ISB1: 225 mA-> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA
ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA
Add BG and BZ pkg lead-free part numbers to ordering info section
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Unshaded frequencies of 250, 200, 166 MHz in AC/DC Tables and Selection
Guide
Changed Θ
6.13 °C/W respectively
Changed Θ
14.0 °C/W respectively
Changed Θ
3.0 °C/W respectively
Modified V
Added Lead-Free product information
and Θ
JA
and Θ
JA
and Θ
JA
OL, VOH
for TQFP Package from 25 and 9 °C/W to 29.41 and
JC
for BGA Package from 25 and 6 °C/W to 34.1 and
JC
for FBGA Package from 27 and 6 °C/W to 16.8 and
JC
test conditions
Updated Ordering Information Table
Changed from Preliminary to Final
from 35 to 40 mA
Updated Ordering Information Table
SB2
DDQ
< V
“3901 North First Street” to “198 Champion Court”
Changed three-state to tri-state.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in
the Electrical Characteristics Table.
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Changed t
AC Switching Characteristics table.
, t
from 25 ns to 20 ns and t
TH
TL
from 5 ns to 10 ns in TAP
TDOV
Updated the Ordering Information table.
DD to VDDQ
Relative to GND
DDQ
≤ V
DD
Document #: 38-05538 Rev. *G Page 28 of 28
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