t
tecture
CY7C1353G
A
B
4-Mbit (256K x 18) Flow-through SRAM
h NoBL™ Archi
wi
Features
• Supports up to 133-MHz bus operations with zero wait
states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the
need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 256K x 18 common IO architecture
• 2.5V/3.3V IO power supply (V
DDQ
)
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN
) pin to suspend operation
• Synchronous self timed writes
• Asynchronous Output Enable
• Available in Pb-free 100-Pin TQFP package
• Burst Capability — linear or interleaved burst order
• Low standby power
Logic Block Diagram
ADDRESS
REGISTER
A1
D1
A0
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
CLK
CEN
A0, A1, A
MODE
C
ADV/LD
BW
BW
WE
CE
A
B
Functional Description
[1]
The CY7C1353G is a 3.3V, 256K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN
) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW
conducted with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
) and a Write Enable (WE) input. All writes are
[A:B]
, CE2, CE3) and an
1
) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
A1'
Q1
A0'
Q0
BURST
LOGIC
O
U
T
P
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
G
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
DQs
DQP
DQP
E
OE
CE
1
CE
2
CE
3
ZZ
Note:
1.For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
READ LOGIC
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05515 Rev. *E Revised July 09, 2007
SLEEP
INPUT
REGISTER
E
[+] Feedback
CY7C1353G
Selection Guide
133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.0 ns
Maximum Operating Current 225 205 mA
Maximum CMOS Standby Current 40 40 mA
Pin Configuration
100-Pin TQFP Pinout
BYTE B
V
DDQ
V
DQ
DQ
V
V
DDQ
DQ
DQ
V
V
DQ
DQ
V
DDQ
V
DQ
DQ
DQP
V
V
DDQ
NC
NC
NC
SS
NC
NC
SS
NC
DD
NC
SS
SS
NC
SS
NC
NC
NC
NC
NC
BBWA
BW
CE3VDDV
9291908988
CY7C1353G
SS
CLKWECEN
OE
878685
ADV/LD
NC/9M
NC/18M
848382
A
A
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQP
DQ
DQ
V
SS
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SS
DQ
DQ
NC
NC
V
SS
V
DDQ
NC
NC
NC
A
A
A
A
A
BYTE A
A
A
A
A
A
100
1CE2
A
CE
99
98
9796959493
1
2
3
4
5
6
7
8
B
9
B
10
11
12
B
13
B
14
15
16
17
18
B
19
B
20
21
22
B
23
B
24
B
25
26
27
28
29
30
313233343536373839
A
MODE
Document #: 38-05515 Rev. *E Page 2 of 13
40
414243444546474849
A
A
A
A1
A0
NC/288M
NC/144M
SS
DD
V
V
NC/72M
A
NC/36M
A
A
A
50
A
A
A
[+] Feedback
CY7C1353G
Pin Definitions
Name IO Description
, A1, A Input-
A
0
BW
WE
[A:B]
Synchronous
Input-
Synchronous
Input-
Synchronous
ADV/LD Input-
Synchronous
CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
CE
CE
CE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
OE Input-
Asynchronous
CEN
Input-
Synchronous
ZZ Input-
Asynchronous
DQ
DQP
s
[A:B]
IO-
Synchronous
IO-
Synchronous
MODE Input
Strap P in
V
DD
V
DDQ
V
SS
NC,NC/9M,
Power Supply Power supply inputs to the core of the device.
IO Power
Supply
Ground Ground for the device.
– No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M, NC/288M,
NC/18M,
NC/36M
NC/72M,
NC/144M,
NC/288M,
Address Inputs used to select one of the 256K address locations. Sampled at the rising edge
of the CLK. A
are fed to the two-bit burst counter.
[1:0]
Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN
address can be loaded into the device for an access. After being deselected, ADV/LD
is asserted LOW) the internal burst counter is advanced. When LOW, a new
must be
driven LOW to load a new address.
is only recognized if CEN
is active LOW.
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
, and CE3 to select/deselect the device.
2
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
and CE2 to select/deselect the device.
CE
1
Output Enable, asynchronous input, Active LOW. Combined with the synchronous logic block
inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to
behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.
Clock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. While deasserting CEN
deselect the device, CEN
can be used to extend the previous cycle when required.
does not
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin
has an internal pull down.
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and
the internal control logic. When OE
and DQP
DQ
s
the data portion of a write sequence, during the first clock when emerging from a deselected state,
are placed in a tri-state condition. The outputs are automatically tri-stated during
[A:B]
and when the device is deselected, regardless of the state of OE
is asserted LOW, the pins can behave as outputs. When HIGH,
.
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During write
sequences, DQP
is controlled by BWx correspondingly.
[A:B]
MODE Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved
burst sequence.
Power supply for the IO circuitry.
are address expansion pins are not internally connected to the die.
Document #: 38-05515 Rev. *E Page 3 of 13
[+] Feedback
CY7C1353G
Functional Overview
The CY7C1353G is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN
). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (t
Accesses can be initiated by asserting all three Chip Enables
(CE
Enable (CEN
the address presented to the device is latched. The access
can either be a read or write operation, depending on the
status of the Write Enable (WE
conduct byte write operations.
Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self timed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipe lined.
ADV/LD must be driven LOW after the device has been
deselected to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE
clock of the read access, the output buffers are controlled by
OE
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output is tri-stated
immediately.
Burst Read Accesses
The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW to load a new address into the SRAM, as
described in the Single Read Access section. The sequence
of the burst counter is determined by the MODE input signal.
A LOW input on MODE selects a linear burst mode, a HIGH
selects an interleaved burst sequence. Both burst counters
use A0 and A1 in the burst sequence, and wraps around when
incremented sufficiently. A HIGH input on ADV/LD
the internal burst counter regardless of the state of chip enable
inputs or WE
) is 6.5 ns (133-MHz device).
CDV
, CE2, CE3) active at the rising edge of the clock. If Clock
1
) is active LOW and ADV/LD is asserted LOW,
). BW
can be used to
[A:B]
). All
, CE2, CE3) and an
1
) simplify depth expansion.
is asserted LOW, (2) CE1, CE2,
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and 4) ADV/LD is asserted
is active LOW. After the first
and the internal control logic. OE must be driven LOW in
increments
. WE is latched at the beginning of a burst cycle.
Therefore, the type of access (Read or Write) is maintained
throughout the burst sequence.
Single Write Accesses
Write access are initiated when these conditions are satisfied
at clock rise:
is asserted LOW
•CEN
•CE
, CE2, and CE3 are ALL asserted active
1
• The write signal WE is asserted LOW.
The address presented to the address bus is loaded into the
Address Register. The write signals are latched into the
Control Logic block. The data lines are automatically tri-stated
regardless of the state of the OE
external logic to present the data on DQs and DQP
On the next clock rise the data presented to DQs and DQP
(or a subset for byte write operations, see truth table for
input signal. This allows the
.
[A:B]
[A:B]
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BW
signals. The CY7C1353G provides byte write
[A:B]
capability that is described in the truth table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input selectively writes to only the desired bytes. Bytes not
selected during a byte write operation remains unaltered. A
synchronous self timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included to greatly simplify Read/Modify/Write sequences,
which can be reduced to simple byte write operations.
Because the CY7C1353G is a common IO device, data must
not be driven into the device while the outputs are active. The
Output Enable (OE
presenting data to the DQs and DQP
tri-states the output drivers. As a safety precaution, DQs and
DQP
a write cycle, regardless of the state of OE
.are automatically tri-stated during the data portion of
[A:B]
) can be deasserted HIGH before
inputs. Doing so
[A:B]
.
Burst Write Accesses
The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD
must be driven LOW to load the initial address, as
described in the Single Write Access section. When ADV/LD
is driven HIGH on the subsequent clock rise, the Chip Enables
(CE
, CE2, and CE3) and WE inputs are ignored and the burst
1
counter is incremented. The correct BW
driven in each cycle of the burst write, to write the correct bytes
inputs must be
[A:B]
of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
, CE2, and CE3, must remain inactive
1
after the ZZ input returns LOW.
ZZREC
Document #: 38-05515 Rev. *E Page 4 of 13
[+] Feedback
CY7C1353G
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
Second
Address
A1, A0
DD
)
Third
Address
A1, A0
Fourth
Address
A1, A0
11 10 01 00
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
Deselect Cycle None H X X L L X X X L L->H Tri-State
Deselect Cycle None X X H L L X X X L L->H Tri-State
Deselect Cycle None X L X L L X X X L L->H Tri-State
Continue Deselect Cycle None X X X L H X X X L L->H Tri-State
READ Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q)
READ Cycle (Continue Burst) Next X X X L H X X L L L->H Data Out (Q)
NOP/DUMMY READ (Begin
Burst)
DUMMY READ (Continue Burst) Next X X X L H X X H L L->H Tri-State
WRITE Cycle (Begin Burst) External L H L L L L L X L L->H Data In (D)
WRITE Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D)
NOP/WRITE ABORT (Begin
Burst)
WRITE ABORT (Continue Burst) Next X X X L H X H X L L->H Tri-State
IGNORE CLOCK EDGE (Stall) Current X X X L X X X X H L->H –
SLEEP MODE None X X X H X X X X X X Tri-State
Sleep mode standby current ZZ > VDD − 0.2V 40 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
ZZ inactive to exit sleep current This parameter is sampled 0 ns
[2, 3, 4, 5, 6, 7, 8]
Address
Operation
Used CE1CE2CE3ZZ ADV/LD WE BWXOE CEN CLK DQ
External L H L L L H X H L L->H Tri-State
None L H L L L L H X L L->H Tri-State
CYC
CYC
ns
ns
ns
Notes:
2. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. BW
selects are asserted, see truth table for details.
3. Write is defined by BW
4. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
5. The DQs and DQP
6. CEN
= H, inserts wait states.
7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
8. OE
is inactive or when the device is deselected, and DQs and DQP
, and WE. See truth table for Read/Write.
X
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
[A:B]
Document #: 38-05515 Rev. *E Page 5 of 13
x = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
.
= data when OE is active.
[A:B]
= tri-state when OE
[A:B]
[+] Feedback
CY7C1353G
Partial Truth Table for Read/Write
Function WE BW
[2, 3, 9]
A
BW
B
Read HXX
Write – No bytes written L H H
Write Byte A – (DQ
Write Byte B – (DQ
and DQPA)LLH
A
and DQPB)LHL
B
Write All Bytes L L L
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write is based on which byte write is active.
Document #: 38-05515 Rev. *E Page 6 of 13
[+] Feedback
CY7C1353G
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
Supply Voltage on V
Relative to GND........ –0.5V to +4.6V
DD
Relative to GND ...... –0.5V to +V
DDQ
DD
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to V
DDQ
+ 0.5V
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min Max Unit
V
V
V
V
V
V
I
X
I
OZ
I
DD
I
SB1
I
SB2
I
SB3
I
SB4
DD
DDQ
OH
OL
IH
IL
Power Supply Voltage 3.135 3.6 V
IO Supply Voltage 2.375 V
Output HIGH Voltage for 3.3V IO, IOH = –4.0 mA 2.4 V
for 2.5V IO, I
= –1.0 mA 2.0 V
OH
Output LOW Voltage for 3.3V IO, IOH = 8.0 mA 0.4 V
for 2.5V IO, IOH = 1.0 mA 0.4 V
Input HIGH Voltage for 3.3V IO 2.0 VDD + 0.3V V
Input HIGH Voltage for 2.5V IO 1.7 V
Input LOW Voltage
Input LOW Voltage
Input Leakage Current
except ZZ and MODE
Input Current of MODE Input = V
Input Current of ZZ Input = V
Output Leakage Current GND ≤ VI ≤ V
V
Operating Supply
DD
Current
Automatic CE Power down
Current—TTL Inputs
Automatic CE Power down
Current—CMOS Inputs
Automatic CE Power down
Current—CMOS Inputs
Automatic CE Power down
Current—TTL Inputs
[10]
[10]
for 3.3V IO –0.3 0.8 V
for 2.5V IO –0.3 0.7 V
GND ≤ VI ≤ V
Input = V
Input = V
V
= Max., I
DD
f = f
MAX
V
= Max, Device Deselected,
DD
≥ VIH or VIN ≤ VIL, f = f
V
IN
inputs switching
V
= Max, Device Deselected,
DD
V
≥ VDD – 0.3V or VIN ≤ 0.3V,
IN
f = 0, inputs static
V
= Max, Device Deselected,
DD
V
≥ V
IN
f = f
MAX
V
= Max, Device Deselected,
DD
V
≥ V
IN
f = 0, inputs static
DDQ
SS
DD
SS
DD
DDQ
OUT
= 1/t
CYC
– 0.3V or VIN ≤ 0.3V,
DDQ
, inputs switching
– 0.3V or VIN ≤ 0.3V,
DD
DC Input Voltage ...................................–0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current.................................................... > 200 mA
Operating Range
Range
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
Industrial −40°C to +85°C
[10,11]
, Output Disabled –5 5 µA
= 0 mA,
7.5-ns cycle, 133 MHz 225 mA
10-ns cycle, 100 MHz 205 mA
7.5-ns cycle, 133 MHz 90 mA
,
MAX
10-ns cycle, 100 MHz 80 mA
All speeds 40 mA
7.5-ns cycle, 133 MHz 75 mA
10-ns cycle, 100 MHz 65 mA
All speeds 45 mA
Ambient
Temperature (TA) V
−55µA
–30 µA
–5 µA
DD
DD
+ 0.3V V
DD
5 µA
30 µA
V
to V
DDQ
DD
V
Notes:
10. Overshoot: V
11. T
Power-up
(AC) < V
IH
: Assumes a linear ramp from 0V to V
+1.5V (Pulse width less than t
DD
Document #: 38-05515 Rev. *E Page 7 of 13
/2), undershoot: VIL(AC)> –2V (Pulse width less than t
CYC
(min.) within 200 ms. During this time V
DD
< V
and V
IH
DD
DDQ
< VDD.
CYC
[+] Feedback
/2).
CY7C1353G
Capacitance
[12]
Parameter Description Test Conditions
C
IN
C
CLOCK
C
IO
Thermal Resistance
[12]
Input Capacitance TA = 25°C, f = 1 MHz,
Clock Input Capacitance 5 pF
IO Capacitance 5 pF
Parameters Description Test Conditions
Θ
JA
Θ
JC
.
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
according to EIA/JESD51.
AC Test Loads and Waveforms
3.3V IO Test Load
OUTPUT
= 50Ω
Z
0
R
L
VT= 1.5V
(a) (b)
2.5V IO Test Load
OUTPUT
= 50Ω
Z
0
= 1.25V
V
T
R
L
(a) (b)
Note:
12.Tested initially and after any design or process changes that may affect these parameters.
3.3V
OUTPUT
= 50Ω
5pF
INCLUDING
JIG AND
SCOPE
2.5V
OUTPUT
= 50Ω
5pF
INCLUDING
JIG AND
SCOPE
R = 317Ω
R = 351Ω
R = 1667Ω
R =1538Ω
GND
V
DDQ
GND
V
V
DD
V
DDQ
DDQ
≤ 1ns
≤ 1ns
= 3.3V
=3.3V
10%
10%
100 TQFP
Max Unit
5pF
100 TQFP
Package Unit
30.32 °C/W
6.85 °C/W
ALL INPUT PULSES
90%
(c)
ALL INPUT PULSES
90%
(c)
90%
10%
≤ 1ns
90%
10%
≤ 1ns
Document #: 38-05515 Rev. *E Page 8 of 13
[+] Feedback
CY7C1353G
Switching Characteristics Over the Operating Range
Parameter Description
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CDV
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Setup Times
t
AS
t
ALS
t
WES
t
CENS
t
DS
t
CES
Hold Times
t
AH
t
ALH
t
WEH
t
CENH
t
DH
t
CEH
VDD(Typical) to the first Access
Clock Cycle Time 7.5 10 ns
Clock HIGH 2.5 4.0 ns
Clock LOW 2.5 4.0 ns
Data Output Valid After CLK Rise 6.5 8.0 ns
Data Output Hold After CLK Rise 2.0 2.0 ns
Clock to Low-Z
Clock to High-Z
[14, 15, 16]
[14, 15, 16]
OE LOW to Output Valid 3.5 3.5 ns
OE LOW to Output Low-Z
OE HIGH to Output High-Z
Address Setup Before CLK Rise 1.5 2.0 ns
ADV/LD Setup Before CLK Rise 1.5 2.0 ns
WE, BWX Setup Before CLK Rise 1.5 2.0 ns
CEN Setup Before CLK Rise 1.5 2.0 ns
Data Input Setup Before CLK Rise 1.5 2.0 ns
Chip Enable Setup Before CLK Rise 1.5 2.0 ns
Address Hold After CLK Rise 0.5 0.5 ns
ADV/LD Hold after CLK Rise 0.5 0.5 ns
WE, BWX Hold After CLK Rise 0.5 0.5 ns
CEN Hold After CLK Rise 0.5 0.5 ns
Data Input Hold After CLK Rise 0.5 0.5 ns
Chip Enable Hold After CLK Rise 0.5 0.5 ns
[13]
[14, 15, 16]
[14, 15, 16]
[17, 18]
–133 –100
UnitMin Max Min Max
11ms
00ns
3.5 3.5 ns
00ns
3.5 3.5 ns
Notes:
13.This part has a voltage regulator internally; t
can be initiated.
, t
14.t
CHZ
15.At any voltage and temperature, t
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve tri-state prior to Low-Z under the same system conditions.
16.This parameter is sampled and not 100% tested.
17.Timing reference level is 1.5V when V
18.Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
CLZ,tOELZ
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
OEHZ
POWER
is less than t
=3.3V and is 1.25V when V
DDQ
Document #: 38-05515 Rev. *E Page 9 of 13
is the time that the power needs to be supplied above V
and t
OELZ
is less than t
CHZ
DDQ
to eliminate bus contention between SRAMs when sharing the same data
CLZ
=2.5V.
minimum initially before a read or write operation
DD
[+] Feedback
Switching Waveforms
123456789
10
C
Read/Write Waveforms
[19, 20, 21]
CLK
t
t
CENS
CENH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW[A:B]
t
CH
t
CYC
CY7C1353G
t
CL
ADDRESS
A1 A2
t
t
AH
AS
A3
t
CDV
t
CLZ
DQ
D(A1) D(A2) Q(A4)Q(A3)
t
t
DH
DS
D(A2+1)
OE
OMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
A4
t
DOH
READ
Q(A4)
t
OEHZ
Q(A4+1)
BURST
READ
A5 A6 A7
t
OEV
Q(A4+1)
t
OELZ
WRITE
t
t
D(A5)
CHZ
D(A5)
DOH
READ
Q(A6)
WRITE
D(A7)
DON’T CARE UNDEFINED
Notes:
For this waveform ZZ is tied low.
19.
20.When CE
21.Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional.
is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
D(A7)Q(A6)
DESELECT
Document #: 38-05515 Rev. *E Page 10 of 13
[+] Feedback
Switching Waveforms
45678910
123
C
A
NOP, STALL and DESELECT Cycles
CLK
CEN
CE
ADV/LD
WE
BW
[A:B]
CY7C1353G
[19, 20, 22]
ADDRESS
A1 A2
DQ
OMMAND
D(A1)
ZZ Mode Timing
[23,24]
CLK
READ
Q(A2)
ZZ
I
SUPPLY
LL INPUTS
(except ZZ)
A3 A4
Q(A2)D(A1) Q(A3)
STALL NOP READ
READ
Q(A3)
WRITE
D(A4)
STALLWRITE
D(A4)
A5
Q(A5)
t
CHZ
Q(A5)
t
DOH
DESELECT CONTINUE
DON’T CARE UNDEFINED
t
ZZ
t
ZZI
I
DDZZ
t
ZZREC
t
RZZI
DESELECT or READ Only
DESELECT
Outputs (Q)
Notes:
22.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN
23.Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
24.DQs are in high-Z when exiting ZZ sleep mode
Document #: 38-05515 Rev. *E Page 11 of 13
High-Z
DON’T CARE
being used to create a pause. A write is not performed during this cycle.
[+] Feedback
CY7C1353G
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz) Ordering Code
133 CY7C1353G-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial
CY7C1353G-133AXI lndustrial
100 CY7C1353G-100AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial
CY7C1353G-100AXI lndustrial
Package Diagrams
Package
Diagram Part and Package Type
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
14.00±0.10
100
1
81
80
0.30±0.08
Operating
Range
1.40±0.05
20.00±0.10
22.00±0.20
GAUGE PLANE
R 0.08 MIN.
0.20 MAX.
0.25
0°-7°
0.60±0.15
1.00 REF.
30
31 50
0° MIN.
R 0.08 MIN.
0.20 MAX.
0.20 MIN.
A
DETAIL
0.65
TYP.
51
STAND-OFF
0.05 MIN.
0.15 MAX.
SEATING PLANE
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
12°±1°
(8X)
SEE DETAIL
0.20 MAX.
1.60 MAX.
0.10
51-85050-*B
ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor.
All product and company names mentioned in this document are the trademarks of their respective holders.
A
Document #: 38-05515 Rev. *E Page 12 of 13
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
Document History Page
Document Title: CY7C1353G 4-Mbit (256K x 18) Flow-through SRAM with NoBL™ Architecture
Document Number: 38-05515
REV. ECN NO. Issue Date
** 224363 See ECN RKF New data sheet
*A 288431 See ECN VBL Deleted 66 MHz
*B 333626 See ECN SYT Removed 117-MHz speed bin
*C 418633 See ECN RXU Converted from Preliminary to Final
*D 480124 See ECN VKN Added the Maximum Rating for Supply Voltage on V
*E 1274724 See ECN VKN/AESA Corrected typo in the Ordering Information table
Orig. of
Change Description of Change
Changed TQFP package in Ordering Information section to Pb-free TQFP
Modified Address Expansion balls in the pinouts for 100 TQFP Packages
according to JEDEC standards and updated the Pin Definitions accordingly
Modified V
Replaced ‘Snooze’ with ‘Sleep’
OL, VOH
Replaced TBD’s for Θ
Resistance table
test conditions
and ΘJC to their respective values on the Thermal
JA
Updated the Ordering Information by shading and unshading MPNs
according to availability
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Modified test condition from V
Modified test condition from V
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
< V
IH
< VDD to V
DDQ
DD to VIH
< V
DDQ
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
Updated the Ordering Information table.
CY7C1353G
DD
< V
DD
Relative to GND.
DDQ
Document #: 38-05515 Rev. *E Page 13 of 13
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