Cypress Semiconductor CY7C1353-66AC, CY7C1353-50AC, CY7C1353-40AC Datasheet

1

353

CY7C1353

256Kx18 Flow-Through SRAM with NoBL™ Architecture

Features

Pin compatible and fu ncti onally equivalent to ZBT

•

devices MCM63Z819 and MT55L256L18F

• Supports 66-MHz bus operations with zero wait states
—Data is transferred on every clock

• Internally self-timed output b uffer control to eliminate

the need to use OE

• Registered inputs for Flow-Through operation

• Byte Write capability

• 256K x 18 common I/O architecture

• Single 3.3V power supply

• Fas t clock-to-o u tp u t times
—11.0 ns (for 66-MHz device)
—12. 0 ns (for 50-MHz device)
—14.0 ns (for 40-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchr onous self-timed writes

• Asynchr onous Output Enable

• JEDEC-standard 100 TQFP package

• Burst Capabili ty—linear or inte rleaved bur st order

• Low standby power

Logic Block Diagram

CLK

ADV/LD

[17:0]

CEN

CE
CE

CE
WE

[1:0]

18

CONTROL

1

2
3

and WRI TE

LOGIC

A

BWS

Mode

Functional Description

The CY7C1353 is a 3.3V 256K by 18 Synchronous­Flow-Through Burst SRAM designed specifically to support
unlimited true b ac k-to- back Read /Write operat ions wi thout t he
insertion of wait states. The CY7C1353 is equipped with the
advanced No Bus Latency (NoBL) logic required to enable
consecutiv e Read/Write operati ons with data being transf erred
on every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems
that require frequent Write -Read transition s.The CY7C1353 is
pin/functional ly compati ble t o ZBT SRAMs MCM63Z819 and
MT55L256L18F.

All synchronous input s pass through i nput regist er s controll ed
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN
pends operation and extends the previous clock cycle. Maxi­mum access delay from the clock rise is 9.0 ns (66-MHz de­vice).

Write operations are controlled by the four Byte Write Select
(BWS

) and a Write Enable (WE) input. All writes are con-

[1:0]

ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE

asynchronous Output Enable (OE
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.

D

Data-In REG.

CE

Q

18

256KX18

MEMORY

18

ARRAY

) signal, which when deasserted sus-

, CE2, CE3) and an

1

) provide for easy bank se-

18

18

DQ

[15:0]

DP

[1:0]

OE

Selection Guide

7C1353-66 7C1353-50 7C1353-40

Maximum Access Time (ns) 11 12.0 14.0
Maximum Operati ng Current (mA) Commercial 250 mA 200 mA 175 mA
Maximum CMOS Standby Curr ent (mA) Commercial 5 mA 5 mA 5 mA
NoBL is a trademark of Cypress Semiconductor Corporation .

ZBT is a trademark of Integrated Device Technology.

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 3, 1999

Pin Configuration

CY7C1353

100-Pin TQFP

V

DQ
DQ

V
DQ
DQ

DQ
DQ
V

DQ
DQ

V

NC
NC
NC

DDQ

V

SS

NC
NC

V

SS

DDQ

V

SS

V

DD

V

DD

V

SS

DDQ

V

SS

DP

NC

V

SS

DDQ

NC
NC
NC

NC

95

1

BWS

BWS0CE3VDDV

94

93

CY7C1353

92

91

90

SS

89

CLK

WE

CEN

88

87

OE

86

ADV/LD

85

NC

84

NC

83

82

A

81
80
79

78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A

17

NC
NC
V

DDQ

V

SS

NC
DP
DQ
DQ
V

SS

V

DDQ

DQ
DQ
V

SS

VSS
V

DD

VSS
DQ
DQ

V

DDQ

V

SS

DQ
DQ
NC
NC
V

SS

V

DDQ

NC
NC
NC

0
7
6

5
4

3
2

1
0

8A9

1CE2

A6

A7

CE

100

99

98

97

NC

96

1
2
3
4
5
6
7
8

8

9

9

10
11
12

10

13

11

14
15
16
17
18

12

19

13

20
21
22

14

23

15

24

1

25
26
27
28
29
30

31

32

33

34

A5A4A3A2A1A

MODE

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

0

DNU

DNU

SS

DD

V

V

DNU

DNU

10

A11A12A13A

A

14

16

15

A

A

2

CY7C1353

Pin Definitions

Pin Number Name I/O Description

80, 50−44,
81−82, 99–
100, 32−37

94, 93

88

85

89 CLK Input-Clock Clock Input. Used t o capt ure all synchr ono us inp uts to the device . CLK is qual ifi ed

98

97 CE

92

86

87

23−22,
19−18,
13−12, 9−8,
73−72,
69−68,
63−62, 59−58

24, 74 DP

31 Mode Input

15, 16, 41, 65, 91V

4, 11, 20, 27,
54, 61, 70, 77

5, 10, 14, 17,
21, 26, 40, 55,
60, 64,
66−67, 71,
76, 90

A

[17:0]

BWS

[1:0]

WE

AD V/LD

CE

1

2

CE

3

OE

CEN

DQ

[15:0]

[1:0]

DD

V

DDQ

V

SS

Input­Synchronous

Input­Synchronous

Input­Synchronous

Input­Synchronous

Address Inputs used to select one of the 262,144 addr ess locations. Sampled a t
the rising edge of the CLK.

Byte Write Select Inputs, active LOW. Qualified wi th WE to conduct writes to the
SRAM. Sampled on the risi ng edge of CLK. BWS
control s D Q

and DP1. See Write Cycle Description Table for details.

[15:8]

controls DQ

0

and DP0, BWS1

[7:0]

Write Enable Input, activ e LOW . Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be ass erted LOW to i nitiate a write sequence.

Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN

is asserted LOW) the internal b urst counter is
advanc ed. When LOW , a new address can be loaded into the de vice f or an access.
After being deselected, ADV/LD

should be driven LOW in order to load a new

address.

Input­Synchronous

Input­Synchronous

Input­Synchronous

Input­Asynchronous

with CEN
Chip Enable 1 Inpu t, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE
Chip Enable 2 Inpu t, acti ve HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE
Chip Enable 3 Inpu t, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE
Output Enab le, active LO W . Combined with the synchro nous logi c bloc k insi de t he

device t o control the direction of t he I/O pins. When LO W , the I/O pins are al lowed

. CLK is only recogniz ed if CEN is active LOW.

, and CE3 to select/deselect the device.

2

and CE3 to select/desel ect the devi ce.

1

and CE2 to select/deselect the device.

to behav e as out puts . When de asserted HIGH, I/ O pins ar e three- state d, an d act
as input data pins. OE

is masked during the data portion of a write seq uence,
during the first clock wh en emerging fr om a deselec ted state, when the de vice has
been deselected.

Input­Synchronous

Clock Enable Input, acti ve LOW. When ass erted LOW the Clock signal i s recog­nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN

does not deselect the device, CEN can be used to extend the

prev ious cycle when required.

I/O­Synchronous

Bidirectiona l Data I/O Line s. As inputs, they f eed into an on- chip data regi ster that
is triggered by t he rising edge of CLK. As outp uts, they deliv e r the data containe d
in the memory location specified by A
read cycle. The direction of the pins is controlled by OE
logic. When OE
DQ

are placed in a three-state condition. The outputs are automatically

[15:0]

is asserted LOW, the pins can behave as outputs. When HIGH,

during the previous clock rise of the

[17:0]

and the internal control

three-stated d uring the data po rtion of a write sequence , during the fi rst clock when
emerging from a de sel ected st ate , and when t he device is des electe d, regar dless

I/O­Synchronous

of the state of OE
Bidirectional Data Parity I/O Li nes. Functionall y, these signals are identical to

DQ
by BWS

. During write sequences, DP0 is controlled by BWS0 and DP1 is controlled

[15:0]

.

1

.

Mode Input. Selec ts the burst order of the de vice. Tied HIGH sel ects the interleav ed

Strap pin

burst order. Pull ed LOW selects the linear burst order. MODE shou ld not change
states during operation. When left floating MODE will default HIGH, to an inter­leaved burst or d er.

Po wer Supply Power supply i nputs t o the cor e of t he dev ic e. Sh oul d be con nect ed to 3.3 V powe r

supply.

I/O Power

Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.

Supply
Ground Ground for the device. Should be connected to gro und of the system.

3

CY7C1353

Pin Definitions

(continued)

Pin Number Name I/O Description

1−3, 6−7, 25,

NC - No Connects. These pins are not connected to the internal device.
28−30,51−53,
56−57, 75,
78−79, 95−96

83, 84 NC - No Connects. Res erved for a ddress inputs f or depth e xpansion. Pin 83 wi ll be used

for 512K depth and pin 84 will be used for 1-Mb depth.

38, 39, 42, 43 DNU - Do Not Use Pins. These pins should be l eft floating or tied to VSS.

Introduction

must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Acces s section abov e.

Functional Overview

The CY7C1353 is a Synchronous Flow-Through Burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN

). If CEN is HIGH, the clock signal i s not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN
rise (t

) is 9.0 ns (66-MHz device).

CD V

. Maximum acce ss dela y f rom the clock

Accesses can be initiated by asserting all three Chip Enables
(CE

, CE2, CE3) active at the rising edge of the clock. If clock

1

enable (CEN

) is activ e LO W and AD V/LD is asserted LO W , th e
address presented to the device will be latched. The access
can either be a r ead or write operation, depending on the sta­tus of the Write Enabl e (WE

). BWS

can be used t o conduct

[1:0]

byte write operations.
Write operations are qualified by the Write Enable (WE

). All
writes are s implifi ed with on-chi p synchr onou s s elf-ti med writ e
circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE

, CE2, CE3) and an

1

) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD

should be driven LOW once the devic e has been de-

selected in order to load a ne w addres s f or t he nex t operat i on.

Single Read Accesses

A read access is initiated when the following conditions are
satisfi ed at cl ock rise: (1) CEN
and CE
signal WE

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and 4) ADV/LD is assert ed
LOW. The address present ed to t he ad dress i nputs ( A
latched into the Address Register and present ed to t he mem-

is asserted LOW, (2) CE1, CE2,

) is

[17:0]

ory core and control logic. The con trol logic determines that a
read access is in progress and allows the requested data to
propagate to the output bu ffer s. The da ta is a vail able wi thin 9. 0
ns (66-MHz device) provided OE

is active LOW. After the first
clock of the read access the output buffers are controlled by
OE

and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one o f the chip enab le s ignals, i ts output will be three-state d
immediately.

Burst Read Accesses

The CY7C1353 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD

The sequence o f the b urst coun ter is determined b y the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD
the state of chip enable inputs or WE

will increment t he internal b urs t counter regardl ess of

. WE is latched at the
beginning of a burst cycle. Theref ore , the ty pe of acces s (Read
or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are
satisfied at cl ock rise: (1) CEN
and CE
is asserted LOW. The address presented to A

are ALL asserted active, and (3) the write signal WE

3

into the Address Register. The write signals are latched into

is asserted LO W, (2) CE1, CE2,

is loaded

[17:0]

the Control Logic block. The data lines are automatically
three-stated r egardless of t he state of the OE
allows the external logic to present the data on DQ
DP

.

[1:0]

On the next clock rise the data presented to DQ
DP

(or a subset for byte write operations, see Write Cycle

[1:0]

Description table for details) inputs is latched into the device

input signal. This

and

[15:0]

and

[15:0]

and the write is complete. Additional accesses
(Read/Write/Deselect) can be initiated on this cycle.

The data written during the Write operation is controlled by
BWS
ity that is described in the Write Cycle Description Table. As­serting the Write Enable input (WE
Write Selec t (BWS
desired by tes. Bytes not selec ted during a byte write oper ation

signals. The CY7C1353 pro vides b y te write c apabil -

[1:0]

) with the selected Byte

) input will selec tively wr ite to on ly the

[1:0]

will remain unaltered. A synchronous self-timed write mecha­nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim­ple byte write opera ti ons.

Because the CY7C1353 is a common I/O device, data should
not be driven in to t he device whi le t he outputs are active. The
Output Enable (OE
ing data to the DQ
three-state t he output driv er s. As a sa f e ty pr ecauti on, DQ
and DP
tion of a write cycle, regardless of the state of OE

.are automat ical ly th ree-st ated d urin g the da ta por -

[1:0]

) can be deasserted HIGH before present-

[15:0]

and DP

inputs. Doing so will

[1:0]

[15:0]

.

Burst Write Accesses

The CY7C1353 ha s an On-Chip Burst Counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD

must be driven LOW in order to load the initial ad-

4