Cypress Semiconductor CY7C1352-143AC, CY7C1352-133AC, CY7C1352-100AC, CY7C1352-80AC Datasheet

CY7C1352

256K x18 Pipelined SRAM with NoBL™ Architecture

Features

• Pin compatible and functionally equivalent to ZBT™
devices MCM63Z818 and MT55L256L18P

• Supports 143-MHz b us opera tions with zer o wait states

—D ata is transferred on every clock

• Internally self-timed output buffer control to eliminate
the need to use OE

• Fully registered (inputs and outputs) for pipelined
operation

• Byte Write Capabi li ty

• 256K x 18 common I/O architecture

• Single 3.3V power supply

• Fast clock-to-out put times

—4.0 ns (for 143-MHz device)
—4.2 ns (for 133-MHz device)
—5.0 ns (for 100-MHz device)
—7.0 ns (for 80-MHz device)

• Clock Enable (CEN

• Synchronous self-timed writes

• Asynchronous output enable

• JEDEC-standard 100-pin TQFP package

• Burst Capabi li ty—linear or interleaved burst order

) pin to suspend operation

• Low standby power

Functional Description

The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1352 is equipped with t he a dvanc ed No
Bus Latency™ (NoBL™) logic requi red to enabl e consecutiv e
Read/Write operations with data being transferred on every
clock cycle. This feat ure dramatically improves the throughput
of the SRAM, especially in systems that require frequent
Read/Write transi tions. The CY7C1352 is pin/func tionally c om­patible to ZBT™ SRAMs MCM63Z819 and MT55L256L18P.

All synchronous input s pass through i nput regi ster s control led
by the rising edge of the clock. All data outputs pass through
output regi sters controlled by the rising edge of the clock. The
clock input is qualified by the Cl ock Enable (CEN
when deasserted suspends operation and extends the previ­ous clock cycle. Maximum access delay from the clock rise is

4.0 ns (143-MHz device).
Write operations are controlled by the four Byte Write Select

(BWS

) and a Write Enable (WE) input. All writes are con-

[1:0]

ducted with on-chip synchronous self-t imed write circuitry.
Three synchronous Chip Enables (CE

asynchronous Output Enable (OE

1

) provide for easy bank se­lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.

) signal , which

, CE2, CE3) and an

Logic Block Diagram

CLK

ADV/LD

A

[17:0]

CEN

CE
CE

CE

WE

BWS

[1:0]

Mode

OE

D

Data-In REG.

CE

Q

18

18

CONTROL

1

2
3

and WRIT E

LOGIC

18

256Kx18

MEMORY

ARRAY

.

18

18

OUTPUT

REGISTERS

and LOGIC

CLK

18

DQ

DP

[15:0]

[1:0]

Selection G uide

7C1352-143 7C1352-133 7C1352-100 7C1352-80

Maximum Access Time (ns) 4.0 4.2 5.0 7.0
Maximum Operating Curr ent (mA) Commercial 450 400 350 300
Maximum CMOS Standby Current (mA) Commercial 5 5 5 5

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 9, 1999

Pin Configuration

100-Pin TQFP

A6A7CE1CE2NCNCBWS1BWS0CE3VDDVSSCLKWECEN

OE

CY7C1352

9

NC

ADV/LD

NC

A8A

V

V
DQ
DQ
V

DQ
DQ
V

DQ
DQ

V

NC
NC
NC

DDQ

V

NC

NC
DQ
DQ

V

DDQ

DDQ

V
V
V

DDQ

V

DP

NC

V

DDQ

NC

NC

NC

SS

SS

DD
DD

SS

SS

SS

100999897969594939291908988878685848382
1
2
3
4
5
6
7

8
9

8
9
10
11

10
11

12
13

CY7C1352

14
15
16
17

12
13

18
19
20
21

14
15

1

22
23
24
25
26
27
28
29
30

81
80

79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A

17

NC
NC
V

DDQ

V

SS

NC
DP
DQ
DQ
V

SS

V

DDQ

DQ
DQ
V

SS

VDD
V

DD

VSS
DQ
DQ
V

DDQ

V

SS

DQ
DQ
NC
NC
V

SS

V

DDQ

NC
NC
NC

0

7
6

5
4

3
2

1
0

31323334353637383940414243444546474849

A5A4A3A2A1A

MODE

0

DNU

DNU

SS

DD

V

V

DNU

DNU

10

A11A12A13A

A

15

14

A

2

50

A

16

CY7C1352

Pin Definitions

Pin Number Name I/O Description

80, 50−44,
81−82, 99−
100, 32−37

94, 93 BWS

88 WE Input-

85 ADV/LD Input-

89 CLK Input-Clock Clock input . Used to captur e all synchronous i nputs to the de vice. CLK is qua lified

98 CE

97 CE

92 CE

86 OE Input-

87 CEN Input-

23−22, 19−18,
13−12, 9−8,
73−72, 69−68,
63−62, 59−58

24, 74 DP

31 MODE Input

15, 16, 41, 65,
66, 91

4, 11, 14, 20,
27, 54, 61, 70,
77

5, 10, 17, 21,
26, 40, 55, 60,
64, 67, 71, 76,
90

A

DQ

V

V

V

[17:0]

1

2

3

[15:0]

[1:0]

DD

DDQ

SS

[1:0]

Input-

Synchronous

Input-

Synchronous

Address Inputs used to sel ect one of the 262, 144 address locat ions. Sampl ed at
the rising edge of the CLK.

Byte Write Select Input s, ac tiv e LO W. Qualified with WE to conduc t writes to t he
SRAM. Sampled on the rising edge of CLK. BWS
BWS

controls DQ

1

and DP1. See Write Cycle Description table for deta il s.

[15:8]

controls DQ

0

[7:0]

Write Enable Input, acti ve LOW. Sampled on the rising edge of CLK if CEN is

Synchronous

active LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load i npu t used t o adva nce t he on-ch ip a ddress c ounter o r load a ne w

Synchronous

address. When HIGH (and CEN

is asserted LOW) the internal b urst counter is
advanced. When LOW, a new address can be loaded into the device for an ac­cess. After being deselected, ADV/LD

should be driven LOW in order to load a

new address.

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

with CEN
Chip Enable 1 Input acti ve LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE
Chip Enable 2 Input active HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE
Chip Enable 3 Input, act ive LOW. Sample d on the rising edge of CLK. Used in

conjunction with CE

. CLK is only recognized if CEN is acti ve LOW.

and CE3 to select/deselect the device.

2

and CE3 to select/deselect the device.

1

and CE2 to select/d eselect the device.

1

Output Enable, active LOW . Combined with the synchr onous logic block inside

Asynchronous

the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed t o behav e as out puts. When deasserted HIGH, I/O pins a re three-st ated,
and act as input data pins. OE

is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.

Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-

Synchronous

nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN

does not deselect the device, CEN can be used to ext end the

previous cycle when required.

I/O-

Synchronous

Bidirectional Data I/O lines . As inputs , they f eed into an on-chip data regi ster that
is triggered b y the rising ed ge of CLK. As outputs , they deliv er the dat a contained
in the memory location specified by A
read cycle. The direction of t he pins is controll ed by OE
logic. When OE
DQ
three-stated during the data portion of a write sequence, duri ng the first clock

are placed in a three-state condition. The outputs are automatically

[15:0]

is asserted LOW, the pins can behave as outpu ts. When HIGH,

during the prev ious clock rise of the

[16:0]

and the internal control

when emerging from a desele cted state, and when the device is deselec ted,

I/O-

Synchronous

regardless of the state of OE
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to

DQ
trolled by BWS

. During write sequences, DP0 is controlled by BWS0 and DP1 is con-

[15:0]

1

.

Mode input. Selects the burst order of the device. Tied HIGH selects the inter-

Strap pin

leaved burst or der. Pulled LOW selects the linear burst order. MODE should not
change states during oper ation. When left flo ating, MODE wi ll defa ult HIGH t o an
interleaved burst order.

Powe r Suppl y Pow er supply inputs t o the core of the de vice. Should be c onnected to 3.3V po wer

supply.

I/O Power

Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.

Supply

Ground Ground for the device. Should be connected to ground of the system.

and DP0,

3

CY7C1352

Pin Definitions

(continued)

Pin Number Name I/O Description

1−3, 6−7, 25,

NC - No Connects. These pins are not connected to the int ernal device.
28−30, 51−53,
56−57, 75,
78−79, 95−96

83, 84 NC - No Connects. Reserved for address inputs for depth expansion. Pin 83 is re-

served for 512K depth and pin 84 is reserved for 1-Mb depth devices.

38, 39, 42, 43 DNU - Do Not Use pins. These pins should be left floating or ti ed to VSS.

Introduction

Functional Overview

The CY7C1352 is a synchronous-pipelined Burst SRAM de­signed specifically to eliminate wait states during Write-Read
transitions. All synchronous inputs pass through input regis­ters contr olled by th e risin g edge of the c loc k. The cloc k signal
is qualifie d with t he Cloc k Enab l e input signal (CEN
HIGH, the clo c k signal is n ot reco gnize d and all i nternal states
are maintained. All synchronous operations are qualified with
CEN

. All data ou tput s pass th rough out put r egist ers contr olle d
by the rising edge of the clock. Maximum access delay from
the clock ris e (t

) is 4.0 ns (143-MHz device).

CO

Accesses can be initiated by asserting all three chip enables
(CE

, CE2, CE3) activ e at the rising edge of the clock. If Clock

1

Enable (CEN

) is active LOW and ADV/ LD is asserted LOW , the
address presented to the device will be latched. The access
can either be a read or write operation, depending on the sta­tus of the Write Enabl e (WE
byte write operat ions.

). BWS

can be used to conduct

[1:0]

Write operations are qualified by the Write Enable (WE
writes are simpl ifi ed wit h on- chi p synchr onou s self -tim ed write
circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE

, CE2, CE3) and an

1

) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD

should be driven LOW once the device has been de-

selected in order to load a ne w addr ess f or the ne x t operat ion.

Single Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and (4) ADV/ LD is asserted

is asserted LOW, (2) CE1, CE2,

LOW. The address presented to the address inputs (A
is latched into the Address Register and presented to the
memory core and control logic. The control logic determines
that a read access is in progress and allows the requested
data to propagate to the input of the output register. At the
rising edge of the next clock the requested data is allowed to
propagate through the output register and onto the data bus
within 4.0 ns (143-MHz device) provided OE
After the first clock of the read access the output buffers are
controlled by OE

and the internal control logic. OE must be
driven LOW in order for the device to drive out the requested
data. During the second clock, a subsequent operation
(Read/Write/ Deselect) c an be initia ted. Desel ecting th e devic e
is also pipelined. Therefore, when the SRAM is deselected at
clock rise by one of the chip enable signals, its output will
three-state follow ing the next clock rise.

). If CEN is

). All

0−A17

is active LOW.

Burst Read Accesses

The CY7C1352 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Acce ss section abov e.
The sequence of the burst coun ter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD
the state of chip enables inputs or WE

will increment th e internal burst counter regardless of

. WE is latched at the
beginning of a burst cycle. Theref ore , the type of acces s (Read
or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write accesses are initia ted when the following conditions are
satisfied at clock rise: (1) CEN
and CE

are ALL asserted active, and (3) the write si gnal WE

3

is asserted LOW. The address presented to A
into the Address Register. The write signals are latched into

is asserted LOW , (2) CE1, CE2,

0−A17

the C o ntrol Logi c block.
On the subsequent clock rise the data lines are automatically

three-stated r egardless of the s tate of the OE

input signal. This
allows the external logic to present the data on DQ
DP

. In addition, the address for the subsequent access

[1:0]

(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQ
DP

(or a subset for byte write operations, see Write Cycle

[1:0]

Description table for details) inputs is latched into the device
and the write is complete.

The data written during the Write operation is controlled by
BWS

)

signals. The CY7C1352 provides byte write capabi l-

[1:0]

ity that is described in the write cyc le description t able. Assert­ing the Write Enable input (WE
Select (BWS

) input will se lectiv el y write to onl y the des ired

[1:0]

) with the selected Byte Write

bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim­ple byte write operations.

Because the CY7C1352 is a common I/O device, data s hould
not be driven into the device while the outputs are active. The
Output Enable ( O E
ing data to the DQ
three-state the out put driver s . As a safe ty precau tion, DQ
and DP
tion of a write cycle, regardless of the state of OE

are automati cally three- stat ed during t he data por -

[1:0]

) can be deasserted HIGH before present -

[15:0]

and DP

inputs. Doing so will

[1:0]

is loaded

[15:0]

[15:0]

.

and

and

[15:0]

4

CY7C1352

Burst Write Accesses

The CY7C1352 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD

must be driven LOW in order to load the initial ad-

When ADV/LD
the chip enables (CE
nored and the burst counter is incremented. The correct
BWS

[1:0]

in order to write the correct bytes of data.

is driven HIGH on the subsequent clock rise,

, CE2, and CE3) and WE inputs are ig-

1

inputs must be driven i n each cyc le of the burs t write

dress, as described in the Single Write Access section abo ve.

Cycle Description Truth Table

Operation

Address

used CE CEN

[

1, 2, 3, 4, 5, 6

]

ADV/

LD/ WE BWS

CLK Comments

x

Deselected External 1 0 L X X L-H I/Os three-state f oll owing ne xt rec-

ognized clock.

Suspend - X 1 X X X L-H Clock ignored, all operations

suspended.
Begin Read External 0 0 0 1 X L-H Address latched.
Begin Write External 0 0 0 0 Valid L-H Address latche d, data presented

two valid clocks la ter.
Burst READ

Operation

Internal X 0 1 X X L-H Burst Read operation. Previous

access was a Read oper ation. Ad-

dresses incremented internally in

conjunction with the state of

MODE.
Burst WR IT E

Operation

Internal X 0 1 X Valid L-H Burst Write operation. Previous

access w as a W rite operat ion. Ad-

dresses incremented internally in

conjunction with the state of

MODE. Bytes written are deter-

mined by BWS

[1:0]

.

Interleave d B u rst S eq u en ce

First

Address

Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Write Cycle D escriptio n s

Second

Address

Third

Address

[1, 2]

Fourth

Address

Function WE BWS

Linear Burst Sequence

First

Address

Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Second

Address

Third

Address

1

Fourth

Address

BWS

0

Read 1XX
Write − No bytes written 0 1 1
Write Byte 0 − (DQ
Write Byte 1 − (DQ

and DP0)010

[7:0]

and DP1)001

[15:8]

Write All Bytes 0 0 0

Notes:

1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW, CE
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

2. Write is defined by WE and BWS

3. The DQ and DP pins are controlled by the current cycle and the OE signal.

=1 inserts wait states.

4. CEN

5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.

6. OE assumed LOW.

. See Write Cycle Description table for details.

[1:0]

stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx =

5

CY7C1352

Maximum Ratings

(Abov e which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .....................................−65°C to +150°C

Ambient Temperature with

Curre n t in to Out p ut s (L OW )............... .......................... 2 0 mA

Static Discharge Voltage ............. .. ............ ............... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current............. ....................................... >200 mA

Operating Range

Po wer Applied..................................................−55°C to +12 5°C

Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V

DC Voltage Applied to Outputs
in High Z State

DC Input Voltage

Electrical Characteristics

[7]

.....................................−0.5V to V

[7]

..................................−0.5V to V

Over the Operating Range

DDQ
DDQ

+ 0.5V
+ 0.5V

Range

Com’l 0°C to +70°C 3.3V ± 5%

Ambient

Temperature

[8]

VDD/V

DDQ

Parameter Description Test Co ndit ions Min. Max. Unit

V
V
V
V
V
V
I

X

DD

DDQ
OH
OL

IH

IL

Power Supply Voltage 3.135 3.465 V
I/O Supply Voltage 3.135 3.465 V

[9]

[9]

2.4 V

0.4 V
+ 0.3V

DD

−0.3

−5

−30

0.8 V

5

30

Output HIGH Voltage VDD = Min., I

= -4.0 mA

OH

Output LOW Voltage VDD = Min., IOL = 8.0 mA
Input HIGH Voltage 2.0 V
Input LOW Voltage
Input Load Current GND ≤ VI ≤ V

[7]

DDQ

Input Current of MODE

V

µA
µA

I

I

OZ

CC

Output Leakage
Current

VDD Operating Supply V

GND ≤ VI ≤ V

= Max., I

DD

f = f

MAX

= 1/t

Output Disabled

DDQ,

= 0 mA,

OUT

CYC

7.0-ns cycle, 143 MHz 450 mA

7.5-ns cycle, 133 MHz 400 mA
10-ns cycle, 100 MHz 350 mA

12.5-ns cycle, 80 MHz 300 mA

I

SB1

Automati c C E
Power-Down
Current—TTL Inputs

Max. VDD, Device Deselected,
V

≥ VIH or VIN ≤ V

IN

f = f

MAX

= 1/t

IL

CYC

7.0-ns cycle, 143 MHz 70 mA

7.5-ns cycle, 133 MHz 60 mA
10-ns cycle, 100 MHz 50 mA

12.5-ns cycle, 80 MHz 40 mA

I

SB2

Automati c C E
Power-Down
Current—CMOS

Max. VDD, Device Deselected,
V

≤ 0.3V or VIN > V

IN

f = 0

DDQ

– 0.3V,

All speed grades 5 mA

Inputs

I

SB3

Automati c C E
Power-Down
Current—CMOS
Inputs

Max. VDD, Device D esele cte d, or
V

≤ 0.3V or VIN > V

IN

f = f

MAX

= 1/t

CYC

DDQ

– 0.3V

7.0-ns cycle, 143 MHz 60 mA

7.5-ns cycle, 133 MHz 50 mA
10-ns cycle, 100 MHz 40 mA

12.5-ns cycle, 80 MHz 30 mA

Notes:

7. Minimum voltage equals –2.0V for pulse duration less than 20 ns.

8. T

is the case temperature.

A

9. The load used for VOH and VCL testing is shown in part (b) of A/C Test Loads and Wav eforms.

−5

5

µA

6

CY7C1352

Capacitance

[10]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

V

= 3.3V.

C

CLK

C

I/O

Clock Input Capa citance 4 pF
Input/Output Capacitance 4 pF

V

DD
DDQ

= 3.3V

AC Test Loads and Waveforms

R=317

OUTPUT

3.3V

Z

=50

Ω

0

V

L

R

= 1.5V

L

=50

OUTPUT

Ω

INCLUDING

JIG AND

(a) (b)

5pF

SCOPE

Ω

R=351

1352-2

Ω

Thermal Resistance

4 pF

[11]

ALL INPUT PULSES

3.0V

GND

Description Tes t Condi ti ons Symbol TQFP Typ. Units Notes

Thermal Resistance
(Junc t ion to Ambie nt)

Still Air, soldered on a 4.25 x 1.125 i nch,
4-layer printed circuit board

Thermal Resistance
(Junction to Case)

Note:

10. Tested initially and after any design or process change that may affect these parameters.

11. A/C test conditions assume signal transition time of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading shown in
(a) of AC T e st Loads and Waveforms.

Θ

JA

Θ

JC

28 °C/W 10

4 °C/W 10

7

CY7C1352

Switching Characteristics

Over the Operating Range

[11,12,13]

-143 -133 -100 -80

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit

t

CYC

t

CH

t

CL

t

AS

t

AH

t

CO

t

DOH

t

CENS

t

CENH

t

WES

t

WEH

t

ALS

t

ALH

t

DS

t

DH

t

CES

t

CEH

t

CHZ

t

CLZ

t

EOHZ

t

EOLZ

t

EOV

Note:

12. t

CHZ

from steady-state voltage.

13. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.

14. This parameter is sampled and not 100% tested.

Clock Cycle Tim e 7.0 7.5 10 12.5 ns
Clock HIGH 2.0 2.5 3.5 4.0 ns
Clock LOW 2.0 2.5 3.5 4.0 ns
Address Set-Up Before CLK Rise 2.0 2.0 2.2 2.5 ns
Address Hold After CLK Rise 0.5 0.5 0.5 1.0 ns
Data Output Valid After CLK Rise 4.0 4.2 5.0 7.0 ns
Data Output Hold After CLK Rise 1.5 1.5 1.5 1.5 ns
CEN Set-Up Before CLK Rise 2.0 2.0 2.2 2.5 ns
CEN Hold After CLK Rise 0.5 0.5 0.5 1.0 ns
GW, BWS
GW, BWS

Set-Up Before CLK Rise 2.0 2.0 2.2 2.5 ns

[1:0]

Hold After CLK Rise 0.5 0.5 0.5 1.0 ns

[1:0]

ADV/LD Set-Up Before CLK Rise 2.0 2.0 2.2 2.5 ns
ADV/LD Hold after CLK Rise 0.5 0.5 0.5 1.0 ns
Data Input Set-Up Before CLK Rise 1.7 1.7 2.0 2.5 ns
Data Input Hold After CLK Rise 0.5 0.5 0.5 1.0 ns
Chip Enable Set-Up Before CLK Rise 2.0 2.0 2.2 2.5 ns
Chip Enable Hold After CLK Rise 0.5 0.5 0.5 1.0 ns

, and t

[10, 12, 13 , 14]

[10, 12, 13, 14]

[10, 12, 13, 14]

[10, 12, 13 , 14]

[12]

are specified with A/C test conditions shown in part (a) of AC Test Loads and waveforms. Transition is measured ± 200 mV

EOHZ

is less than t

EOHZ

EOLZ

and t

1.5 3.5 1.5 3.5 1.5 3.5 1.5 5.0 ns

1.5 1.5 1.5 1.5 ns

4.0 4.2 5.0 7.0 ns

0 0 0 0 ns

4.0 4.2 5.0 7.0 ns

is less than t

CHZ

to eliminate bus contention between SRAMs when sharing the same

CLZ

Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
OE LOW to Output Valid

, t

, t

, t

CLZ

OEV

EOLZ

8

Sw itching Wave fo rms

Read/Write/Deselect Sequence

CY7C1352

CLK

CEN

ADDRESS

WE &
BWS

[1:0]

CE

Data­In/Out

READ

RA1

t

t

WS

WH

t

Device
originally
deselected

t

t

CES

CLZ

AS

WA2

WRITE

t

AH

t

CEH

t

CO

READ

DESELECT

t

CL

t

CH

RA3 RA4

t

t

DH

1a

DS

D2

In

t

DOH

Q1

Out

Q3

Out

READ

t

1a

t

CHZ

CYC

WA5

t

CENS

RA7

D5

In

READ

SUSPEND

DESELECT

t

CENH

CEN HIGH blocks
all synchronous inputs

Q6

Out

Q7

Out

DESELECT

t

CHZ

WRITE

t

DOH

RA6

Q4

Out

READ

The combination of WE & BWS

defines a write cycle (see Write Cycle Description table).

[1:0]

CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for

Write Address X, Dx stands for Data- in for location X, Qx stands for Data -out for location X. ADV/LD
OE held LOW.

= DON’T CARE

= UNDEFINED

9

held LOW.

CY7C1352

Sw itching Wave fo rms

Burst Sequences

Begin Read

CLK

RA1

t

WH

t

ALH

t

ALS

ADV/LD

ADDRESS

WE

t

WS

(continued)

Burst Read

Burst Read

t

CH

Burst Read

t

CL

t

CYC

t

WS

t

AS

WA2

Begin Write

t

AH

t

WH

Burst Write

Burst Write

Burst Write

Begin Read

RA3

Burst Read

Burst Read

BWS

[1:0]

t

t

CES

CEH

CE

t

t

CLZ

Data­In/Out

Device
originally
deselected

The combination of WE & BWS

t

CO

t

DOH

Q1

Out

Q1+1

1a

Out

t

CO

defines a write cycle (see Write Cycle Descript ion table).

[1:0]

Q1+2

Out

CHZ

Q1+3

Out

CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for

Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN
LOW. During burst writes, byte writes can be conducte d by asserting the appropr iat e BWS

Burst order determin ed by the st ate of the MODE input. CEN

held LOW. OE held LOW.

t

DH

D2

In

t

DS

D2+1

In

D2+2

In

t

D2+3

In

held

input signals.

[1:0]

CLZ

Q3
Out

= DON’T CARE

= UNDEFINED

10

CY7C1352

Sw itching Wave fo rms

OE Timing

(continued)

OE

t

EOV

EOLZ

I/O’s

t

EOHZ

Three-state

t

Ordering Information

Speed

(MHz)

143 CY7C1352-143AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial
133 CY7C1352-133AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial
100 CY7C1352-100AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial

80 CY7C1352-80AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial

Document #: 38−00688-B

Ordering Code

Package

Name

Packag e Type

Operating

Range

11

Package Diagram

CY7C1352

100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) A101

51-85050-A

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.