Cypress Semiconductor CY7C1352-143AC, CY7C1352-133AC, CY7C1352-100AC, CY7C1352-80AC Datasheet
CY7C1352
256K x18 Pipelined SRAM with NoBL™ Architecture
Features
• Pin compatible and functionally equivalent to ZBT™
devices MCM63Z818 and MT55L256L18P
• Supports 143-MHz b us opera tions with zer o wait states
—D ata is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write Capabi li ty
• 256K x 18 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-out put times
—4.0 ns (for 143-MHz device)
—4.2 ns (for 133-MHz device)
—5.0 ns (for 100-MHz device)
—7.0 ns (for 80-MHz device)
• Clock Enable (CEN
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100-pin TQFP package
• Burst Capabi li ty—linear or interleaved burst order
) pin to suspend operation
• Low standby power
Functional Description
The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1352 is equipped with t he a dvanc ed No
Bus Latency™ (NoBL™) logic requi red to enabl e consecutiv e
Read/Write operations with data being transferred on every
clock cycle. This feat ure dramatically improves the throughput
of the SRAM, especially in systems that require frequent
Read/Write transi tions. The CY7C1352 is pin/func tionally c ompatible to ZBT™ SRAMs MCM63Z819 and MT55L256L18P.
All synchronous input s pass through i nput regi ster s control led
by the rising edge of the clock. All data outputs pass through
output regi sters controlled by the rising edge of the clock. The
clock input is qualified by the Cl ock Enable (CEN
when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is
4.0 ns (143-MHz device).
Write operations are controlled by the four Byte Write Select
(BWS
) and a Write Enable (WE) input. All writes are con-
[1:0]
ducted with on-chip synchronous self-t imed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
1
) provide for easy bank selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
) signal , which
, CE2, CE3) and an
Logic Block Diagram
CLK
ADV/LD
A
[17:0]
CEN
CE
CE
CE
WE
BWS
[1:0]
Mode
OE
D
Data-In REG.
CE
Q
18
18
CONTROL
1
2
3
and WRIT E
LOGIC
18
256Kx18
MEMORY
ARRAY
.
18
18
OUTPUT
REGISTERS
and LOGIC
CLK
18
DQ
DP
[15:0]
[1:0]
Selection G uide
7C1352-143 7C1352-133 7C1352-100 7C1352-80
Maximum Access Time (ns) 4.0 4.2 5.0 7.0
Maximum Operating Curr ent (mA) Commercial 450 400 350 300
Maximum CMOS Standby Current (mA) Commercial 5 5 5 5
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 9, 1999
Pin Configuration
100-Pin TQFP
A6A7CE1CE2NCNCBWS1BWS0CE3VDDVSSCLKWECEN
OE
CY7C1352
9
NC
ADV/LD
NC
A8A
V
V
DQ
DQ
V
DQ
DQ
V
DQ
DQ
V
NC
NC
NC
DDQ
V
NC
NC
DQ
DQ
V
DDQ
DDQ
V
V
V
DDQ
V
DP
NC
V
DDQ
NC
NC
NC
SS
SS
DD
DD
SS
SS
SS
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
8
9
10
11
10
11
12
13
CY7C1352
14
15
16
17
12
13
18
19
20
21
14
15
1
22
23
24
25
26
27
28
29
30
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
17
NC
NC
V
DDQ
V
SS
NC
DP
DQ
DQ
V
SS
V
DDQ
DQ
DQ
V
SS
VDD
V
DD
VSS
DQ
DQ
V
DDQ
V
SS
DQ
DQ
NC
NC
V
SS
V
DDQ
NC
NC
NC
0
7
6
5
4
3
2
1
0
31323334353637383940414243444546474849
A5A4A3A2A1A
MODE
0
DNU
DNU
SS
DD
V
V
DNU
DNU
10
A11A12A13A
A
15
14
A
2
50
A
16
CY7C1352
Pin Definitions
Pin Number Name I/O Description
80, 50−44,
81−82, 99−
100, 32−37
94, 93 BWS
88 WE Input-
85 ADV/LD Input-
89 CLK Input-Clock Clock input . Used to captur e all synchronous i nputs to the de vice. CLK is qua lified
98 CE
97 CE
92 CE
86 OE Input-
87 CEN Input-
23−22, 19−18,
13−12, 9−8,
73−72, 69−68,
63−62, 59−58
24, 74 DP
31 MODE Input
15, 16, 41, 65,
66, 91
4, 11, 14, 20,
27, 54, 61, 70,
77
5, 10, 17, 21,
26, 40, 55, 60,
64, 67, 71, 76,
90
A
DQ
V
V
V
[17:0]
1
2
3
[15:0]
[1:0]
DD
DDQ
SS
[1:0]
Input-
Synchronous
Input-
Synchronous
Address Inputs used to sel ect one of the 262, 144 address locat ions. Sampl ed at
the rising edge of the CLK.
Byte Write Select Input s, ac tiv e LO W. Qualified with WE to conduc t writes to t he
SRAM. Sampled on the rising edge of CLK. BWS
BWS
controls DQ
1
and DP1. See Write Cycle Description table for deta il s.
[15:8]
controls DQ
0
[7:0]
Write Enable Input, acti ve LOW. Sampled on the rising edge of CLK if CEN is
Synchronous
active LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load i npu t used t o adva nce t he on-ch ip a ddress c ounter o r load a ne w
Synchronous
address. When HIGH (and CEN
is asserted LOW) the internal b urst counter is
advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a
new address.
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
with CEN
Chip Enable 1 Input acti ve LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
Chip Enable 2 Input active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
Chip Enable 3 Input, act ive LOW. Sample d on the rising edge of CLK. Used in
conjunction with CE
. CLK is only recognized if CEN is acti ve LOW.
and CE3 to select/deselect the device.
2
and CE3 to select/deselect the device.
1
and CE2 to select/d eselect the device.
1
Output Enable, active LOW . Combined with the synchr onous logic block inside
Asynchronous
the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed t o behav e as out puts. When deasserted HIGH, I/O pins a re three-st ated,
and act as input data pins. OE
is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-
Synchronous
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN
does not deselect the device, CEN can be used to ext end the
previous cycle when required.
I/O-
Synchronous
Bidirectional Data I/O lines . As inputs , they f eed into an on-chip data regi ster that
is triggered b y the rising ed ge of CLK. As outputs , they deliv er the dat a contained
in the memory location specified by A
read cycle. The direction of t he pins is controll ed by OE
logic. When OE
DQ
three-stated during the data portion of a write sequence, duri ng the first clock
are placed in a three-state condition. The outputs are automatically
[15:0]
is asserted LOW, the pins can behave as outpu ts. When HIGH,
during the prev ious clock rise of the
[16:0]
and the internal control
when emerging from a desele cted state, and when the device is deselec ted,
I/O-
Synchronous
regardless of the state of OE
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ
trolled by BWS
. During write sequences, DP0 is controlled by BWS0 and DP1 is con-
[15:0]
1
.
Mode input. Selects the burst order of the device. Tied HIGH selects the inter-
Strap pin
leaved burst or der. Pulled LOW selects the linear burst order. MODE should not
change states during oper ation. When left flo ating, MODE wi ll defa ult HIGH t o an
interleaved burst order.
Powe r Suppl y Pow er supply inputs t o the core of the de vice. Should be c onnected to 3.3V po wer
supply.
I/O Power
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
Supply
Ground Ground for the device. Should be connected to ground of the system.
and DP0,
3
CY7C1352
Pin Definitions
(continued)
Pin Number Name I/O Description
1−3, 6−7, 25,
NC - No Connects. These pins are not connected to the int ernal device.
28−30, 51−53,
56−57, 75,
78−79, 95−96
83, 84 NC - No Connects. Reserved for address inputs for depth expansion. Pin 83 is re-
served for 512K depth and pin 84 is reserved for 1-Mb depth devices.
38, 39, 42, 43 DNU - Do Not Use pins. These pins should be left floating or ti ed to VSS.
Introduction
Functional Overview
The CY7C1352 is a synchronous-pipelined Burst SRAM designed specifically to eliminate wait states during Write-Read
transitions. All synchronous inputs pass through input registers contr olled by th e risin g edge of the c loc k. The cloc k signal
is qualifie d with t he Cloc k Enab l e input signal (CEN
HIGH, the clo c k signal is n ot reco gnize d and all i nternal states
are maintained. All synchronous operations are qualified with
CEN
. All data ou tput s pass th rough out put r egist ers contr olle d
by the rising edge of the clock. Maximum access delay from
the clock ris e (t
) is 4.0 ns (143-MHz device).
CO
Accesses can be initiated by asserting all three chip enables
(CE
, CE2, CE3) activ e at the rising edge of the clock. If Clock
1
Enable (CEN
) is active LOW and ADV/ LD is asserted LOW , the
address presented to the device will be latched. The access
can either be a read or write operation, depending on the status of the Write Enabl e (WE
byte write operat ions.
). BWS
can be used to conduct
[1:0]
Write operations are qualified by the Write Enable (WE
writes are simpl ifi ed wit h on- chi p synchr onou s self -tim ed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD
should be driven LOW once the device has been de-
selected in order to load a ne w addr ess f or the ne x t operat ion.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and (4) ADV/ LD is asserted
is asserted LOW, (2) CE1, CE2,
LOW. The address presented to the address inputs (A
is latched into the Address Register and presented to the
memory core and control logic. The control logic determines
that a read access is in progress and allows the requested
data to propagate to the input of the output register. At the
rising edge of the next clock the requested data is allowed to
propagate through the output register and onto the data bus
within 4.0 ns (143-MHz device) provided OE
After the first clock of the read access the output buffers are
controlled by OE
and the internal control logic. OE must be
driven LOW in order for the device to drive out the requested
data. During the second clock, a subsequent operation
(Read/Write/ Deselect) c an be initia ted. Desel ecting th e devic e
is also pipelined. Therefore, when the SRAM is deselected at
clock rise by one of the chip enable signals, its output will
three-state follow ing the next clock rise.
). If CEN is
). All
0−A17
is active LOW.
Burst Read Accesses
The CY7C1352 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Acce ss section abov e.
The sequence of the burst coun ter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD
the state of chip enables inputs or WE
will increment th e internal burst counter regardless of
. WE is latched at the
beginning of a burst cycle. Theref ore , the type of acces s (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initia ted when the following conditions are
satisfied at clock rise: (1) CEN
and CE
are ALL asserted active, and (3) the write si gnal WE
3
is asserted LOW. The address presented to A
into the Address Register. The write signals are latched into
is asserted LOW , (2) CE1, CE2,
0−A17
the C o ntrol Logi c block.
On the subsequent clock rise the data lines are automatically
three-stated r egardless of the s tate of the OE
input signal. This
allows the external logic to present the data on DQ
DP
. In addition, the address for the subsequent access
[1:0]
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ
DP
(or a subset for byte write operations, see Write Cycle
[1:0]
Description table for details) inputs is latched into the device
and the write is complete.
The data written during the Write operation is controlled by
BWS
)
signals. The CY7C1352 provides byte write capabi l-
[1:0]
ity that is described in the write cyc le description t able. Asserting the Write Enable input (WE
Select (BWS
) input will se lectiv el y write to onl y the des ired
[1:0]
) with the selected Byte Write
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to simple byte write operations.
Because the CY7C1352 is a common I/O device, data s hould
not be driven into the device while the outputs are active. The
Output Enable ( O E
ing data to the DQ
three-state the out put driver s . As a safe ty precau tion, DQ
and DP
tion of a write cycle, regardless of the state of OE
are automati cally three- stat ed during t he data por -
[1:0]
) can be deasserted HIGH before present -
[15:0]
and DP
inputs. Doing so will
[1:0]
is loaded
[15:0]
[15:0]
.
and
and
[15:0]
4
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