Cypress Semiconductor CY7C1351-66AC, CY7C1351-50AC, CY7C1351-40AC Datasheet

CY7C1351

128Kx36 Flow-Through SRAM with NoBL™ Architecture

Features

Pin compatible and functi onally equivalent to ZBT™ de-

•

vices IDT71V547, MT55L128L36F, and MCM63Z737

• Supports 66-MHz bus operati ons with zero wai t states
—D ata is transferred on every clock

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for Flow-Through operation

• Byte Write capabil ity

• 128K x 36 common I/O architecture

• Single 3.3V power supply

• Fast clock-to-output times
—11.0 ns (for 66-MHz device)

—12.0 ns (for 50-MHz device)
—14.0 ns (for 40-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchro nous self-timed writes

• Asynchr onous Output Enable

• JEDEC-standard 100 TQFP package

• Burst Capability—linear or interleaved burst order

Low st a ndby pow er

Logic Block Diagram

CLK

ADV/LD

[16:0]

CEN

CE
CE

CE

WE
[3:0]

17

CONTROL

1
2

3

and WRIT E

LOGIC

A

BWS

Mode

Functional Description

The CY7C1351 is a 3.3V, 128K by 36 Synchronous
Flow-Through Burst SRAM designed specifically to support
unlimited true bac k-to- back Read /Write operat ions wi thout the
insertion of wait states. The CY7C1351 is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to en­able consecut ive Read/ Write operat ions with data be ing trans ­ferred on e v ery c lock c ycle. Thi s f eat ure d ra matical ly improves
the throughput of data through the SRAM, especially in sys­tems that require frequent Write/Read transitions. The
CY7C1351 is pin/functionally compatible to ZBT SRAMs
IDT71V547, MT55L128L 36F, and MCM63Z737.

All synchronous input s pass through i nput regi ster s control led
by the rising edge of the clock.The clock input is qualified by
the Clock Enable (CEN
pends operation and extends the previous clock cycle. Maxi­mum access delay from the clock rise is 11.0 ns (66-MHz
device).

Write operations are controlled by the four Byte Write Select
(BWS

) and a Write Enable (WE) input. All writes are con-

[3:0]

ducted with on-chip synchronous self-timed write cir cuitry.
Three synchronous Chip Enables (CE

asynchronous Output Enable (OE
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.

D

Data-In REG.

CE

Q

36

128KX36

MEMORY

17

ARRAY

) signal, which when deasserted sus-

, CE2, CE3) and an

1

) provide for easy bank se-

36

36

DQ

[31:0]

DP

[3:0]

OE

.

Selection G uide

7C1351-66 7C1351-50 7C1351-40

Maximum Access Time (ns) 11.0 12.0 14.0
Maximum Operating Curr ent (mA) Commercial 250 mA 200 mA 175 mA
Maximum CMOS Standby Current (mA) Commercial 5 mA 5 mA 5 mA
NoBL and No Bus Latency are trademark s of Cypr ess Sem iconductor Corporation.

ZBT is a trademark of Integr ated Device Technology.

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 9, 1999

Pin Configuration

CY7C1351

100-Pin TQFP

DQ
DQ
V

DQ
DQ
DQ
DQ

V
DQ
DQ

V

DQ
DQ
V

DQ
DQ
DQ
DQ

V
DQ
DQ

DP

DP

DDQ

V

V

DDQ

V

V

DD
DD

V

DDQ

V

V

DDQ

SS

SS

SS

SS

SS

SS

1CE2

A6

A7

CE

BWS3BWS2BWS1BWS0CE3VDDV

9998979695949392919089

100

2
16
17

1
2
3
4
5

18
19
20
21

6
7
8
9
10
11

22
23

12
13
14
15
16
17

24
25

18
19
20
21

26
27
28
29

22
23
24
25
26
27

30
31

3

28
29
30

SS

CLK

WE

88

CY7C1351

NC

CEN

OE

NC

ADV/LD

A8A

87868584838281

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

9

DP1
DQ

15

DQ

14

V

DDQ

V

SS

DQ

13

DQ

12

DQ

11

DQ

10

V

SS

V

DDQ

DQ

9

DQ

8

V

SS

VSS
V

DD

VSS
DQ

7

DQ

6

V

DDQ

V

SS

DQ

5

DQ

4

DQ

3

DQ

2

V

SS

V

DDQ

DQ

1

DQ

0

DP0

31323334353637383940414243444546474849

A5A4A3A2A1A

MODE

0

DNU

DNU

SS

DD

V

V

DNU

DNU

10

A11A12A13A

A

15

14

A

2

50

A

16

CY7C1351

Pin Definitions

Pin Number Name I/O Description

50–44,
81–82, 99,
100, 32–37

96–93 BWS

88 WE Input-

85 ADV/LD Input-

89 CLK Input-Clock Clock Input. Used to captu re all synchron ous inputs t o the devi ce. CLK is qua lified

98 CE

97 CE

92 CE

86 OE Input-

87 CEN Input-

29–28,
25–22,
19–18,
13–12, 9–6,
3–2, 79–78,
75–72,
69–68,
63–62,
59–56, 53–52

1, 30, 51, 80 DP

31 MODE Input

15, 16, 41, 65, 91V

4, 11, 20, 27,
54, 61, 70, 77

5, 10, 14, 17,
21, 26, 40, 60,
64, 66–67,
55, 71, 76, 90

A

DQ

V

V

[16:0]

1

2

3

[31:0]

[3:0]

DD

DDQ

SS

[3:0]

Input­Synchronous

Input­Synchronous

Address Inputs used to select one of the 133,072 address locat ions. Sampled at
the rising edge of the CLK.

Byte Write Select Input s, active LOW. Qualified with WE to con duct writes to the
SRAM. Sampled on the risin g edge of CLK. BWS
controls DQ
DQ

[31:24]

and DP3.

and DP1, BWS2 controls DQ

[15:8]

controls DQ

0

and DP2, BWS0 controls

[23:16]

[7:0]

and DP0, BWS1

Write Enable Input, active LO W . Sampled on the rising edge of CLK if CEN is active

Synchronous

LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load input used to advance the on-chip address counter or load a new

Synchronous

address. When HIGH (and CEN

is asserted LOW) the internal b urst counter is
advance d. When LOW , a new address can be loaded into the de vice f or an access.
After being deselected, ADV/LD

should be driven LOW in order to load a new

address.

Input­Synchronous

Input­Synchronous

Input­Synchronous

with CEN
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE

. CLK is only recogniz ed if CEN is active LOW.

and CE3 to select/deselect the device.

2

and CE3 to select/deselect the device.

1

and CE2 to select/dese lect the device.

1

Output Enabl e, acti ve LO W . Combin ed with the s ynchronous l ogic bl ock insi de the

Asynchronous

device t o c ontrol the di rect ion of the I /O p ins. When LO W , t he I/ O pins ar e all o wed
to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE

is masked during the data portion of a write sequence,
during the f irst c lo ck whe n emer ging f r om a d eselect ed st ate and when th e de vi ce
has been deselected.

Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-

Synchronous

nized by the SRAM. When deasserted HIGH the clock signal is masked. Sinc e
deasserting CEN

does not deselect the device, CEN can be used to extend the

previous cycle when required.

I/O­Synchronous

Bidirectiona l Data I /O Lin es . As in puts, the y f eed into a n on- chip da ta regi ster that
is triggered by t he rising edge of CLK. As output s, the y deliv er the data conta ined
in the memory location specified by A
read cycle. The direction of the pins is controlled by OE
logic. When OE
DQ

are placed in a three-state condition. The outputs are aut om atically

[31:0]

is asserted LOW, the pins can behave as outputs. When HIGH,

during the previous clock rise of the

[16:0]

and the internal control

three-stated d uring the data po rtion of a write sequence, during the firs t clock when
emerging from a de sel ected st ate , and when the device is desele cted, regar dl ess

I/O­Synchronous

of the state of OE
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to

DQ
BWS

. During write s equen ces , DP0 is controlled b y BWS0, DP1 is controlled by

[31:0]

, DP2 is control l e d by BWS2, and DP3 is controlled by BWS3.

1

.

Mode Input. Selec ts the burst order of the de vice. Tied HIGH select s the interleave d

Strap pin

burst order. Pulled LOW selects the linear burst order. MODE should not change
states during operation. When left floating MODE will default HIGH, to an inter­leaved burst order.

Power Supply Power s upply i np uts t o the cor e of t he de vi ce . Sho uld be conn ected t o 3.3V po we r

supply.

I/O Power

Power supply for the I/O circuitry . Shoul d be connected to a 3.3V power supply.

Supply
Ground Ground for the device. Should be connected to ground of the system.

3

CY7C1351

Pin Definitions

(continued)

Pin Number Name I/O Description

83, 84 NC - No Connects. Reserv ed for address inputs for depth expansion. Pins 83 and 84

will be used for 256K and 512K depths respectively.

38, 39, 42, 43 DNU - Do Not Use pins. These pins should be left floating or tied to VSS.

Introduction

input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both

Functional Overview

The CY7C1351 is a Synchronous Flow-Through Burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN

). If CEN is HIGH, the cl ock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified wi th CEN
rise (t

) is 11.0 ns (66-MHz device).

CDV

. Maximum access del a y from the clock

Accesses can be init iat ed by asserting all three Chip Enables
(CE

, CE2, CE3) activ e at the rising edge of the clock. If Clock

1

Enable (CEN

) is active LOW and ADV/ LD is asserted LOW , the
address presented to the device will be latched. The access
can either be a Read or Write operation, depending on the
status of the W rite Enab le ( WE
duct byte write operations.

Write operations are qualified by the Write Enable (WE

). BWS

can be used to con-

[3:0]

). All
writes are simpl ifi ed wit h on- chi p synchr onou s self -tim ed write
circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE

, CE2, CE3) and an

1

) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD

should be driven LOW once the device has been de-

selected in order to load a ne w addr ess f or the ne x t operat ion.

Single Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN

is asserted LOW, (2) CE1, CE
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE
LOW. The address presented to the address inputs (A
is latched into the Address Register and presented to the

is deasserted HIGH, and 4) ADV/LD is asser ted

0–A16

memory core and control logic. The control logic determines
that a read access is in progress and allows the requested
data to propagate to the output buffers. The data is available
within 11.0 ns (66-MHz device) provided OE

is active LOW.
After the first clock of the read access the output buffers are
controlled by OE

and the internal control logic. OE mus t be
driven LOW in order for the device to drive out the requested
data. On the subsequent clock, another operation
(Read/Write/De select) can be initi ated. When the SRAM is de­selected at clock rise by one of the chip enable signals, its
output will three-stated immediately.

Burst Read Accesses

The CY7C1351 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/ LD
must be driven LOW in order to load a new address into the
SRAM, as de scribed in t he Singl e Read Ac cess secti on abov e.
The sequenc e of the b urst c ounter is determined b y the MODE

burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD
the state of chip enables inputs or WE

will increment the int ernal burst counter regardless o f

. WE is latched at the
beginning of a burst cycle. Theref ore , the type of acces s (Read
or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are
satisfied at cl oc k rise : (1) CEN
and CE
is asserted LOW. The address present ed to A0–A16 is loaded

are ALL asserted active, and (3) the write signal WE

3

is asserted LO W, (2) CE1, CE2,

into the Address Register. The write signals are latched into
the Control Logic block. The data lines are automatically
three-stated r egardless of the s tate of the OE

input signal. This
allows the external logic to present the data on DQ
DP

.

[3:0]

On the next clock rise the data presented to DQ
DP

(or a subset for byte write operations, see Write Cycle

[3:0]

Description table for details) inputs is latched into the device
and the write is complete. Additional accesses
(Read/Write/Dese lect) can be initiated on this cycle.

The data written during the Write operation is controlled by
BWS

signals. The CY7C1351 provides byte write capabil-

[3:0]

ity that is described in the Write Cycle Description table. As­serting the Write Enable input (WE
Write Selec t (BW S

) input will sele ctively wr ite to on ly the

[3:0]

) with the selected Byte

desired byte s. Bytes not selected during a byt e write opera tion
will remain unaltered. A synchronous self-timed write mecha­nism has been provided to simplify the write operations. Byte

2

write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim-

)

ple byte write operations.
Because the CY7C1351 is a com mo n I/O device, Data should

not be driven into the device while the out puts are active. The
Output Enable ( O E
ing data to the DQ
three-state the out put driver s . As a safe ty precau tion, DQ
and DP
tion of a write cycle, regardless of the state of OE

.are automat ical ly th ree-st ated d uring t he da ta por -

[3:0]

) can be deasserted HIGH before present-

[31:0]

and DP

inputs. Doing so will

[3:0]

Burst Write Accesses

The CY7C1351 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD

must be driven LOW in order to load the initial ad­dress, as describe d in the Single Write Acce ss secti on abov e .
When ADV/LD
the chip enables (CE
nored and the burst counter is incremented. The correct
BWS

[3:0]

is driven HIGH on the subsequent clock rise,

, CE2, and CE3) and WE inputs are ig-

1

inputs must be driven i n each cyc le of the burs t write

in order to write the correct bytes of data.

[31:0]

[31:0]

.

and

and

[31:0]

4