A
B
C
D
C
Logic Block Di
CY7C1350G
4-Mbit (128K x 36) Pipelined SRAM
with NoBL™ Architecture
Features
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Byte Write capability
• 128K x 36 common I/O architecture
• 3.3V power supply (V
• 2.5V/3.3V I/O power supply (V
DD
)
)
DDQ
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN
) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable (OE
)
• Available in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
• Burst Capability—linear or interleaved burst order
• “ZZ” Sleep mode option
agram
REGISTER 0
WRITE ADDRESS
REGISTER 1
ADDRESS
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1
A0
D0
CLK
A0, A1, A
MODE
EN
C
BURST
LOGIC
Functional Description
[1]
The CY7C1350G is a 3.3V , 128K x 36 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1350G is equipped with the advanced
No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.6 ns (250-MHz device)
Write operations are controlled by the four Byte Write Select
(BW
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
) and a Write Enable (WE) input. All writes are
[A:D]
, CE2, CE3) and an
1
) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
A1'
Q1
A0'
Q0
) signal,
ADV/LD
BW
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
A
BW
B
BW
C
BW
D
WE
OE
CE1
CE2
CE3
ZZ
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05524 Rev. *F Revised July 5, 2006
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
I
M
S
T
P
E
S
R
S
E
E
INPUT
REGISTER 0
O
D
U
T
A
P
T
U
A
T
B
S
U
T
F
E
F
E
E
R
R
S
I
E
N
G
E
DQs
DQP
DQP
DQP
DQP
[+] Feedback
CY7C1350G
Selection Guide
250 MHz 200 MHz 166 MHz 133 MHz 100 MHz Unit
Maximum Access Time 2.6 2.8 3.5 4.0 4.5 ns
Maximum Operating Current 325 265 240 225 205 mA
Maximum CMOS Standby Current 40 40 40 40 40 mA
Pin Configurations
100-Pin TQFP Pinout
BYTE C
BYTE D
DQP
DQ
DQ
V
DDQ
V
DQ
DQ
DQ
DQ
V
V
DDQ
DQ
DQ
V
NC
V
DQ
DQ
V
DDQ
V
DQ
DQ
DQ
DQ
V
V
DDQ
DQ
DQ
DQP
NC
SS
SS
DD
SS
SS
SS
1CE2
A
A
99989796959493
100
C
C
C
1
2
3
BWDBWCBWBBWACE3VDDV
CE
92
4
5
C
C
C
C
6
7
8
9
10
11
C
C
12
13
14
CY7C1350G
15
16
17
D
D
18
19
20
21
D
D
D
D
22
23
24
25
26
27
D
D
D
28
29
30
SS
CLKWECEN
OE
NC/18M
ADV/LD
NC/9M
A
A
9190898887868584838281
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
DQP
BYTE B
BYTE A
A
313233343536373839
A
A
MODE
Document #: 38-05524 Rev. *F Page 2 of 15
4041424344454647484950
A1A
0
A
A
NC/288M
NC/144M
SS
DD
V
V
NC/72M
A
NC/36M
A
A
A
A
A
A
[+] Feedback
Pin Configurations (continued)
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DDQ
NC/576M
NC/1G
DQ
DQ
V
DDQ
DQ
DQ
V
DDQ
DQ
DQ
V
DDQ
DQ
DQ
NC/144M
NC
V
DDQ
C
C
C
C
D
D
D
D
119-Ball BGA Pinout
234 5671
AA AANC/18M V
CE
2
A
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
A
NC/72M
NC
A
A
V
SS
V
SS
V
SS
BW
V
SS
V
SS
V
SS
BW
V
SS
V
SS
V
SS
MODE
A
ADV/LD
V
DD
NC DQP
CE
1
OE
NC/9M
C
WE
V
DD
CLK
D
NC
CEN
A1
A0 V
V
DD
A NC/36M
A
AANC
V
SS
V
SS
V
SS
BW
V
SS
V
SS
V
SS
BW
V
SS
V
SS
SS
NC
A
NC
B
A
CE
DQ
DQ
DQ
DQ
V
DD
DQ
DQ
DQ
DQ
DQP
NCNC NC V
CY7C1350G
DDQ
3
B
B
B
B
A
A
A
A
NC
DQ
B
A
DQ
V
DQ
DQ
V
DQ
DQ
V
DQ
DQ
B
B
DDQ
B
B
DDQ
A
A
DDQ
A
A
NC/288MA
ZZ
DDQ
Pin Definitions
Name I/O Description
A0, A1, A Input-
Synchronous
BW
[A:D]
Input-
Synchronous
WE Input-
Synchronous
ADV/LD Input-
Synchronous
CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN
CE
CE
CE
OE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CEN
Input-
Synchronous
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK. A
are fed to the two-bit burst counter.
[1:0]
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN
address can be loaded into the device for an access. After being deselected, ADV/LD
is asserted LOW) the internal burst counter is advanced. When LOW, a new
should be
driven LOW in order to load a new address.
CLK is only recognized if CEN
is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
and CE2 to select/deselect the device.
CE
1
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN
deselect the device, CEN
can be used to extend the previous cycle when required.
does not
.
Document #: 38-05524 Rev. *F Page 3 of 15
[+] Feedback
CY7C1350G
Pin Definitions (continued)
Name I/O Description
ZZ Input-
Asynchronous
DQs I/O-
Synchronous
DQP
[A:D]
I/O-
Synchronous
MODE Input
Strap pin
V
V
V
DD
DDQ
SS
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground Ground for the device.
NC No Connects. Not internally connected to the die. 9M, 18M, 36M, 72M, 144M and 288M are
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved.During normal operation, this pin has to be low or left floating. ZZ pin
has an internal pull-down.
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the address during the clock rise of the read cycle. The direction of the pins is
controlled by OE
outputs. When HIGH, DQ
cally tri-stated during the data po rtion of a write sequence, during the first clock when emerging from
and the internal control logic. When OE is asserted LOW, the pins can behave as
and DQPX are placed in a tri-state condition. The outputs are automati-
s
a deselected state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O Li nes. Functionally , these signals are identical to DQs. During write
sequences, DQP
is controlled by BW
[A:D]
correspondingly.
[A:D]
Mode Input. Selects the burst order of the device. When tied to GND selects linear burst
sequence. When tied to VDD or left floating selects interleaved burst sequence.
address expansion pins in this device and will be used as address pins in their respective densities.
Functional Overview
The CY7C1350G is a synchronous-pipelined Burst SRAM
designed specifically to eliminate wait states during
Write/Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN
). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (t
device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN
) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD
should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and (4) ADV/LD is asserted
is asserted LOW, (2) CE1, CE2,
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
) is 2.6 ns (250-MHz
CO
). BW
can be used to
[A:D]
). All
, CE2, CE3) and an
1
) simplify depth expansion.
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus, provided OE
is active LOW. After the first clock of the read access the output
buffers are controlled by OE
and the internal control logic. OE
must be driven LOW in order for the device to drive out the
requested data. During the second clock, a subsequent
operation (Read/Write/Deselect) can be initiated. Deselecting
the device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output will tri-state following the next clock rise.
Burst Read Accesses
The CY7C1350G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD
the state of chip enables inputs or WE
will increment the internal burst counter regardless of
. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address inputs
are ALL asserted active, and (3) the Write signal WE
3
is asserted LOW, (2) CE1, CE2,
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
Document #: 38-05524 Rev. *F Page 4 of 15
[+] Feedback
CY7C1350G
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
allows the external logic to present the data on DQs
DQP
(Read/Write/Deselect) is latched into the Address Register
. In addition, the address for the subsequent access
[A:D]
input signal. This
and
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQs
(or a subset for Byte Write operations, see Write Cycle
and DQP
[A:D]
Description table for details) inputs is latched into the device
and the write is complete.
The data written during the Write operation is controlled by
BW
capability that is described in the Write Cycle Description table.
signals. The CY7C1350G provides byte write
[A:D]
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW
desired bytes. Bytes not selected during a Byte Write
) input will selectively write to only the
[A:D]
operation will remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the write
operations. Byte write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple byte write operations.
Because the CY7C1350G is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE
before presenting data to the DQs
so will tri-state the output drivers. As a safety precaution, DQs
and DQP
portion of a write cycle, regardless of the state of OE
are automatically tri-stated during the data
[A:D]
) can be deasserted HIGH
and DQP
inputs. Doing
[A:D]
.
Burst Write Accesses
The CY7C1350G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD
must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE
Truth Table
[2, 3, 4, 5, 6, 7, 8]
, CE2, and CE3) and WE inputs are
1
ignored and the burst counter is incremented. The correct
BW
in order to write the correct bytes of data.
inputs must be driven in each cycle of the burst write
[A:D]
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
, CE2, and CE3, must remain inactive
1
after the ZZ input returns LOW.
ZZREC
Interleaved Burst Address Table
(MODE = Floating or V
First Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
A1, A0
DD
)
Third
Address
A1, A0
Fourth
Address
A1, A0
Linear Burst Address Table (MODE = GND)
First Address
A1, A0
Address
A1, A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Third
Address
A1, A0
Fourth
Address
A1, A0
Operation Address Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ
Deselect Cycle None H L L X X X L L-H Tri-State
Continue Deselect Cycle None X L H X X X L L-H Tri-State
Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q)
Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q)
NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State
Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State
Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D)
Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D)
Notes:
2. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. CE
signifies that the desired byte write selects are asserted, see Write Cycle Descript i on table for details.
3. Write is defined by BW
4. When a write cycle is detected, all DQs are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE
= H, inserts wait states.
6. CEN
7. Device will power-up deselected and the DQs in a tri-state condition, regardless of OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
8. OE
OE
is inactive or when the device is deselected, and DQs and DQP
, and WE. See Write Cycle Descriptions table.
X
stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signal. OE is asynchronous and is not sampled with the clock.
.
= data when OE is active.
[A:D]
= tri-state when
[A:D]
Document #: 38-05524 Rev. *F Page 5 of 15
[+] Feedback
CY7C1350G
Truth Table
[2, 3, 4, 5, 6, 7, 8]
(continued)
Operation Address Used CE
ZZ ADV/LD WE BWxOE CEN CLK DQ
NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-State
WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State
IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H —
SNOOZE MODE None X H X X X X X X Tri-State
Partial Truth Table for Read/Write
Function WE BW
[2, 3, 9]
D
BW
C
BW
B
BW
Read H X X X X
Write − No bytes written L H H H H
Write Byte A − (DQ
Write Byte B − (DQ
and DQPA) LHHHL
A
and DQPB)LHHLH
B
Write Bytes A, B L H H L L
Write Byte C − (DQ
and DQPC)LHLHH
C
Write Bytes C,A L H L H L
Write Bytes C, B L H L L H
Write Bytes C, B, A L H L L L
Write Byte D − (DQ
and DQPD)LLHHH
D
Write Bytes D, A L L H H L
Write Bytes D, B L L H L H
Write Bytes D, B, A L L H L L
Write Bytes D, C L L L H H
Write Bytes D, C, A L L L H L
Write Bytes D, C, B L L L L H
Write All Bytes L L L L L
A
ZZ Mode Electrical Characteristics
Parameter Description T est Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Note:
9. Table only lists a partial listing of the byte write combination s. Any combination of BW
Document #: 38-05524 Rev. *F Page 6 of 15
Snooze mode standby current ZZ > VDD − 0.2V 40 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to snooze current This parameter is sampled 2t
CYC
CYC
ns
ns
ns
ZZ inactive to exit snooze current This parameter is sampled 0 ns
is valid. Appropriate write will be done on which byte write is active.
X
[+] Feedback
CY7C1350G
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage on V
Supply Voltage on V
Relative to GND......... −0.5V to +4.6V
DD
Relative to GND.......−0.5V to +V
DDQ
DD
DC Voltage Applied to Outputs
in tri-state..................................................−0.5V to V
DDQ
+ 0.5V
Electrical Characteristics Over the Operating Range
DC Input Voltage....................................... −0.5V to V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range
Commercial 0°C to +70°C 3.3V – 5%
Industrial −40°C to +85°C
[10, 11]
Ambient
T emperature (TA) V
+10%
DD
+ 0.5V
DD
V
DDQ
2.5V – 5%
to V
DD
Parameter Description T est Conditions Min. Max. Unit
V
V
V
V
V
V
I
I
I
DD
DDQ
OH
OL
IH
IL
X
OZ
DD
Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage 2.375 V
Output HIGH Voltage for 3.3V I/O, I
for 2.5V I/O, I
= −4.0 mA 2.4 V
OH
= −1.0 mA 2.0 V
OH
DD
Output LOW Voltage for 3.3V I/O, IOL= 8.0 mA 0.4 V
for 2.5V I/O, I
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
[10]
V
DDQ
V
DDQ
[10]
V
DDQ
V
DDQ
GND ≤ VI ≤ V
= 3.3V 2.0 VDD + 0.3V V
= 2.5V 1.7 VDD + 0.3V V
= 3.3V –0.3 0.8 V
= 2.5V –0.3 0.7 V
except ZZ and MODE
Input Current of MODE Input = V
Input = V
Input Current of ZZ Input = V
Input = V
Output Leakage
GND ≤ VI ≤ V
Current
VDD Operating Supply
Current
V
DD
f = f
= Max., I
MAX
= 1/t
=1.0 mA 0.4 V
OL
−55µA
−30 µA
–5 µA
SS
DD
SS
DD
DDQ
Output Disabled −55µA
DDQ,
OUT
CYC
= 0 mA,
4-ns cycle, 250 MHz 325 mA
5-ns cycle, 200 MHz 265 mA
5 µA
30 µA
6-ns cycle, 166 MHz 240 mA
7.5-ns cycle, 133 MHz 225 mA
10-ns cycle, 100MHz 205 mA
I
SB1
Automatic CE
Power-Down
Current—TTL Inputs
V
= Max, Device Deselected,
DD
V
≥ VIH or VIN ≤ V
IN
f = f
MAX
= 1/t
IL
CYC
4-ns cycle, 250 MHz 120 mA
5-ns cycle, 200 MHz 110 mA
6-ns cycle, 166 MHz 100 mA
7.5-ns cycle, 133 MHz 90 mA
10-ns cycle, 100 MHz 80 mA
I
SB2
Automatic CE
Power-down
Current—CMOS
V
= Max, Device Deselected,
DD
V
≤ 0.3V or VIN > V
IN
DDQ
All speeds 40 mA
– 0.3V , f = 0
Inputs
V
Notes:
10.Overshoot: V
11. T
Power-up
(AC) < V
IH
: Assumes a linear ramp from 0V to V
+1.5V (Pulse width less than t
DD
Document #: 38-05524 Rev. *F Page 7 of 15
/2), undershoot: VIL(AC)> –2V (Pulse width less than t
CYC
(min.) within 200 ms. During this time VIH < VDD and V
DD
DDQ
< V
DD.
CYC
/2).
[+] Feedback
CY7C1350G
Electrical Characteristics Over the Operating Range
[10, 11]
(continued)
Parameter Description T est Conditions Min. Max. Unit
I
SB3
Automatic CE
Power-Down
Current—CMOS
Inputs
V
= Max, Device Deselected, or
DD
V
≤ 0.3V or VIN > V
IN
f = f
MAX
= 1/t
CYC
DDQ
– 0.3V
4-ns cycle, 250 MHz 105 mA
5-ns cycle, 200 MHz 95 mA
6-ns cycle, 166 MHz 85 mA
7.5-ns cycle, 133 MHz 75 mA
10-ns cycle, 100 MHz 65 mA
I
SB4
Capacitance
Parameter Description Test Conditions
C
Input Capacitance TA = 25°C, f = 1 MHz,
IN
C
CLK
C
I/O
Thermal Resistance
Parameter Description Test Conditions
Θ
JA
Θ
JC
Automatic CE
Power-Down
Current—TTL Inputs
[12]
V
= Max, Device Deselected,
DD
V
≥ VIH or VIN ≤ VIL, f = 0
IN
All speeds 45 mA
100 TQFP
Max.
119 BGA
Max. Unit
55pF
V
= 3.3V, V
Clock Input Capacitance 5 5 pF
DD
DDQ
= 3.3V
Input/Output Capacitance 5 7 pF
[12]
Thermal Resistance (Junction to
Ambient)
Thermal Resistance (Junction to
Case)
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
per EIA/JESD51.
100 TQFP
Package
30.32 34.1 °C/W
6.85 14.0 °C/W
119 BGA
Package Unit
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
= 50Ω
Z
2.5V I/O Test Load
OUTPUT
Z
0
0
= 50Ω
VT= 1.5V
(a)
V
T
(a)
= 1.25V
R
R
L
L
= 50Ω
= 50Ω
3.3V
OUTPUT
INCLUDING
2.5V
OUTPUT
INCLUDING
5pF
JIG AND
SCOPE
5pF
JIG AND
SCOPE
R = 317Ω
(b)
R = 1667Ω
(b)
R = 351Ω
R =1538Ω
V
V
GND
DDQ
GND
DDQ
≤ 1 ns
≤ 1 ns
ALL INPUT PULSES
10%
ALL INPUT PULSES
10%
90%
90%
90%
10%
≤ 1 ns
(c)
90%
10%
≤ 1 ns
(c)
Note:
12.Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05524 Rev. *F Page 8 of 15
[+] Feedback
CY7C1350G
Switching Characteristics Over the Operating Range
[17, 18]
–250 –200 –166 –133 –100
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
POWER
VDD (typical) to the first Access
[13]
1 1 1 1 1 ms
Clock
t
CYC
t
CH
t
CL
Clock Cycle Time 4.0 5.0 6.0 7.5 10 ns
Clock HIGH 1.7 2.0 2.5 3.0 3.5 ns
Clock LOW 1.7 2.0 2.5 3.0 3.5 ns
Output Times
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Data Output Valid After CLK Rise 2.6 2.8 3.5 4.0 4.5 ns
Data Output Hold After CLK Rise 1.0 1.0 1.5 1.5 1.5 ns
Clock to Low-Z
Clock to High-Z
[14, 15, 16]
[14, 15, 16]
0 0 0 0 0 ns
2.6 2.8 3.5 4.0 4.5 ns
OE LOW to Output Valid 2.6 2.8 3.5 4.0 4.5 ns
OE LOW to Output Low-Z
OE HIGH to Output High-Z
16]
[14, 15, 16]
[14, 15,
0 0 0 0 0 ns
2.6 2.8 3.5 4.0 4.5 ns
Set-up Times
t
AS
t
ALS
t
WES
t
CENS
t
DS
t
CES
Address Set-up Before CLK Rise 1.2 1.2 1.5 1.5 1.5 ns
ADV/LD Set-up Before CLK Rise 1.2 1.2 1.5 1.5 1.5 ns
GW, BWX Set-Up Before CLK Rise 1.2 1.2 1.5 1.5 1.5 ns
CEN Set-up Before CLK Rise 1.2 1.2 1.5 1.5 1.5 ns
Data Input Set-up Before CLK Rise 1.2 1.2 1.5 1.5 1.5 ns
Chip Enable Set-Up Before CLK
1.2 1.2 1.5 1.5 1.5 ns
Rise
Hold Times
t
AH
t
ALH
t
WEH
t
CENH
t
DH
t
CEH
Address Hold After CLK Rise 0.3 0.5 0.5 0.5 0.5 ns
ADV/LD Hold after CLK Rise 0.3 0.5 0.5 0.5 0.5 ns
GW, BWX Hold After CLK Rise 0.3 0.5 0.5 0.5 0.5 ns
Hold After CLK Rise
CEN
0.3 0.5 0.5 0.5 0.5 ns
Data Input Hold After CLK Rise 0.3 0.5 0.5 0.5 0.5 ns
Chip Enable Hold After CLK Rise 0.3 0.5 0.5 0.5 0.5 ns
Notes:
13.This part has a voltage regulator internally; t
can be initiated.
, t
14.t
CHZ
15.At any given voltage and temperature, t
data bus. These specifications do not imply a bus content ion condi tion, but refl ect parameter s guaranteed over worst case user conditions. Device is designed
to achieve tri-state prior to Low-Z under the same system conditions.
16.This parameter is sampled and not 100% tested.
17.Timing reference level is 1.5V when V
18.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
CLZ,tOELZ
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. T ransition is measured ± 20 0 mV from steady- state voltage.
OEHZ
POWER
OEHZ
= 3.3V and is 1.25V when V
DDQ
Document #: 38-05524 Rev. *F Page 9 of 15
is the time that the power needs to be supplied above VDD minimum initially before a Read or W rite operation
is less than t
OELZ
and t
is less than t
CHZ
DDQ
= 2.5V.
to eliminate bus contention between SRAMs when sharing the same
CLZ
[+] Feedback
Switching Waveforms
123456789
10
I
t
CENS
t
CES
[19, 20, 21]
t
CENH
t
CEH
Read/Write Timing
CLK
CEN
CE
ADV/LD
WE
BW
[A:D]
CY7C1350G
t
CYC
t
t
CL
CH
ADDRESS
Data
n-Out (DQ)
OE
A1 A2
t
t
AH
AS
WRITE
D(A1)
WRITE
D(A2)
A3
t
t
DH
DS
D(A1) D(A2) D(A5)Q(A4)Q(A3)
BURST
WRITE
D(A2+1)
READ
Q(A3)
A4
t
CO
t
D(A2+1)
READ
Q(A4)
CLZ
t
BURST
READ
Q(A4+1)
DOH
A5 A6 A7
t
OEHZ
t
WRITE
D(A5)
OEV
t
OELZ
t
CHZ
Q(A4+1)
t
DOH
READ
Q(A6)
DON’T CARE UNDEFINED
Notes:
For this waveform ZZ is tied LOW.
19.
20.When CE
21.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are opt ional.
is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
WRITE
D(A7)
Q(A6)
DESELECT
Document #: 38-05524 Rev. *F Page 10 of 15
[+] Feedback
Switching Waveforms (continued)
45678910
123
A
NOP, STALL, and DESELECT Cycles
CLK
CEN
CE
ADV/LD
WE
BW
[A:D]
CY7C1350G
[19, 20, 22]
ADDRESS
A1
A2
Data
In-Out (DQ)
READ
D(A1)
I
SUPPLY
[23, 24]
CLK
ZZ
ZZ Mode Timing
LL INPUTS
(except ZZ)
Q(A2)
A3 A4
D(A1) Q(A2) Q(A3)
STALL NOP READ
READ
Q(A3)
WRITE
D(A4)
STALLWRITE
A5
D(A4)
DESELECT CONTINUE
Q(A5)
DON’T CARE UNDEFINED
t
ZZ
t
ZZI
I
DDZZ
t
ZZREC
t
RZZI
DESELECT or READ Only
t
CHZ
Q(A5)
DESELECT
Outputs (Q)
Notes:
22.The IGNORE CLOCK EDG E or STALL cycle (Clock 3) illustrates CEN
23.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
24.DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05524 Rev. *F Page 11 of 15
High-Z
DON’T CARE
being used to create a pause. A write is not performed during this cycle.
[+] Feedback
CY7C1350G
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz) Ordering Code
100 CY7C1350G-100AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1350G-100BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1350G-100BGXC 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1350G-100AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
CY7C1350G-100BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1350G-100BGXI 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
133 CY7C1350G-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1350G-133BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1350G-133BGXC 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1350G-133AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
CY7C1350G-133BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1350G-133BGXI 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
166 CY7C1350G-166AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1350G-166BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1350G-166BGXC 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1350G-166AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
CY7C1350G-166BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1350G-166BGXI 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
200 CY7C1350G-200AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1350G-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1350G-200BGXC 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1350G-200AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
CY7C1350G-200BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1350G-200BGXI 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
250 CY7C1350G-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1350G-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1350G-250BGXC 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1350G-250AXI 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
CY7C1350G-250BGI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1350G-250BGXI 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
visit www.cypress.com for actual products offered.
Package
Diagram Package Type
Operating
Range
Document #: 38-05524 Rev. *F Page 12 of 15
[+] Feedback
Package Diagrams
R 0.08 MIN.
0.20 MAX.
0.25
GAUGE PLANE
0°-7°
0.60±0.15
1.00 REF.
20.00±0.10
22.00±0.20
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
14.00±0.10
100
1
30
31 50
0° MIN.
R 0.08 MIN.
0.20 MAX.
0.20 MIN.
A
DETAIL
81
80
0.30±0.08
0.65
TYP.
51
STAND-OFF
0.05 MIN.
0.15 MAX.
CY7C1350G
1.40±0.05
12°±1°
(8X)
SEATING PLANE
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
51-85050-*B
SEE DETAIL
0.20 MAX.
1.60 MAX.
0.10
A
Document #: 38-05524 Rev. *F Page 13 of 15
[+] Feedback
Package Diagrams (continued)
A1 CORNER
2165437
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
119- Ba ll BGA (14 x 22 x 2.4 mm) (51-85115)
Ø1.00(3X) REF.
1.27
19.50
20.32
22.00±0.20
10.16
CY7C1350G
Ø0.05 M C
Ø0.25MCAB
Ø0.75±0.15(119X)
2143657
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
0.70 REF.
12.00
30° TYP.
0.90±0.05
0.25 C
SEATING PLANE
C
0.56
2.40 MAX.
0.15 C
0±0.10
A
B
0.15(4X)
3.81
7.62
14.00±0.20
51-85115-*B
1.27
ZBT is a trademark of Integrated Device T echnology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor
Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05524 Rev. *F Page 14 of 15
© Cypress Semiconductor Corporation, 2006. The information contained herein i s su bj ect to ch an ge wi t hou t notice. Cypress Semiconductor Corporation assumes no responsibility for th e u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypre ss does not auth orize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
Document History Page
Document Title: CY7C1350G 4-Mbit (128K x 36) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05524
REV. ECN NO.
Date
** 224380 See ECN RKF New data sheet
*A 276690 See ECN VBL Changed TQFP pkg to lead-free TQFP in Ordering Info section
*B 332895 See ECN SYT Converted from Preliminary to Final
*C 351194 See ECN PCI Updated Ordering Information Table
*D 419264 See ECN RXU Converted from Preliminary to Final
*E 419705 See ECN RXU Added 100 MHz speed grade
*F 480368 See ECN VKN Added the Maximum Rating for Supply Voltage on V
Issue
Orig. of
Change Description of Change
Added comment of BG lead-free package availability
Removed 225 MHz and 100 MHz speed grades
Address Expansion balls in the pinouts for 119 BGA Package was modified as per
JEDEC standards
Modified V
Replaced TBDs for Θ
OL, VOH
table
test conditions
JA
Changed the package name for 100 TQFP from A100RA to A101
Removed comment on the availability of BG lead-free package
Updated Ordering Information by removing Shaded Parts
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Modified test condition from V
Modified test condition from VIH < V
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering Information
table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
Updated the Ordering Information table.
and ΘJC to their respective values on the Thermal Resistance
< V
DDQ
to V
DD
DD to VIH
DDQ
< V
< V
DD
DD
DDQ
CY7C1350G
Relative to GND.
Document #: 38-05524 Rev. *F Page 15 of 15
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